February 2016 - U-Boot

[U-Boot] [PATCH] ls2-2085a: Increase default hugepage count
by Ashish Kumar 24 Feb '16

24 Feb '16

* Increase default hugepage count to 256 from 16 * Note: default env variables are stored at 0x580200000/0x584200000 of size 0x2000 Signed-off-by: Ashish Kumar <Ashish.Kumar(a)freescale.com> --- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4ae7d11..a503934 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -272,7 +272,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" + " hugepagesz=2m hugepages=256" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 10 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 116dbcd..356d254 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -333,7 +333,7 @@ unsigned long get_board_sys_clk(void); #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0600" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" + " hugepagesz=2m hugepages=256" /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET -- 1.7.6.GIT

4 10

[U-Boot] [PATCH v2 0/2] Convert ls1021aqds to use driver model for serial ports
by York Sun 24 Feb '16

24 Feb '16

Since a recent merge 5160def "dm: lpuart: Drop the legacy code", ls1021aqds_ddr4_nor_lpuart and ls1021aqds_nor_lpuart failed to compile because they are using legacy driver for lpuart. Following ls1021atwr, ls1021aqds should be converted as well. Changes in v2: Fix default device tree name for ls1021aqds_ddr4_nor_lpuart_defconfig York Sun (2): arm: ls1021aqds: Convert to driver model and enable serial support arm: ls1021aqds: Enable driver model lpuart serial driver arch/arm/dts/Makefile | 3 ++- arch/arm/dts/ls1021a-qds-duart.dts | 16 ++++++++++++++++ arch/arm/dts/ls1021a-qds-lpuart.dts | 16 ++++++++++++++++ arch/arm/dts/{ls1021a-qds.dts => ls1021a-qds.dtsi} | 3 +-- configs/ls1021aqds_ddr4_nor_defconfig | 4 ++++ configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 4 ++++ configs/ls1021aqds_nor_defconfig | 4 ++++ configs/ls1021aqds_nor_lpuart_defconfig | 4 ++++ configs/ls1021aqds_qspi_defconfig | 2 +- configs/ls1021aqds_sdcard_defconfig | 3 +++ include/configs/ls1021aqds.h | 2 ++ 11 files changed, 57 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/ls1021a-qds-duart.dts create mode 100644 arch/arm/dts/ls1021a-qds-lpuart.dts rename arch/arm/dts/{ls1021a-qds.dts => ls1021a-qds.dtsi} (98%) -- 1.7.9.5

4 8

[U-Boot] [PATCH 1/2] net: gem: Allow to set the MAC from an EEPROM
by Michal Simek 24 Feb '16

24 Feb '16

From: Joe Hershberger <joe.hershberger(a)gmail.com> Provide board specific option how to read MAC address from ROM. Do it in generic way to be reusable by differnet boards. If this is not enough board specific functions can be created. Signed-off-by: Joe Hershberger <joe.hershberger(a)gmail.com> (driver part) Signed-off-by: Michal Simek <monstr(a)monstr.eu> --- arch/arm/mach-zynq/include/mach/sys_proto.h | 2 ++ board/xilinx/zynq/board.c | 13 +++++++++++++ drivers/net/zynq_gem.c | 18 ++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h index 882beabe132f..44c9b50fe5b8 100644 --- a/arch/arm/mach-zynq/include/mach/sys_proto.h +++ b/arch/arm/mach-zynq/include/mach/sys_proto.h @@ -19,6 +19,8 @@ extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); extern unsigned int zynq_get_silicon_version(void); +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); + /* Driver extern functions */ extern void ps7_init(void); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 2f17e977a4b3..4c20450b6359 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -98,6 +98,19 @@ int checkboard(void) } #endif +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ +#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ + defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) + if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, + ethaddr, 6)) + printf("I2C EEPROM MAC address read failed\n"); +#endif + + return 0; +} + int dram_init(void) { int node; diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index b3821c31a91d..4cfc1fadbcad 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -561,6 +561,23 @@ static void zynq_gem_halt(struct udevice *dev) ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); } +__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ + return -ENOSYS; +} + +static int zynq_gem_read_rom_mac(struct udevice *dev) +{ + int retval; + struct eth_pdata *pdata = dev_get_platdata(dev); + + retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); + if (retval == -ENOSYS) + retval = 0; + + return retval; +} + static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { @@ -634,6 +651,7 @@ static const struct eth_ops zynq_gem_ops = { .free_pkt = zynq_gem_free_pkt, .stop = zynq_gem_halt, .write_hwaddr = zynq_gem_setup_mac, + .read_rom_hwaddr = zynq_gem_read_rom_mac, }; static int zynq_gem_ofdata_to_platdata(struct udevice *dev) -- 1.9.1

1 1

[U-Boot] [PATCH] arm: socfpga: Enabling U-Boot environment support in QSPI
by Chin Liang See 24 Feb '16

24 Feb '16

Enabling the support of storing U-Boot environment within serial NOR flash. By default, its still store into SDMMC Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- include/configs/socfpga_common.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a09e906..c1eef54 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -291,6 +291,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ #endif +/* Environment for QSPI boot */ +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET 0x00100000 +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#endif + /* * mtd partitioning for serial NOR flash * -- 1.9.2.468.g3f0c02a

1 0

[U-Boot] [PATCH v2] ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
by Dongsheng Wang 24 Feb '16

24 Feb '16

From: Wang Dongsheng <dongsheng.wang(a)nxp.com> "DISCARD" will remove ._secure.text relocate, but PSCI framework has already used some absolute address those need to relocate. Use readelf -t -r u-boot show us: .__secure_start addr: 601408e4 .__secure_end addr: 60141460 60141140 00000017 R_ARM_RELATIVE 46 _secure_monitor: 47 #ifdef CONFIG_ARMV7_PSCI 48 ldr r5, =_psci_vectors 60141194 00000017 R_ARM_RELATIVE 6014119c 00000017 R_ARM_RELATIVE 601411a4 00000017 R_ARM_RELATIVE 601411ac 00000017 R_ARM_RELATIVE 64 _psci_table: 66 .word psci_cpu_suspend ... 72 .word psci_migrate 60141344 00000017 R_ARM_RELATIVE 6014145c 00000017 R_ARM_RELATIVE 202 ldr r5, =psci_text_end Solutions: 1. Change absolute address to RelAdr. Based on LDR (immediate, ARM), we only have 4K offset to jump. Now PSCI code size is close to 4K size that is LDR limit jump size, so even if the LDR is based on the current instruction address, there is also have a risk for RelAdr. If we use two jump steps I think we can fix this issue, but looks too hack, so give up this way. 2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined. If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure will in the BASE address that is absolute. Signed-off-by: Wang Dongsheng <dongsheng.wang(a)nxp.com> diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index d48a905..e148ab7 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -14,23 +14,24 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { +#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) /* - * Discard the relocation entries for secure text. - * The secure code is bundled with u-boot image, so there will - * be relocations entries for the secure code, since we use - * "-mword-relocations" to compile and "-pie" to link into the - * final image. We do not need the relocation entries for secure - * code, because secure code will not be relocated, it only needs - * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE, - * which is the linking and running address for secure code. - * If keep the relocation entries in .rel.dyn section, - * "relocation offset + linking address" may locates into an - * address that is reserved by SoC, then will trigger data abort. + * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not + * bundle with u-boot, and code offsets are fixed. Secure zone + * only needs to be copied from the loading address to + * CONFIG_ARMV7_SECURE_BASE, which is the linking and running + * address for secure code. * - * The reason that move .rel._secure at the beginning, is to - * avoid hole in the final image. + * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will + * be included in u-boot address space, and some absolute address + * were used in secure code. The absolute addresses of the secure + * code also needs to be relocated along with the accompanying u-boot + * code. + * + * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. */ /DISCARD/ : { *(.rel._secure*) } +#endif . = 0x00000000; . = ALIGN(4); -- 2.1.0.27.g96db324

3 3

[U-Boot] Please pull u-boot-sunxi master
by Hans de Goede 23 Feb '16

23 Feb '16

Hi Tom, Here is a sunxi pull-req for v2016.04, it contains some improvements for Allwinner H3 support. The following changes since commit 595af9db2422fa5ae734cfe615415b17a5098f34: Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2016-02-21 07:56:16 -0500) are available in the git repository at: http://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to dc44fd8ae4be0a88123a90ae2b3acdec45290ecf: sunxi: H3: Add support for the host usb-phys (2016-02-23 20:59:10 +0100) ---------------------------------------------------------------- Jelle van der Waa (2): sunxi: power: add support for sy8106a driver sunxi: H3: Add support for the host usb-phys arch/arm/cpu/armv7/sunxi/usb_phy.c | 35 +++++++++++++++++++++------ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 22 +++++++++++++++++ arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 ++++++ board/sunxi/Kconfig | 5 +++- board/sunxi/board.c | 5 ++++ configs/orangepi_pc_defconfig | 3 ++- configs/orangepi_plus_defconfig | 2 ++ drivers/power/Kconfig | 16 ++++++++++++ drivers/power/Makefile | 1 + drivers/power/sy8106a.c | 29 ++++++++++++++++++++++ drivers/usb/host/ehci-sunxi.c | 14 +++++------ drivers/usb/host/ohci-sunxi.c | 18 +++++++------- include/configs/sun8i.h | 6 ++++- include/configs/sunxi-common.h | 6 +++-- include/sy8106a.h | 11 +++++++++ 15 files changed, 153 insertions(+), 28 deletions(-) create mode 100644 drivers/power/sy8106a.c create mode 100644 include/sy8106a.h Regards, Hans

2 1

[U-Boot] Pull request: u-boot-video/master
by Anatolij Gustschin 23 Feb '16

23 Feb '16

Hi Tom, The following changes since commit 595af9db2422fa5ae734cfe615415b17a5098f34: Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2016-02-21 07:56:16 -0500) are available in the git repository at: git://git.denx.de/u-boot-video.git master for you to fetch changes up to 703c751169feafecb0abfd730e287986cf4ac4e1: video: Add S3C24xx framebuffer support (2016-02-22 18:07:17 +0100) ---------------------------------------------------------------- Marek Vasut (1): video: Add S3C24xx framebuffer support Simon Glass (2): video: truetype: Fix a memory leak on error video: freetype: Fix a memory leak with a bad parameter drivers/video/Makefile | 1 + drivers/video/cfb_console.c | 2 +- drivers/video/console_truetype.c | 1 + drivers/video/s3c-fb.c | 172 ++++++++++++++++++++++++++++++++++++++ drivers/video/stb_truetype.h | 5 +- 5 files changed, 179 insertions(+), 2 deletions(-) create mode 100644 drivers/video/s3c-fb.c Please pull. Thanks! -- Anatolij

2 1

[U-Boot] [GIT PULL] Xilinx fixes
by Michal Simek 23 Feb '16

23 Feb '16

Hi Tom, please pull these fixes to your tree. Below is the log from buildman for zynq platform. Microblaze build is broken by one commit I have just replied in different thread. Thanks, Michal The following changes since commit 595af9db2422fa5ae734cfe615415b17a5098f34: Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2016-02-21 07:56:16 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master for you to fetch changes up to fdcdde567c1bd4f4c4b81dc1432933d8f88feef4: ARM: zynq: Enable EDID for zybo (2016-02-22 16:37:51 +0100) ---------------------------------------------------------------- Jason Wu (1): zynq-common: Fix usbboot env variable Michal Simek (13): ARM: zynq: Remove unused SPI base addresses zynq: zc770: Remove unused ifdefs for xm011 and xm013 mmc: Kconfig: Add Arasan SDHCI entry ARM: zynq: Read memory size setting from DT ARM: zynq: Remove ZYNQ_BOOT_FREEBSD option serial: zynq: Change logic in putc ARM: zynq: Enable SPL RAM support by default dm: ns16550: Add support for reg-offset property i2c: spd: Extend SPD memory types ARM: zynq: Enable Realtek phys by default net: phy: realtek: Use generic genphy_parse_link() for RTL8211E ARM: zynq: Add reset-gpio property for USB on Zybo ARM: zynq: Enable EDID for zybo Nathan Rossi (1): ARM: zynq: Enable u-boot,dm-pre-reloc for qspi arch/arm/dts/zynq-microzed.dts | 1 + arch/arm/dts/zynq-zc706.dts | 1 + arch/arm/dts/zynq-zed.dts | 1 + arch/arm/dts/zynq-zybo.dts | 3 ++- arch/arm/include/asm/arch-zynqmp/hardware.h | 3 --- arch/arm/mach-zynq/include/mach/hardware.h | 2 -- board/xilinx/zynq/board.c | 4 ---- cmd/i2c.c | 14 +++++++++++++- configs/xilinx_zynqmp_ep_defconfig | 1 + configs/zynq_microzed_defconfig | 1 + configs/zynq_picozed_defconfig | 1 + configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + drivers/mmc/Kconfig | 6 ++++++ drivers/net/phy/realtek.c | 10 +++++++++- drivers/serial/ns16550.c | 6 ++++-- drivers/serial/serial_zynq.c | 4 ++-- include/configs/xilinx_zynqmp.h | 6 +----- include/configs/xilinx_zynqmp_ep.h | 1 - include/configs/zynq-common.h | 16 +++++++--------- include/configs/zynq_microzed.h | 4 ---- include/configs/zynq_picozed.h | 4 ---- include/configs/zynq_zc70x.h | 4 ---- include/configs/zynq_zc770.h | 11 +---------- include/configs/zynq_zed.h | 4 ---- include/configs/zynq_zybo.h | 9 +++++---- include/ns16550.h | 1 + 30 files changed, 62 insertions(+), 61 deletions(-) [u-boot]$ ./tools/buildman/buildman -b master zynq -o /tmp/ -sSed boards.cfg is up to date. Nothing to do. Summary of 16 commits for 11 boards (8 threads, 1 job per thread) 01: Merge branch 'master' of git://www.denx.de/git/u-boot-imx 02: ARM: zynq: Remove unused SPI base addresses 03: zynq: zc770: Remove unused ifdefs for xm011 and xm013 04: mmc: Kconfig: Add Arasan SDHCI entry arm: (for 10/10 boards) spl/u-boot-spl:all +21832.7 spl/u-boot-spl:bss +19674.4 spl/u-boot-spl:data +24.0 spl/u-boot-spl:rodata +371.5 spl/u-boot-spl:text +1762.8 zynq_picozed : spl/u-boot-spl:all +218327 spl/u-boot-spl:bss +196744 spl/u-boot-spl:data +240 spl/u-boot-spl:rodata +3715 spl/u-boot-spl:text +17628 05: ARM: zynq: Read memory size setting from DT 06: ARM: zynq: Remove ZYNQ_BOOT_FREEBSD option 07: serial: zynq: Change logic in putc arm: (for 10/10 boards) all +7.6 bss +3.6 spl/u-boot-spl:all +4.0 spl/u-boot-spl:text +4.0 text +4.0 zynq_zc706 : all +32 bss +28 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 zynq_zc770_xm010: all +32 bss +28 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 zynq_zc770_xm011: all +4 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 zynq_zc770_xm013: all +4 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 zynq_zc770_xm012: all +4 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 zynq_microzed : bss -4 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 zynq_zybo : bss -4 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 zynq_zc702 : bss -4 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 zynq_zed : bss -4 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 zynq_picozed : bss -4 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +4 08: ARM: zynq: Enable u-boot,dm-pre-reloc for qspi 09: ARM: zynq: Enable SPL RAM support by default arm: (for 10/10 boards) spl/u-boot-spl:all +206.4 spl/u-boot-spl:bss +7.2 spl/u-boot-spl:data +8.0 spl/u-boot-spl:rodata +4.0 spl/u-boot-spl:text +187.2 zynq_zc770_xm011: spl/u-boot-spl:all +596 spl/u-boot-spl:bss +24 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 spl/u-boot-spl:text +560 zynq_zc770_xm013: spl/u-boot-spl:all +596 spl/u-boot-spl:bss +24 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 spl/u-boot-spl:text +560 zynq_zc770_xm012: spl/u-boot-spl:all +596 spl/u-boot-spl:bss +24 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 spl/u-boot-spl:text +560 zynq_zc706 : spl/u-boot-spl:all +44 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 spl/u-boot-spl:text +32 zynq_microzed : spl/u-boot-spl:all +44 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 spl/u-boot-spl:text +32 zynq_zybo : spl/u-boot-spl:all +44 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 spl/u-boot-spl:text +32 zynq_zc702 : spl/u-boot-spl:all +44 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 spl/u-boot-spl:text +32 zynq_zc770_xm010: spl/u-boot-spl:all +44 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 spl/u-boot-spl:text +32 zynq_zed : spl/u-boot-spl:all +44 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 spl/u-boot-spl:text +32 zynq_picozed : spl/u-boot-spl:all +12 spl/u-boot-spl:data +8 spl/u-boot-spl:rodata +4 10: zynq-common: Fix usbboot env variable arm: (for 10/10 boards) all +0.2 bss -0.8 rodata +1.0 zynq_zc770_xm011: all +1 rodata +1 zynq_zc770_xm013: all +1 rodata +1 zynq_microzed : all +1 rodata +1 zynq_zybo : all +1 rodata +1 zynq_zc770_xm010: all +1 rodata +1 zynq_zed : all +1 rodata +1 zynq_zc770_xm012: all +1 rodata +1 zynq_picozed : all +1 rodata +1 zynq_zc706 : all -3 bss -4 rodata +1 zynq_zc702 : all -3 bss -4 rodata +1 11: dm: ns16550: Add support for reg-offset property 12: i2c: spd: Extend SPD memory types 13: ARM: zynq: Enable Realtek phys by default arm: (for 10/10 boards) all +1468.6 bss -0.4 data +208.0 rodata +69.0 text +1192.0 zynq_zc706 : all +1473 bss +4 data +208 rodata +69 text +1192 zynq_microzed : all +1473 bss +4 data +208 rodata +69 text +1192 zynq_zybo : all +1473 bss +4 data +208 rodata +69 text +1192 zynq_zc702 : all +1473 bss +4 data +208 rodata +69 text +1192 zynq_zed : all +1473 bss +4 data +208 rodata +69 text +1192 zynq_picozed : all +1473 bss +4 data +208 rodata +69 text +1192 zynq_zc770_xm011: all +1469 data +208 rodata +69 text +1192 zynq_zc770_xm013: all +1469 data +208 rodata +69 text +1192 zynq_zc770_xm012: all +1469 data +208 rodata +69 text +1192 zynq_zc770_xm010: all +1441 bss -28 data +208 rodata +69 text +1192 14: net: phy: realtek: Use generic genphy_parse_link() for RTL8211E arm: (for 10/10 boards) all +21.2 bss -6.8 text +28.0 zynq_zybo : all +32 bss +4 text +28 zynq_zc702 : all +32 bss +4 text +28 zynq_zc770_xm010: all +32 bss +4 text +28 zynq_zed : all +32 bss +4 text +28 zynq_zc770_xm011: all +28 text +28 zynq_zc770_xm013: all +28 text +28 zynq_zc770_xm012: all +28 text +28 zynq_zc706 : bss -28 text +28 zynq_microzed : bss -28 text +28 zynq_picozed : bss -28 text +28 15: ARM: zynq: Add reset-gpio property for USB on Zybo 16: ARM: zynq: Enable EDID for zybo arm: (for 10/10 boards) all +1144.0 bss -2.8 data +153.6 rodata +158.8 spl/u-boot-spl:all +0.4 spl/u-boot-spl:text +0.4 text +834.4 zynq_zybo : all +11440 bss -28 data +1536 rodata +1588 spl/u-boot-spl:all +4 spl/u-boot-spl:text +4 text +8344 (no errors to report) [u-boot]$ -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

2 1

[U-Boot] [PATCH 0/7] support mapping PCI device ids to stream ids for MSIs
by Stuart Yoder 23 Feb '16

23 Feb '16

From: Stuart Yoder <stuart.yoder(a)nxp.com> A binding for PCI nodes has been finalized specifying how PCI device IDs can be mapped to MSI specifiers. See Documentation/devicetree/bindings/pci/pci-msi.txt in the kernel. For ls2080a and similar Layerscape SoCs, the MSI specifier is the stream id. A programmable table (LUT) in the PCI controller defines the hardware mapping of PCI requester IDs to stream IDs. This patch series implements support for this mapping. Patch 1 removes the obsolete available-stream-id support. Patch 2 updates stream ID partitioning info to be current Patch 3 updates pci.h so pci_get_hose_head() is available Patch 4 implements support for programming the LUT Patch 5 implements a simple stream ID allocator for PCI Patch 6 implements a function to set msi-map properties Patch 7 implements a function to iterate over all PCI buses and set up a LUT entry and msi-map for all discovered devices This patch series enables MSIs on ls2080a on v4.5-rc5 and later kernels. The obsolete support removed was unused in any upstream kernels. Stuart Yoder (7): armv8: ls2080a: remove obsolete stream ID partitioning support armv8: ls2080a: update stream ID partitioning info pci: make pci_get_hose_head() available to external users pci/layerscape: add support for LUT pci/layerscape: add stream ID allocator pci/layerscape: fdt: function to set msi-map entries pci/layerscape: set LUT and msi-map for discovered PCI devices arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 113 ---------- .../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 55 +++-- drivers/pci/pcie_layerscape.c | 226 ++++++++++++++------ include/pci.h | 1 + 4 files changed, 191 insertions(+), 204 deletions(-) -- 1.7.9.5

3 11

[U-Boot] [PATCH] sunxi: H3: Add support for the host usb-phys
by Hans de Goede 23 Feb '16

23 Feb '16

From: Jelle van der Waa <jelle(a)vdwaa.nl> Add support for phy 1-3. Signed-off-by: Jelle van der Waa <jelle(a)vdwaa.nl> [hdegoede(a)redhat.com: use setclrbits_le32 instead of read-modify-write] Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- arch/arm/cpu/armv7/sunxi/usb_phy.c | 35 +++++++++++++++++++++------ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 22 +++++++++++++++++ arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 ++++++ configs/orangepi_pc_defconfig | 1 + configs/orangepi_plus_defconfig | 1 + drivers/usb/host/ehci-sunxi.c | 14 +++++------ drivers/usb/host/ohci-sunxi.c | 18 +++++++------- include/configs/sun8i.h | 6 ++++- 8 files changed, 81 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c index 19bb5a1..6ac96cc 100644 --- a/arch/arm/cpu/armv7/sunxi/usb_phy.c +++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c @@ -31,6 +31,9 @@ #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) +#define REG_PHY_UNK_H3 0x420 +#define REG_PMU_UNK_H3 0x810 + static struct sunxi_usb_phy { int usb_rst_mask; int gpio_vbus; @@ -39,19 +42,30 @@ static struct sunxi_usb_phy { int id; int init_count; int power_on_count; + int base; } sunxi_usb_phy[] = { { .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK, .id = 0, + .base = SUNXI_USB0_BASE, }, { .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, .id = 1, + .base = SUNXI_USB1_BASE, }, #if CONFIG_SUNXI_USB_PHYS >= 3 { .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, .id = 2, + .base = SUNXI_USB2_BASE, + }, +#endif +#if CONFIG_SUNXI_USB_PHYS >= 4 + { + .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK, + .id = 3, + .base = SUNXI_USB3_BASE, } #endif }; @@ -114,6 +128,15 @@ static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, } } +#if defined CONFIG_MACH_SUN8I_H3 +static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) +{ + if (phy->id == 0) + clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); + + clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02); +} +#else static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { /* The following comments are machine @@ -136,16 +159,14 @@ static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) return; } +#endif -static void sunxi_usb_phy_passby(int index, int enable) +static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable) { unsigned long bits = 0; void *addr; - if (index == 1) - addr = (void *)SUNXI_USB1_BASE + SUNXI_USB_PMU_IRQ_ENABLE; - else - addr = (void *)SUNXI_USB2_BASE + SUNXI_USB_PMU_IRQ_ENABLE; + addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE; bits = SUNXI_EHCI_AHB_ICHR8_EN | SUNXI_EHCI_AHB_INCR4_BURST_EN | @@ -181,7 +202,7 @@ void sunxi_usb_phy_init(int index) sunxi_usb_phy_config(phy); if (phy->id != 0) - sunxi_usb_phy_passby(index, SUNXI_USB_PASSBY_EN); + sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN); } void sunxi_usb_phy_exit(int index) @@ -194,7 +215,7 @@ void sunxi_usb_phy_exit(int index) return; if (phy->id != 0) - sunxi_usb_phy_passby(index, !SUNXI_USB_PASSBY_EN); + sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN); clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask); } diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 554d858..1655f10 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -229,8 +229,18 @@ struct sunxi_ccm_reg { /* ahb_gate0 offsets */ #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 +#ifdef CONFIG_MACH_SUN8I_H3 +/* + * These are EHCI1 - EHCI3 in the datasheet we call them 0 - 2 like they + * were called on older SoCs. + */ +#define AHB_GATE_OFFSET_USB_EHCI2 27 +#define AHB_GATE_OFFSET_USB_EHCI1 26 +#define AHB_GATE_OFFSET_USB_EHCI0 25 +#else #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 +#endif #define AHB_GATE_OFFSET_USB0 24 #define AHB_GATE_OFFSET_MCTL 14 #define AHB_GATE_OFFSET_GMAC 17 @@ -263,13 +273,25 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) #define CCM_USB_CTRL_PHY2_RST (0x1 << 2) +#define CCM_USB_CTRL_PHY3_RST (0x1 << 3) /* There is no global phy clk gate on sun6i, define as 0 */ #define CCM_USB_CTRL_PHYGATE 0 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) +#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) +#ifdef CONFIG_MACH_SUN8I_H3 +/* + * These are OHCI1 - OHCI3 in the datasheet we call them 0 - 2 like they + * were called on older SoCs. + */ +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#endif #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 0cdefdc..b6e11eb 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -52,10 +52,18 @@ #define SUNXI_USB2_BASE 0x01c1c000 #endif #ifdef CONFIG_SUNXI_GEN_SUN6I +#ifdef CONFIG_MACH_SUN8I_H3 +#define SUNXI_USBPHY_BASE 0x01c19000 +#define SUNXI_USB0_BASE 0x01c1a000 +#define SUNXI_USB1_BASE 0x01c1b000 +#define SUNXI_USB2_BASE 0x01c1c000 +#define SUNXI_USB3_BASE 0x01c1d000 +#else #define SUNXI_USB0_BASE 0x01c19000 #define SUNXI_USB1_BASE 0x01c1a000 #define SUNXI_USB2_BASE 0x01c1b000 #endif +#endif #define SUNXI_CSI1_BASE 0x01c1d000 #define SUNXI_TZASC_BASE 0x01c1e000 #define SUNXI_SPI3_BASE 0x01c1f000 diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 358caa5..254be90 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -12,3 +12,4 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y +CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 003a9c6..958b9fc 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -12,3 +12,4 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_CMD_GPIO=y +CONFIG_USB_EHCI_HCD=y diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index d494ca1..4d4e190 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -35,13 +35,12 @@ static int ehci_usb_probe(struct udevice *dev) * This should go away once we've moved to the driver model for * clocks resp. phys. */ - if (hccr == (void *)SUNXI_USB1_BASE) { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; - priv->phy_index = 1; - } else { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1; - priv->phy_index = 2; - } + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; +#ifdef CONFIG_MACH_SUN8I_H3 + priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0; +#endif + priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1; + priv->ahb_gate_mask <<= priv->phy_index - 1; setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); #ifdef CONFIG_SUNXI_GEN_SUN6I @@ -84,6 +83,7 @@ static const struct udevice_id ehci_usb_ids[] = { { .compatible = "allwinner,sun7i-a20-ehci", }, { .compatible = "allwinner,sun8i-a23-ehci", }, { .compatible = "allwinner,sun9i-a80-ehci", }, + { .compatible = "allwinner,sun8i-h3-ehci", }, { } }; diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index 6079272..2319b3c 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -37,15 +37,14 @@ static int ohci_usb_probe(struct udevice *dev) * This should go away once we've moved to the driver model for * clocks resp. phys. */ - if (regs == (void *)(SUNXI_USB1_BASE + 0x400)) { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; - priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; - priv->phy_index = 1; - } else { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI1; - priv->usb_gate_mask = CCM_USB_CTRL_OHCI1_CLK; - priv->phy_index = 2; - } + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; +#ifdef CONFIG_MACH_SUN8I_H3 + priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0; +#endif + priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; + priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1; + priv->ahb_gate_mask <<= priv->phy_index - 1; + priv->usb_gate_mask <<= priv->phy_index - 1; setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask); @@ -87,6 +86,7 @@ static const struct udevice_id ohci_usb_ids[] = { { .compatible = "allwinner,sun7i-a20-ohci", }, { .compatible = "allwinner,sun8i-a23-ohci", }, { .compatible = "allwinner,sun9i-a80-ohci", }, + { .compatible = "allwinner,sun8i-h3-ohci", }, { } }; diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 781ff6e..7c0ab1e 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -18,7 +18,11 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif -#define CONFIG_SUNXI_USB_PHYS 2 +#ifdef CONFIG_MACH_SUN8I_H3 + #define CONFIG_SUNXI_USB_PHYS 4 +#else + #define CONFIG_SUNXI_USB_PHYS 2 +#endif #ifndef CONFIG_MACH_SUN8I_A83T -- 2.5.0

2 2