February 2016 - U-Boot

[U-Boot] Samsung I2C driver
by Simon Glass 01 Mar '16

01 Mar '16

Hi Przemyslaw, At present this driver has a few implementations and supports non-device-tree and non-driver model. From I can see the odroid and perhaps one other platform need conversion and then all of this old stuff can be removed. Do you have any plans to look at this? Regards, Simon

3 7

[U-Boot] [PATCH] compiler*.h: sync include/linux/compiler*.h with Linux 4.5-rc6
by Tom Rini 01 Mar '16

01 Mar '16

Copy these from Linux v4.5-rc6 tag. This is needed so that we can keep up with newer gcc versions. Note that we don't have the uapi/ hierarchy from the kernel so continue to use <linux/types.h> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- include/linux/compiler-gcc.h | 259 ++++++++++++++++++++++++++++++++-------- include/linux/compiler-gcc3.h | 23 ---- include/linux/compiler-gcc4.h | 88 -------------- include/linux/compiler-gcc5.h | 65 ---------- include/linux/compiler-intel.h | 5 + include/linux/compiler.h | 178 +++++++++++++++++++++++++-- 6 files changed, 383 insertions(+), 235 deletions(-) delete mode 100644 include/linux/compiler-gcc3.h delete mode 100644 include/linux/compiler-gcc4.h delete mode 100644 include/linux/compiler-gcc5.h diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h index e057bd2..22ab246 100644 --- a/include/linux/compiler-gcc.h +++ b/include/linux/compiler-gcc.h @@ -5,14 +5,28 @@ /* * Common definitions for all gcc versions go here. */ -#define GCC_VERSION (__GNUC__ * 10000 \ - + __GNUC_MINOR__ * 100 \ - + __GNUC_PATCHLEVEL__) - +#define GCC_VERSION (__GNUC__ * 10000 \ + + __GNUC_MINOR__ * 100 \ + + __GNUC_PATCHLEVEL__) /* Optimization barrier */ + /* The "volatile" is due to gcc bugs */ #define barrier() __asm__ __volatile__("": : :"memory") +/* + * This version is i.e. to prevent dead stores elimination on @ptr + * where gcc and llvm may behave differently when otherwise using + * normal barrier(): while gcc behavior gets along with a normal + * barrier(), llvm needs an explicit input variable to be assumed + * clobbered. The issue is as follows: while the inline asm might + * access any memory it wants, the compiler could have fit all of + * @ptr into memory registers instead, and since @ptr never escaped + * from that, it proofed that the inline asm wasn't touching any of + * it. This version works well with both compilers, i.e. we're telling + * the compiler that the inline asm absolutely may see the contents + * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495 + */ +#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory") /* * This macro obfuscates arithmetic on a variable address so that gcc @@ -32,58 +46,63 @@ * the inline assembly constraint from =g to =r, in this particular * case either is valid. */ -#define RELOC_HIDE(ptr, off) \ - ({ unsigned long __ptr; \ - __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \ - (typeof(ptr)) (__ptr + (off)); }) +#define RELOC_HIDE(ptr, off) \ +({ \ + unsigned long __ptr; \ + __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \ + (typeof(ptr)) (__ptr + (off)); \ +}) /* Make the optimizer believe the variable can be manipulated arbitrarily. */ -#define OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var)) +#define OPTIMIZER_HIDE_VAR(var) \ + __asm__ ("" : "=r" (var) : "0" (var)) #ifdef __CHECKER__ -#define __must_be_array(arr) 0 +#define __must_be_array(a) 0 #else /* &a[0] degrades to a pointer: a different type from an array */ -#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) +#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) #endif /* * Force always-inline if the user requests it so via the .config, * or if gcc is too old: */ -#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ +#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4) -# define inline inline __attribute__((always_inline)) notrace -# define __inline__ __inline__ __attribute__((always_inline)) notrace -# define __inline __inline __attribute__((always_inline)) notrace +#define inline inline __attribute__((always_inline)) notrace +#define __inline__ __inline__ __attribute__((always_inline)) notrace +#define __inline __inline __attribute__((always_inline)) notrace #else /* A lot of inline functions can cause havoc with function tracing */ -# define inline inline notrace -# define __inline__ __inline__ notrace -# define __inline __inline notrace +#define inline inline notrace +#define __inline__ __inline__ notrace +#define __inline __inline notrace #endif -#define __deprecated __attribute__((deprecated)) -#ifndef __packed -#define __packed __attribute__((packed)) -#endif -#ifndef __weak -#define __weak __attribute__((weak)) -#endif +#define __always_inline inline __attribute__((always_inline)) +#define noinline __attribute__((noinline)) + +#define __deprecated __attribute__((deprecated)) +#define __packed __attribute__((packed)) +#define __weak __attribute__((weak)) +#define __alias(symbol) __attribute__((alias(#symbol))) /* - * it doesn't make sense on ARM (currently the only user of __naked) to trace - * naked functions because then mcount is called without stack and frame pointer - * being set up and there is no chance to restore the lr register to the value - * before mcount was called. + * it doesn't make sense on ARM (currently the only user of __naked) + * to trace naked functions because then mcount is called without + * stack and frame pointer being set up and there is no chance to + * restore the lr register to the value before mcount was called. + * + * The asm() bodies of naked functions often depend on standard calling + * conventions, therefore they must be noinline and noclone. * - * The asm() bodies of naked functions often depend on standard calling conventions, - * therefore they must be noinline and noclone. GCC 4.[56] currently fail to enforce - * this, so we must do so ourselves. See GCC PR44290. + * GCC 4.[56] currently fail to enforce this, so we must do so ourselves. + * See GCC PR44290. */ -#define __naked __attribute__((naked)) noinline __noclone notrace +#define __naked __attribute__((naked)) noinline __noclone notrace -#define __noreturn __attribute__((noreturn)) +#define __noreturn __attribute__((noreturn)) /* * From the GCC manual: @@ -95,34 +114,170 @@ * would be. * [...] */ -#ifndef __pure -#define __pure __attribute__((pure)) +#define __pure __attribute__((pure)) +#define __aligned(x) __attribute__((aligned(x))) +#define __printf(a, b) __attribute__((format(printf, a, b))) +#define __scanf(a, b) __attribute__((format(scanf, a, b))) +#define __attribute_const__ __attribute__((__const__)) +#define __maybe_unused __attribute__((unused)) +#define __always_unused __attribute__((unused)) + +/* gcc version specific checks */ + +#if GCC_VERSION < 30200 +# error Sorry, your compiler is too old - please upgrade it. +#endif + +#if GCC_VERSION < 30300 +# define __used __attribute__((__unused__)) +#else +# define __used __attribute__((__used__)) +#endif + +#ifdef CONFIG_GCOV_KERNEL +# if GCC_VERSION < 30400 +# error "GCOV profiling support for gcc versions below 3.4 not included" +# endif /* __GNUC_MINOR__ */ +#endif /* CONFIG_GCOV_KERNEL */ + +#if GCC_VERSION >= 30400 +#define __must_check __attribute__((warn_unused_result)) +#endif + +#if GCC_VERSION >= 40000 + +/* GCC 4.1.[01] miscompiles __weak */ +#ifdef __KERNEL__ +# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101 +# error Your version of gcc miscompiles the __weak directive +# endif +#endif + +#define __used __attribute__((__used__)) +#define __compiler_offsetof(a, b) \ + __builtin_offsetof(a, b) + +#if GCC_VERSION >= 40100 && GCC_VERSION < 40600 +# define __compiletime_object_size(obj) __builtin_object_size(obj, 0) +#endif + +#if GCC_VERSION >= 40300 +/* Mark functions as cold. gcc will assume any path leading to a call + * to them will be unlikely. This means a lot of manual unlikely()s + * are unnecessary now for any paths leading to the usual suspects + * like BUG(), printk(), panic() etc. [but let's keep them for now for + * older compilers] + * + * Early snapshots of gcc 4.3 don't support this and we can't detect this + * in the preprocessor, but we can live with this because they're unreleased. + * Maketime probing would be overkill here. + * + * gcc also has a __attribute__((__hot__)) to move hot functions into + * a special section, but I don't see any sense in this right now in + * the kernel context + */ +#define __cold __attribute__((__cold__)) + +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +#ifndef __CHECKER__ +# define __compiletime_warning(message) __attribute__((warning(message))) +# define __compiletime_error(message) __attribute__((error(message))) +#endif /* __CHECKER__ */ +#endif /* GCC_VERSION >= 40300 */ + +#if GCC_VERSION >= 40500 +/* + * Mark a position in code as unreachable. This can be used to + * suppress control flow warnings after asm blocks that transfer + * control elsewhere. + * + * Early snapshots of gcc 4.5 don't support this and we can't detect + * this in the preprocessor, but we can live with this because they're + * unreleased. Really, we need to have autoconf for the kernel. + */ +#define unreachable() __builtin_unreachable() + +/* Mark a function definition as prohibited from being cloned. */ +#define __noclone __attribute__((__noclone__)) + +#endif /* GCC_VERSION >= 40500 */ + +#if GCC_VERSION >= 40600 +/* + * When used with Link Time Optimization, gcc can optimize away C functions or + * variables which are referenced only from assembly code. __visible tells the + * optimizer that something else uses this function or variable, thus preventing + * this. + */ +#define __visible __attribute__((externally_visible)) #endif -#ifndef __aligned -#define __aligned(x) __attribute__((aligned(x))) + + +#if GCC_VERSION >= 40900 && !defined(__CHECKER__) +/* + * __assume_aligned(n, k): Tell the optimizer that the returned + * pointer can be assumed to be k modulo n. The second argument is + * optional (default 0), so we use a variadic macro to make the + * shorthand. + * + * Beware: Do not apply this to functions which may return + * ERR_PTRs. Also, it is probably unwise to apply it to functions + * returning extra information in the low bits (but in that case the + * compiler should see some alignment anyway, when the return value is + * massaged by 'flags = ptr & 3; ptr &= ~3;'). + */ +#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__))) #endif -#define __printf(a, b) __attribute__((format(printf, a, b))) -#define __scanf(a, b) __attribute__((format(scanf, a, b))) -#define noinline __attribute__((noinline)) -#define __attribute_const__ __attribute__((__const__)) -#define __maybe_unused __attribute__((unused)) -#define __always_unused __attribute__((unused)) -#define __gcc_header(x) #x -#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h) -#define gcc_header(x) _gcc_header(x) -#include gcc_header(__GNUC__) +/* + * GCC 'asm goto' miscompiles certain code sequences: + * + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 + * + * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. + * + * (asm goto is automatically volatile - the naming reflects this.) + */ +#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) + +#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP +#if GCC_VERSION >= 40400 +#define __HAVE_BUILTIN_BSWAP32__ +#define __HAVE_BUILTIN_BSWAP64__ +#endif +#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600) +#define __HAVE_BUILTIN_BSWAP16__ +#endif +#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ + +#if GCC_VERSION >= 50000 +#define KASAN_ABI_VERSION 4 +#elif GCC_VERSION >= 40902 +#define KASAN_ABI_VERSION 3 +#endif + +#if GCC_VERSION >= 40902 +/* + * Tell the compiler that address safety instrumentation (KASAN) + * should not be applied to that function. + * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 + */ +#define __no_sanitize_address __attribute__((no_sanitize_address)) +#endif + +#endif /* gcc version >= 40000 specific checks */ #if !defined(__noclone) #define __noclone /* not needed */ #endif +#if !defined(__no_sanitize_address) +#define __no_sanitize_address +#endif + /* * A trick to suppress uninitialized variable warning without generating any * code */ #define uninitialized_var(x) x = x - -#ifndef __always_inline -#define __always_inline inline __attribute__((always_inline)) -#endif diff --git a/include/linux/compiler-gcc3.h b/include/linux/compiler-gcc3.h deleted file mode 100644 index 7d89feb..0000000 --- a/include/linux/compiler-gcc3.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __LINUX_COMPILER_H -#error "Please don't include <linux/compiler-gcc3.h> directly, include <linux/compiler.h> instead." -#endif - -#if GCC_VERSION < 30200 -# error Sorry, your compiler is too old - please upgrade it. -#endif - -#if GCC_VERSION >= 30300 -# define __used __attribute__((__used__)) -#else -# define __used __attribute__((__unused__)) -#endif - -#if GCC_VERSION >= 30400 -#define __must_check __attribute__((warn_unused_result)) -#endif - -#ifdef CONFIG_GCOV_KERNEL -# if GCC_VERSION < 30400 -# error "GCOV profiling support for gcc versions below 3.4 not included" -# endif /* __GNUC_MINOR__ */ -#endif /* CONFIG_GCOV_KERNEL */ diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h deleted file mode 100644 index 2507fd2..0000000 --- a/include/linux/compiler-gcc4.h +++ /dev/null @@ -1,88 +0,0 @@ -#ifndef __LINUX_COMPILER_H -#error "Please don't include <linux/compiler-gcc4.h> directly, include <linux/compiler.h> instead." -#endif - -/* GCC 4.1.[01] miscompiles __weak */ -#ifdef __KERNEL__ -# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101 -# error Your version of gcc miscompiles the __weak directive -# endif -#endif - -#define __used __attribute__((__used__)) -#define __must_check __attribute__((warn_unused_result)) -#define __compiler_offsetof(a,b) __builtin_offsetof(a,b) - -#if GCC_VERSION >= 40100 && GCC_VERSION < 40600 -# define __compiletime_object_size(obj) __builtin_object_size(obj, 0) -#endif - -#if GCC_VERSION >= 40300 -/* Mark functions as cold. gcc will assume any path leading to a call - to them will be unlikely. This means a lot of manual unlikely()s - are unnecessary now for any paths leading to the usual suspects - like BUG(), printk(), panic() etc. [but let's keep them for now for - older compilers] - - Early snapshots of gcc 4.3 don't support this and we can't detect this - in the preprocessor, but we can live with this because they're unreleased. - Maketime probing would be overkill here. - - gcc also has a __attribute__((__hot__)) to move hot functions into - a special section, but I don't see any sense in this right now in - the kernel context */ -#define __cold __attribute__((__cold__)) - -#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) - -#ifndef __CHECKER__ -# define __compiletime_warning(message) __attribute__((warning(message))) -# define __compiletime_error(message) __attribute__((error(message))) -#endif /* __CHECKER__ */ -#endif /* GCC_VERSION >= 40300 */ - -#if GCC_VERSION >= 40500 -/* - * Mark a position in code as unreachable. This can be used to - * suppress control flow warnings after asm blocks that transfer - * control elsewhere. - * - * Early snapshots of gcc 4.5 don't support this and we can't detect - * this in the preprocessor, but we can live with this because they're - * unreleased. Really, we need to have autoconf for the kernel. - */ -#define unreachable() __builtin_unreachable() - -/* Mark a function definition as prohibited from being cloned. */ -#define __noclone __attribute__((__noclone__)) - -#endif /* GCC_VERSION >= 40500 */ - -#if GCC_VERSION >= 40600 -/* - * Tell the optimizer that something else uses this function or variable. - */ -#define __visible __attribute__((externally_visible)) -#endif - -/* - * GCC 'asm goto' miscompiles certain code sequences: - * - * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 - * - * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. - * Fixed in GCC 4.8.2 and later versions. - * - * (asm goto is automatically volatile - the naming reflects this.) - */ -#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) - -#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP -#if GCC_VERSION >= 40400 -#define __HAVE_BUILTIN_BSWAP32__ -#define __HAVE_BUILTIN_BSWAP64__ -#endif -#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600) -#define __HAVE_BUILTIN_BSWAP16__ -#endif -#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ diff --git a/include/linux/compiler-gcc5.h b/include/linux/compiler-gcc5.h deleted file mode 100644 index c8c5659..0000000 --- a/include/linux/compiler-gcc5.h +++ /dev/null @@ -1,65 +0,0 @@ -#ifndef __LINUX_COMPILER_H -#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead." -#endif - -#define __used __attribute__((__used__)) -#define __must_check __attribute__((warn_unused_result)) -#define __compiler_offsetof(a, b) __builtin_offsetof(a, b) - -/* Mark functions as cold. gcc will assume any path leading to a call - to them will be unlikely. This means a lot of manual unlikely()s - are unnecessary now for any paths leading to the usual suspects - like BUG(), printk(), panic() etc. [but let's keep them for now for - older compilers] - - Early snapshots of gcc 4.3 don't support this and we can't detect this - in the preprocessor, but we can live with this because they're unreleased. - Maketime probing would be overkill here. - - gcc also has a __attribute__((__hot__)) to move hot functions into - a special section, but I don't see any sense in this right now in - the kernel context */ -#define __cold __attribute__((__cold__)) - -#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) - -#ifndef __CHECKER__ -# define __compiletime_warning(message) __attribute__((warning(message))) -# define __compiletime_error(message) __attribute__((error(message))) -#endif /* __CHECKER__ */ - -/* - * Mark a position in code as unreachable. This can be used to - * suppress control flow warnings after asm blocks that transfer - * control elsewhere. - * - * Early snapshots of gcc 4.5 don't support this and we can't detect - * this in the preprocessor, but we can live with this because they're - * unreleased. Really, we need to have autoconf for the kernel. - */ -#define unreachable() __builtin_unreachable() - -/* Mark a function definition as prohibited from being cloned. */ -#define __noclone __attribute__((__noclone__)) - -/* - * Tell the optimizer that something else uses this function or variable. - */ -#define __visible __attribute__((externally_visible)) - -/* - * GCC 'asm goto' miscompiles certain code sequences: - * - * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 - * - * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. - * - * (asm goto is automatically volatile - the naming reflects this.) - */ -#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) - -#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP -#define __HAVE_BUILTIN_BSWAP32__ -#define __HAVE_BUILTIN_BSWAP64__ -#define __HAVE_BUILTIN_BSWAP16__ -#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h index ba147a1..d4c7113 100644 --- a/include/linux/compiler-intel.h +++ b/include/linux/compiler-intel.h @@ -13,9 +13,14 @@ /* Intel ECC compiler doesn't support gcc specific asm stmts. * It uses intrinsics to do the equivalent things. */ +#undef barrier +#undef barrier_data #undef RELOC_HIDE #undef OPTIMIZER_HIDE_VAR +#define barrier() __memory_barrier() +#define barrier_data(ptr) barrier() + #define RELOC_HIDE(ptr, off) \ ({ unsigned long __ptr; \ __ptr = (unsigned long) (ptr); \ diff --git a/include/linux/compiler.h b/include/linux/compiler.h index d5ad7b1..020ad16 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -17,6 +17,7 @@ # define __release(x) __context__(x,-1) # define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0) # define __percpu __attribute__((noderef, address_space(3))) +# define __pmem __attribute__((noderef, address_space(5))) #ifdef CONFIG_SPARSE_RCU_POINTER # define __rcu __attribute__((noderef, address_space(4))) #else @@ -42,6 +43,7 @@ extern void __chk_io_ptr(const volatile void __iomem *); # define __cond_lock(x,c) (c) # define __percpu # define __rcu +# define __pmem #endif /* Indirect macros required for expanded argument pasting, eg. __LINE__. */ @@ -54,7 +56,11 @@ extern void __chk_io_ptr(const volatile void __iomem *); #include <linux/compiler-gcc.h> #endif +#if defined(CC_USING_HOTPATCH) && !defined(__CHECKER__) +#define notrace __attribute__((hotpatch(0,0))) +#else #define notrace __attribute__((no_instrument_function)) +#endif /* Intel compiler defines __GNUC__. So we will overwrite implementations * coming from above header files here @@ -138,7 +144,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); */ #define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) ) #define __trace_if(cond) \ - if (__builtin_constant_p((cond)) ? !!(cond) : \ + if (__builtin_constant_p(!!(cond)) ? !!(cond) : \ ({ \ int ______r; \ static struct ftrace_branch_data \ @@ -165,6 +171,10 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); # define barrier() __memory_barrier() #endif +#ifndef barrier_data +# define barrier_data(ptr) barrier() +#endif + /* Unreachable code */ #ifndef unreachable # define unreachable() do { } while (1) @@ -186,6 +196,126 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); # define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__) #endif +#include <linux/types.h> + +#define __READ_ONCE_SIZE \ +({ \ + switch (size) { \ + case 1: *(__u8 *)res = *(volatile __u8 *)p; break; \ + case 2: *(__u16 *)res = *(volatile __u16 *)p; break; \ + case 4: *(__u32 *)res = *(volatile __u32 *)p; break; \ + case 8: *(__u64 *)res = *(volatile __u64 *)p; break; \ + default: \ + barrier(); \ + __builtin_memcpy((void *)res, (const void *)p, size); \ + barrier(); \ + } \ +}) + +static __always_inline +void __read_once_size(const volatile void *p, void *res, int size) +{ + __READ_ONCE_SIZE; +} + +#ifdef CONFIG_KASAN +/* + * This function is not 'inline' because __no_sanitize_address confilcts + * with inlining. Attempt to inline it may cause a build failure. + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 + * '__maybe_unused' allows us to avoid defined-but-not-used warnings. + */ +static __no_sanitize_address __maybe_unused +void __read_once_size_nocheck(const volatile void *p, void *res, int size) +{ + __READ_ONCE_SIZE; +} +#else +static __always_inline +void __read_once_size_nocheck(const volatile void *p, void *res, int size) +{ + __READ_ONCE_SIZE; +} +#endif + +static __always_inline void __write_once_size(volatile void *p, void *res, int size) +{ + switch (size) { + case 1: *(volatile __u8 *)p = *(__u8 *)res; break; + case 2: *(volatile __u16 *)p = *(__u16 *)res; break; + case 4: *(volatile __u32 *)p = *(__u32 *)res; break; + case 8: *(volatile __u64 *)p = *(__u64 *)res; break; + default: + barrier(); + __builtin_memcpy((void *)p, (const void *)res, size); + barrier(); + } +} + +/* + * Prevent the compiler from merging or refetching reads or writes. The + * compiler is also forbidden from reordering successive instances of + * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the + * compiler is aware of some particular ordering. One way to make the + * compiler aware of ordering is to put the two invocations of READ_ONCE, + * WRITE_ONCE or ACCESS_ONCE() in different C statements. + * + * In contrast to ACCESS_ONCE these two macros will also work on aggregate + * data types like structs or unions. If the size of the accessed data + * type exceeds the word size of the machine (e.g., 32 bits or 64 bits) + * READ_ONCE() and WRITE_ONCE() will fall back to memcpy and print a + * compile-time warning. + * + * Their two major use cases are: (1) Mediating communication between + * process-level code and irq/NMI handlers, all running on the same CPU, + * and (2) Ensuring that the compiler does not fold, spindle, or otherwise + * mutilate accesses that either do not require ordering or that interact + * with an explicit memory barrier or atomic instruction that provides the + * required ordering. + */ + +#define __READ_ONCE(x, check) \ +({ \ + union { typeof(x) __val; char __c[1]; } __u; \ + if (check) \ + __read_once_size(&(x), __u.__c, sizeof(x)); \ + else \ + __read_once_size_nocheck(&(x), __u.__c, sizeof(x)); \ + __u.__val; \ +}) +#define READ_ONCE(x) __READ_ONCE(x, 1) + +/* + * Use READ_ONCE_NOCHECK() instead of READ_ONCE() if you need + * to hide memory access from KASAN. + */ +#define READ_ONCE_NOCHECK(x) __READ_ONCE(x, 0) + +#define WRITE_ONCE(x, val) \ +({ \ + union { typeof(x) __val; char __c[1]; } __u = \ + { .__val = (__force typeof(x)) (val) }; \ + __write_once_size(&(x), __u.__c, sizeof(x)); \ + __u.__val; \ +}) + +/** + * smp_cond_acquire() - Spin wait for cond with ACQUIRE ordering + * @cond: boolean expression to wait for + * + * Equivalent to using smp_load_acquire() on the condition variable but employs + * the control dependency of the wait to reduce the barrier on many platforms. + * + * The control dependency provides a LOAD->STORE order, the additional RMB + * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order, + * aka. ACQUIRE. + */ +#define smp_cond_acquire(cond) do { \ + while (!(cond)) \ + cpu_relax(); \ + smp_rmb(); /* ctrl + rmb := acquire */ \ +} while (0) + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ @@ -304,6 +434,14 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); #define __visible #endif +/* + * Assume alignment of return value. + */ +#ifndef __assume_aligned +#define __assume_aligned(a, ...) +#endif + + /* Are two types/vars the same type (ignoring qualifiers)? */ #ifndef __same_type # define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) @@ -311,7 +449,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); /* Is this type a native word size -- useful for atomic operations */ #ifndef __native_word -# define __native_word(t) (sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long)) +# define __native_word(t) (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long)) #endif /* Compile time object size, -1 for unknown */ @@ -373,12 +511,38 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); * to make the compiler aware of ordering is to put the two invocations of * ACCESS_ONCE() in different C statements. * - * This macro does absolutely -nothing- to prevent the CPU from reordering, - * merging, or refetching absolutely anything at any time. Its main intended - * use is to mediate communication between process-level code and irq/NMI - * handlers, all running on the same CPU. + * ACCESS_ONCE will only work on scalar types. For union types, ACCESS_ONCE + * on a union member will work as long as the size of the member matches the + * size of the union and the size is smaller than word size. + * + * The major use cases of ACCESS_ONCE used to be (1) Mediating communication + * between process-level code and irq/NMI handlers, all running on the same CPU, + * and (2) Ensuring that the compiler does not fold, spindle, or otherwise + * mutilate accesses that either do not require ordering or that interact + * with an explicit memory barrier or atomic instruction that provides the + * required ordering. + * + * If possible use READ_ONCE()/WRITE_ONCE() instead. + */ +#define __ACCESS_ONCE(x) ({ \ + __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \ + (volatile typeof(x) *)&(x); }) +#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x)) + +/** + * lockless_dereference() - safely load a pointer for later dereference + * @p: The pointer to load + * + * Similar to rcu_dereference(), but for situations where the pointed-to + * object's lifetime is managed by something other than RCU. That + * "something other" might be reference counting or simple immortality. */ -#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) +#define lockless_dereference(p) \ +({ \ + typeof(p) _________p1 = READ_ONCE(p); \ + smp_read_barrier_depends(); /* Dependency order vs. p above. */ \ + (_________p1); \ +}) /* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */ #ifdef CONFIG_KPROBES -- 1.7.9.5

1 1

[U-Boot] [PATCH] arm: dra7xx: Define Android partition table
by Semen Protsenko 01 Mar '16

01 Mar '16

From: Sam Protsenko <semen.protsenko(a)linaro.org> "fastboot oem format" command reuses "gpt write" command, which in turn requires correct partitions defined in $partitions variable. This patch adds such definition of Android partitions for DRA7XX EVM board. By default $partitions variable contains Linux partition table. In order to prepare Android environment one can run next commands from U-Boot shell: => env set partitions $partitions_android => env save After those operations one can go to fastboot mode and perform "fastboot oem format" to create Android partition table. While at it, enable CONFIG_RANDOM_UUID to spare user from providing UUIDs for each partition manually. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- include/configs/dra7xx_evm.h | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 4658283..0196280 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -44,8 +44,25 @@ #ifndef CONFIG_SPL_BUILD /* Define the default GPT table for eMMC */ #define PARTS_DEFAULT \ + /* Linux partitions */ \ "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + /* Android partitions */ \ + "partitions_android=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=xloader,start=128K,size=128K,uuid=${uuid_gpt_xloader};" \ + "name=bootloader,size=384K,uuid=${uuid_gpt_bootloader};" \ + "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ + "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ + "name=efs,start=1280K,size=16M,uuid=${uuid_gpt_efs};" \ + "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \ + "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \ + "name=boot,size=10M,uuid=${uuid_gpt_boot};" \ + "name=system,size=768M,uuid=${uuid_gpt_system};" \ + "name=cache,size=256M,uuid=${uuid_gpt_cache};" \ + "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \ + "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \ + "name=userdata,size=-,uuid=${uuid_gpt_userdata}" #define DFU_ALT_INFO_MMC \ "dfu_alt_info_mmc=" \ @@ -116,6 +133,7 @@ /* Enhance our eMMC support / experience. */ #define CONFIG_CMD_GPT #define CONFIG_EFI_PARTITION +#define CONFIG_RANDOM_UUID #define CONFIG_HSMMC2_8BIT /* CPSW Ethernet */ -- 2.7.0

2 2

[U-Boot] [PATCH] sniper: Various minor cleanups, missing Kconfig configs and reorganisation
by Paul Kocialkowski 01 Mar '16

01 Mar '16

This introduces some minor cleanups, regarding aspects such as board name, code and headers organization as well as deprecated and missing config options. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- arch/arm/cpu/armv7/omap3/Kconfig | 2 +- board/lge/sniper/sniper.c | 24 +- board/lge/sniper/sniper.h | 638 +++++++++++++++++++-------------------- configs/sniper_defconfig | 5 +- include/configs/sniper.h | 11 +- 5 files changed, 339 insertions(+), 341 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 652d319..c6168e9 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -110,7 +110,7 @@ config TARGET_OMAP3_CAIRO select DM_GPIO config TARGET_SNIPER - bool "Sniper" + bool "LG Optimus Black" select SUPPORT_SPL select DM select DM_SERIAL diff --git a/board/lge/sniper/sniper.c b/board/lge/sniper/sniper.c index d0e7d66..f093f97 100644 --- a/board/lge/sniper/sniper.c +++ b/board/lge/sniper/sniper.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; const omap3_sysinfo sysinfo = { .mtype = DDR_STACKED, - .board_string = "Sniper", + .board_string = "sniper", .nand_string = "MMC" }; @@ -58,6 +58,11 @@ static struct musb_hdrc_platform_data musb_platform_data = { .board_data = &musb_board_data, }; +void set_muxconf_regs(void) +{ + MUX_SNIPER(); +} + #ifdef CONFIG_SPL_BUILD void get_board_mem_timings(struct board_sdrc_timings *timings) { @@ -69,12 +74,6 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) } #endif -u32 get_board_rev(void) -{ - /* Sold devices are expected to be at least revision F. */ - return 6; -} - int board_init(void) { /* GPMC init */ @@ -147,6 +146,12 @@ int misc_init_r(void) return 0; } +u32 get_board_rev(void) +{ + /* Sold devices are expected to be at least revision F. */ + return 6; +} + void get_board_serial(struct tag_serialnr *serialnr) { omap_die_id_get_board_serial(serialnr); @@ -162,11 +167,6 @@ int fb_set_reboot_flag(void) return omap_reboot_mode_store('b'); } -void set_muxconf_regs(void) -{ - MUX_SNIPER(); -} - #ifndef CONFIG_SPL_BUILD int board_mmc_init(bd_t *bis) { diff --git a/board/lge/sniper/sniper.h b/board/lge/sniper/sniper.h index 01ab301..0f81c43 100644 --- a/board/lge/sniper/sniper.h +++ b/board/lge/sniper/sniper.h @@ -13,353 +13,353 @@ #define MUX_SNIPER() \ /* SDRC */ \ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */ \ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* sdrc_d0 */\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* sdrc_d1 */\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* sdrc_d2 */\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* sdrc_d3 */\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* sdrc_d4 */\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* sdrc_d5 */\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* sdrc_d6 */\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* sdrc_d7 */\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* sdrc_d8 */\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* sdrc_d9 */\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* sdrc_d10 */\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* sdrc_d11 */\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* sdrc_d12 */\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* sdrc_d13 */\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* sdrc_d14 */\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* sdrc_d15 */\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* sdrc_d16 */\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* sdrc_d17 */\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* sdrc_d18 */\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* sdrc_d19 */\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* sdrc_d20 */\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* sdrc_d21 */\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* sdrc_d22 */\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* sdrc_d23 */\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* sdrc_d24 */\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* sdrc_d25 */\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* sdrc_d26 */\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* sdrc_d27 */\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* sdrc_d28 */\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* sdrc_d29 */\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* sdrc_d30 */\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* sdrc_d31 */\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* sdrc_clk */\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* sdrc_dqs0 */\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* sdrc_dqs1 */\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* sdrc_dqs2 */\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* sdrc_dqs3 */ \ /* GPMC */ \ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* GPIO_34: LCD_RESET_N */ \ - MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* GPIO_35: TOUCH_INT_N */ \ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* GPIO_36: VT_CAM_PWDN */ \ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* GPIO_37: CAM_SUBPM_EN */\ - MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* GPIO_38: MODEM_PWR_CHK */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* GPIO_39: MODEM_WAKE */\ - MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* GPIO_40: MUIC_INT_N */\ - MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* GPIO_41: GYRO_INT_N */\ - MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* GPIO_42: MOTION_INT_N */\ - MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* GPIO_43: BT_HOST_WAKEUP */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */ \ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */ \ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */ \ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */ \ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */ \ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */ \ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */ \ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */ \ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */ \ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */ \ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */ \ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */ \ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */ \ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */ \ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */ \ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* gpio_34 */ \ + MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* gpio_35 */ \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* gpio_36 */ \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* gpio_37 */\ + MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* gpio_38 */\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* gpio_39 */\ + MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* gpio_40 */\ + MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* gpio_41 */\ + MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* gpio_42 */\ + MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* gpio_43 */\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* gpmc_d0 */ \ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* gpmc_d1 */ \ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* gpmc_d2 */ \ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* gpmc_d3 */ \ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* gpmc_d4 */ \ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* gpmc_d5 */ \ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* gpmc_d6 */ \ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* gpmc_d7 */ \ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* gpmc_d8 */ \ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* gpmc_d9 */ \ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* gpmc_d10 */ \ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* gpmc_d11 */ \ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* gpmc_d12 */ \ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* gpmc_d13 */ \ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* gpmc_d14 */ \ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTD | DIS | M4)) /* GPIO_52: BT_WAKE_UP */ \ - MUX_VAL(CP(GPMC_NCS2), (IEN | PTD | DIS | M4)) /* GPIO_53: LCD_TE */ \ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54: LCD_CS */ \ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /* GPIO_55: BT_MAKER_ID */ \ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M3)) /* GPIO_56: VIBE_PWM */ \ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /* GPIO_57: VIBE_EN */ \ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | DIS | M4)) /* GPIO_58: COM_INT */ \ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTD | DIS | M4)) /* gpio_52 */ \ + MUX_VAL(CP(GPMC_NCS2), (IEN | PTD | DIS | M4)) /* gpio_53 */ \ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* gpio_54 */ \ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /* gpio_55 */ \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M3)) /* gpio_56 */ \ + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /* gpio_57 */ \ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | DIS | M4)) /* gpio_58 */ \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* safe_mode */ \ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M4)) /* GPIO_60: PROXI_LDO_EN */ \ - MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /* GPIO_61: VT_RESET_N */ \ - MUX_VAL(CP(GPMC_NWP), (IDIS | PTD | DIS | M4)) /* GPIO_62: LCD_CP_EN */ \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M4)) /* gpio_60 */ \ + MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /* gpio_61 */ \ + MUX_VAL(CP(GPMC_NWP), (IDIS | PTD | DIS | M4)) /* gpio_62 */ \ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTD | DIS | M4)) /* GPIO_63: ONENAND_INT */ \ - MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M2)) /* GPIO_64: UART4_TX_IPC */ \ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M2)) /* GPIO_65: UART4_RX_IPC */ \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTD | DIS | M4)) /* gpio_63 */ \ + MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M2)) /* gpio_64 */ \ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M2)) /* gpio_65 */ \ /* DSS */ \ - MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* DSI_DX0 */ \ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* DSI_DY0 */ \ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* DSI_DX1 */ \ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* DSI_DY1 */ \ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* DSI_DX2 */ \ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* DSI_DY2 */ \ - MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M4)) /* GPIO_87: MIC_SEL */ \ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* dsi_dx0 */ \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* dsi_dy0 */ \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* dsi_dx1 */ \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* dsi_dy1 */ \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* dsi_dx2 */ \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* dsi_dy2 */ \ + MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M4)) /* gpio_87 */ \ + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)) /* safe_mode */ \ /* CAM */ \ - MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M0)) /* CAM_HS */ \ - MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* CAM_VS */ \ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* CAM_XCLKA */ \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* CAM_PCLK */ \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* GPIO_98: 5M_RESET_N */ \ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* CSI2_DX2 */ \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* CSI2_DY2 */ \ - MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* GPIO_101: IFX_USB_VBUS_EN */ \ - MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /* CAM_D4 */ \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /* CAM_D5 */ \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /* CAM_D6 */ \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /* CAM_D7 */ \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /* CAM_D8 */ \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /* CAM_D9 */ \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /* CAM_D10 */ \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /* CAM_D11 */ \ - MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /* CAM_XCLKB */ \ - MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /* GPIO_167: 5M_CAM_VCN_EN */ \ - MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M0)) /* cam_hs */ \ + MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M0)) /* cam_vs */ \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /* cam_xclka */ \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M0)) /* cam_pclk */ \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* gpio_98 */ \ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* csi2_dx2 */ \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* csi2_dy2 */ \ + MUX_VAL(CP(CAM_D2), (IDIS | PTD | EN | M4)) /* gpio_101 */ \ + MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /* cam_d4 */ \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /* cam_d5 */ \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /* cam_d6 */ \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /* cam_d7 */ \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /* cam_d8 */ \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /* cam_d9 */ \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /* cam_d10 */ \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /* cam_d11 */ \ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /* cam_xclkb */ \ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /* gpio_167 */ \ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M7)) /* safe_mode */ \ /* CSI2 */ \ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /* CSI2_DX0 */ \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /* CSI2_DY0 */ \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /* CSI2_DX1 */ \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /* CSI2_DY1 */ \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /* csi2_dx0 */ \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /* csi2_dy0 */ \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /* csi2_dx1 */ \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /* csi2_dy1 */ \ /* MCBSP2 */ \ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* MCBSP2_FSX */ \ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP2_CLKX */ \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* MCBSP2_DR */ \ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* MCBSP2_DX */ \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* mcbsp2_fsx */ \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp2_clkx */ \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* mcbsp2_dr */ \ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* mcbsp2_dx */ \ /* MMC1 */ \ - MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* MMC1_CLK */ \ - MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* MMC1_CMD */ \ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* MMC1_DAT0 */ \ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* MMC1_DAT1 */ \ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* MMC1_DAT2 */ \ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* MMC1_DAT3 */ \ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(MMC1_CLK), (IEN | PTD | DIS | M0)) /* mmc1_clk */ \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTD | DIS | M0)) /* mmc1_cmd */ \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTD | DIS | M0)) /* mmc1_dat0 */ \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTD | DIS | M0)) /* mmc1_dat1 */ \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTD | DIS | M0)) /* mmc1_dat2 */ \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTD | DIS | M0)) /* mmc1_dat3 */ \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | DIS | M7)) /* safe_mode */ \ /* MMC2 */ \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /* MMC2_CLK */ \ - MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) /* MMC2_CMD */ \ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) /* MMC2_DAT0 */ \ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) /* MMC2_DAT1 */ \ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) /* MMC2_DAT2 */ \ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) /* MMC2_DAT3 */ \ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0)) /* MMC2_DAT4 */ \ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0)) /* MMC2_DAT5 */ \ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0)) /* MMC2_DAT6 */ \ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0)) /* MMC2_DAT7 */ \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /* mmc2_clk */ \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) /* mmc2_cmd */ \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) /* mmc2_dat0 */ \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) /* mmc2_dat1 */ \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) /* mmc2_dat2 */ \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) /* mmc2_dat3 */ \ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0)) /* mmc2_dat4 */ \ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0)) /* mmc2_dat5 */ \ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0)) /* mmc2_dat6 */ \ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0)) /* mmc2_dat7 */ \ /* MCBSP3 */ \ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /* MCBSP3_DX */ \ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /* MCBSP3_DR */ \ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* MCBSP3_CLKX */ \ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* MCBSP3_FSX */ \ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /* mcbsp3_dx */ \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /* mcbsp3_dr */ \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /* mcbsp3_clkx */ \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /* mcbsp3_fsx */ \ /* UART2 */ \ - MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* UART2_CTS */ \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* UART2_RTS */ \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* UART2_TX */ \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* UART2_RX */ \ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M0)) /* uart2_cts */ \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /* uart2_rts */ \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /* uart2_tx */ \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /* uart2_rx */ \ /* UART1 */ \ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */ \ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* UART1_RTS */ \ - MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* UART1_CTS */ \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ \ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* uart1_tx */ \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* uart1_rts */ \ + MUX_VAL(CP(UART1_CTS), (IEN | PTD | DIS | M0)) /* uart1_cts */ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* uart1_rx */ \ /* MCBSP4 */ \ - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_152: GPS_PWR_ON */ \ - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* GPIO_153: GPS_RESET_N */ \ - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /* GPIO_154: FLASH_LED_TORCH */ \ - MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /* GPIO_155: FLASH_LED_EN */ \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_152 */ \ + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /* gpio_153 */ \ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /* gpio_154 */ \ + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /* gpio_155 */ \ /* MCBSP1 */ \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /* MCBSP1_CLKR */ \ - MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /* MCBSP1_FSR */ \ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /* MCBSP1_DX */ \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /* MCBSP1_DR */ \ - MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /* GPIO_161: OMAP_UART_SW */ \ - MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /* GPIO_162: IFX_UART_SW */ \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /* mcbsp1_clkr */ \ + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /* mcbsp1_fsr */ \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /* mcbsp1_dx */ \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /* mcbsp1_dr */ \ + MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /* gpio_161 */ \ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /* gpio_162 */ \ /* UART3 */ \ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /* GPIO_163: HOOK_DIG */ \ - MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX_IRRX */ \ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX_IRTX */ \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /* gpio_163 */ \ + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* uart3_rx_irrx */ \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* uart3_tx_irtx */ \ /* HSUSB0 */ \ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M0)) /* HSUSB0_CLK */\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTD | DIS | M0)) /* HSUSB0_STP */\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M0)) /* HSUSB0_DIR */\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M0)) /* HSUSB0_NXT */\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M0)) /* HSUSB0_DATA0 */\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M0)) /* HSUSB0_DATA1 */\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M0)) /* HSUSB0_DATA2 */\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M0)) /* HSUSB0_DATA3 */\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M0)) /* HSUSB0_DATA4 */\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M0)) /* HSUSB0_DATA5 */\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M0)) /* HSUSB0_DATA6 */\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M0)) /* HSUSB0_DATA7 */ \ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M0)) /* hsusb0_clk */\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTD | DIS | M0)) /* hsusb0_stp */\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M0)) /* hsusb0_dir */\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M0)) /* hsusb0_nxt */\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M0)) /* hsusb0_data0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M0)) /* hsusb0_data1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M0)) /* hsusb0_data2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M0)) /* hsusb0_data3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M0)) /* hsusb0_data4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M0)) /* hsusb0_data5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M0)) /* hsusb0_data6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M0)) /* hsusb0_data7 */ \ /* I2C1 */ \ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */ \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */ \ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* i2c1_scl */ \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* i2c1_sda */ \ /* I2C2 */ \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* I2C2_SCL */ \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* I2C2_SDA */ \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTD | DIS | M0)) /* i2c2_scl */ \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTD | DIS | M0)) /* i2c2_sda */ \ /* I2C3 */ \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* I2C3_SCL */ \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* I2C3_SDA */ \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTD | DIS | M0)) /* i2c3_scl */ \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTD | DIS | M0)) /* i2c3_sda */ \ /* I2C4 */ \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */ \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */ \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* i2c4_scl */ \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* i2c4_sda */ \ /* HDQ */ \ - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /* GPIO_170: EAR_SENSE */ \ + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /* gpio_170 */ \ /* MCSPI1 */ \ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* GPIO_175: GAUGE_INT */ \ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* GPIO_176: MODEM_SEND */ \ - MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* GPIO_177: MODEM_CHK */ \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* MCSPI2_CLK */ \ - MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* MCSPI2_SIMO */ \ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* MCSPI2_SOMI */ \ - MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* GPIO_181: WLAN_WAKEUP */ \ - MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* GPIO_182: USIF1_SW */ \ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | DIS | M4)) /* gpio_175 */ \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* gpio_176 */ \ + MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTD | DIS | M4)) /* gpio_177 */ \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M0)) /* mcspi2_clk */ \ + MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | DIS | M0)) /* mcspi2_simo */ \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /* mcspi2_somi */ \ + MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTD | DIS | M4)) /* gpio_181 */ \ + MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | DIS | M4)) /* gpio_182 */ \ /* SYS */ \ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */ \ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /* SYS_CLKREQ */ \ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /* SYS_NIRQ */ \ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* SYS_OFF_MODE */ \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* GPIO_10: MICROSD_DET_N */ \ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* SAFE_MODE */ \ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* sys_32k */ \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /* sys_clkreq */ \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /* sys_nirq */ \ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTU | EN | M7)) /* safe_mode */ \ + MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /* sys_off_mode */ \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4)) /* gpio_10 */ \ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | EN | M7)) /* safe_mode */ \ /* JTAG */ \ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* JTAG_NTRST */ \ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* JTAG_TCK */ \ - MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* JTAG_TMS */ \ - MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* JTAG_TDI */ \ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* JTAG_EMU0 */ \ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* JTAG_EMU1 */ \ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /* jtag_ntrst */ \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /* jtag_tck */ \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M0)) /* jtag_tms */ \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M0)) /* jtag_tdi */ \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /* jtag_emu0 */ \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /* jtag_emu1 */ \ /* ETK */ \ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_CLK */ \ - MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* SDMMC3_CMD */ \ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* GPIO_14: PROX_OUT */ \ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* GPIO_15: CHG_STATUS_N_OMAP */ \ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* GPIO_16: BT_EN */ \ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT3 */ \ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT0 */ \ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT1 */ \ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* SDMMC3_DAT2 */ \ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* GPIO_21: IPC_SRDY */ \ - MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_22: IPC_MRDY */ \ - MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_23: WLAN_EN */ \ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | EN | M4)) /* GPIO_24: WLAN_HOST_WAKEUP */ \ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_25: CHG_EN_SET_N_OMAP */ \ - MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_26: IFX_RESET_1.8V */ \ - MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M4)) /* GPIO_27: IFX_PWRON_1.8V */ \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28: CRADLE_DETECT_N */ \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /* GPIO_29: CRADLE_DETECT_S */ \ + MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_clk */ \ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* sdmmc3_cmd */ \ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M4)) /* gpio_14 */ \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M4)) /* gpio_15 */ \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M4)) /* gpio_16 */ \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat3 */ \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat0 */ \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat1 */ \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat2 */ \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M4)) /* gpio_21 */ \ + MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M4)) /* gpio_22 */ \ + MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /* gpio_23 */ \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | EN | M4)) /* gpio_24 */ \ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) /* gpio_25 */ \ + MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M4)) /* gpio_26 */ \ + MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M4)) /* gpio_27 */ \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* gpio_28 */ \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /* gpio_29 */ \ /* D2D */ \ - MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)) /* D2D_MCAD0 */ \ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /* D2D_MCAD1 */ \ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /* D2D_MCAD2 */ \ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /* D2D_MCAD3 */ \ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /* D2D_MCAD4 */ \ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /* D2D_MCAD5 */ \ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /* D2D_MCAD6 */ \ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /* D2D_MCAD7 */ \ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /* D2D_MCAD8 */ \ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /* D2D_MCAD9 */ \ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /* D2D_MCAD10 */ \ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /* D2D_MCAD11 */ \ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /* D2D_MCAD12 */ \ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /* D2D_MCAD13 */ \ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /* D2D_MCAD14 */ \ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /* D2D_MCAD15 */ \ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /* D2D_MCAD16 */ \ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /* D2D_MCAD17 */ \ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /* D2D_MCAD18 */ \ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /* D2D_MCAD19 */ \ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /* D2D_MCAD20 */ \ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /* D2D_MCAD21 */ \ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /* D2D_MCAD22 */ \ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /* D2D_MCAD23 */ \ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /* D2D_MCAD24 */ \ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /* D2D_MCAD25 */ \ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /* D2D_MCAD26 */ \ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /* D2D_MCAD27 */ \ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /* D2D_MCAD28 */ \ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /* D2D_MCAD29 */ \ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /* D2D_MCAD30 */ \ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /* D2D_MCAD31 */ \ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /* D2D_MCAD32 */ \ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /* D2D_MCAD33 */ \ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /* D2D_MCAD34 */ \ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /* D2D_MCAD35 */ \ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* D2D_MCAD36 */ \ - MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* D2D_CLK26MI */ \ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* D2D_NRESPWRON */ \ - MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* D2D_NRESWARM */ \ - MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* D2D_ARM9NIRQ */ \ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* D2D_UMA2P6FIQ */ \ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* D2D_SPINT */ \ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | DIS | M0)) /* D2D_FRINT */ \ - MUX_VAL(CP(D2D_DMAREQ0), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ0 */ \ - MUX_VAL(CP(D2D_DMAREQ1), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ1 */ \ - MUX_VAL(CP(D2D_DMAREQ2), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ2 */ \ - MUX_VAL(CP(D2D_DMAREQ3), (IDIS | PTD | DIS | M0)) /* D2D_DMAREQ3 */ \ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /* D2D_N3GTRST */ \ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTU | EN | M0)) /* D2D_N3GTDI */ \ - MUX_VAL(CP(D2D_N3GTDO), (IDIS | PTD | DIS | M0)) /* D2D_N3GTDO */ \ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTU | EN | M0)) /* D2D_N3GTMS */ \ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /* D2D_N3GTCK */ \ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /* D2D_N3GRTCK */ \ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /* D2D_MSTDBY */ \ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /* D2D_SWAKEUP */ \ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /* D2D_IDLEREQ */ \ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /* D2D_IDLEACK */ \ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /* D2D_MWRITE */ \ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /* D2D_SWRITE */ \ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /* D2D_MREAD */ \ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* D2D_SREAD */ \ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_MBUSFLAG */ \ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* D2D_SBUSFLAG */ \ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* SDRC_CKE0 */ \ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* SDRC_CKE1 */ \ - MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* SAFE_MODE */ \ - MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* GPIO_126: OMAP_SEND */ \ - MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* GPIO_128: KEY_LED_RESET */ \ - MUX_VAL(CP(GPIO129), (IEN | PTD | DIS | M4)) /* GPIO_129: MODEM_AP_WAKE */ + MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)) /* d2d_mcad0 */ \ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /* d2d_mcad1 */ \ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /* d2d_mcad2 */ \ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /* d2d_mcad3 */ \ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /* d2d_mcad4 */ \ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /* d2d_mcad5 */ \ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /* d2d_mcad6 */ \ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /* d2d_mcad7 */ \ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /* d2d_mcad8 */ \ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /* d2d_mcad9 */ \ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /* d2d_mcad10 */ \ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /* d2d_mcad11 */ \ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /* d2d_mcad12 */ \ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /* d2d_mcad13 */ \ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /* d2d_mcad14 */ \ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /* d2d_mcad15 */ \ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /* d2d_mcad16 */ \ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /* d2d_mcad17 */ \ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /* d2d_mcad18 */ \ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /* d2d_mcad19 */ \ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /* d2d_mcad20 */ \ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /* d2d_mcad21 */ \ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /* d2d_mcad22 */ \ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /* d2d_mcad23 */ \ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /* d2d_mcad24 */ \ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /* d2d_mcad25 */ \ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /* d2d_mcad26 */ \ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /* d2d_mcad27 */ \ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /* d2d_mcad28 */ \ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /* d2d_mcad29 */ \ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /* d2d_mcad30 */ \ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /* d2d_mcad31 */ \ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /* d2d_mcad32 */ \ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /* d2d_mcad33 */ \ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /* d2d_mcad34 */ \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /* d2d_mcad35 */ \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /* d2d_mcad36 */ \ + MUX_VAL(CP(D2D_CLK26MI), (IDIS | PTD | DIS | M0)) /* d2d_clk26mi */ \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTU | EN | M0)) /* d2d_nrespwron */ \ + MUX_VAL(CP(D2D_NRESWARM), (IDIS | PTD | DIS | M0)) /* d2d_nreswarm */ \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IDIS | PTD | DIS | M0)) /* d2d_arm9nirq */ \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IDIS | PTD | DIS | M0)) /* d2d_uma2p6fiq */ \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | DIS | M0)) /* d2d_spint */ \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | DIS | M0)) /* d2d_frint */ \ + MUX_VAL(CP(D2D_DMAREQ0), (IDIS | PTD | DIS | M0)) /* d2d_dmareq0 */ \ + MUX_VAL(CP(D2D_DMAREQ1), (IDIS | PTD | DIS | M0)) /* d2d_dmareq1 */ \ + MUX_VAL(CP(D2D_DMAREQ2), (IDIS | PTD | DIS | M0)) /* d2d_dmareq2 */ \ + MUX_VAL(CP(D2D_DMAREQ3), (IDIS | PTD | DIS | M0)) /* d2d_dmareq3 */ \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /* d2d_n3gtrst */ \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTU | EN | M0)) /* d2d_n3gtdi */ \ + MUX_VAL(CP(D2D_N3GTDO), (IDIS | PTD | DIS | M0)) /* d2d_n3gtdo */ \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTU | EN | M0)) /* d2d_n3gtms */ \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /* d2d_n3gtck */ \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /* d2d_n3grtck */ \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /* d2d_mstdby */ \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /* d2d_swakeup */ \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /* d2d_idlereq */ \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /* d2d_idleack */ \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /* d2d_mwrite */ \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /* d2d_swrite */ \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /* d2d_mread */ \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /* d2d_sread */ \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_mbusflag */ \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /* d2d_sbusflag */ \ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTD | DIS | M0)) /* sdrc_cke0 */ \ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M0)) /* sdrc_cke1 */ \ + MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M7)) /* safe_mode */ \ + MUX_VAL(CP(GPIO126), (IDIS | PTD | DIS | M4)) /* gpio_126 */ \ + MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /* gpio_128 */ \ + MUX_VAL(CP(GPIO129), (IEN | PTD | DIS | M4)) /* gpio_129 */ #endif diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 0474deb..0335795 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -2,10 +2,13 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_SNIPER=y CONFIG_SPL=y -CONFIG_SYS_PROMPT="Sniper # " +CONFIG_SYS_PROMPT="sniper # " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_MUSB_GADGET=y diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 4152ecd..171a8c4 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -61,11 +61,8 @@ */ #define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SYS_SDRAM_BASE OMAP34XX_SDRC_CS0 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020F800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) @@ -103,8 +100,8 @@ * MMC */ -#define CONFIG_GENERIC_MMC #define CONFIG_MMC +#define CONFIG_GENERIC_MMC #define CONFIG_OMAP_HSMMC #define CONFIG_CMD_MMC @@ -183,7 +180,6 @@ * Serial */ - #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) @@ -192,7 +188,6 @@ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_CONS_INDEX 3 -#define CONFIG_SERIAL3 3 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ -- 2.6.4

2 2

[U-Boot] [PATCH] ARM: start.S: fix typo
by Yuichiro Goto 01 Mar '16

01 Mar '16

Fix typo in comment about position of 'A' bit in several start.S. Signed-off-by: Yuichiro Goto <goto.yuichiro(a)espark.co.jp> --- arch/arm/cpu/arm1136/start.S | 2 +- arch/arm/cpu/arm1176/start.S | 2 +- arch/arm/cpu/arm920t/start.S | 2 +- arch/arm/cpu/arm926ejs/start.S | 2 +- arch/arm/cpu/arm946es/start.S | 2 +- arch/arm/cpu/pxa/start.S | 2 +- arch/arm/cpu/sa1100/start.S | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 1ec79a6..3ebdfdd 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -78,7 +78,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 4c0ab4d..a602d4e 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -78,7 +78,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache /* Prepare to disable the MMU */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 0740450..69cabeb 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -131,7 +131,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 82cc1c9..f05113d 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -95,7 +95,7 @@ flush_dcache: #else bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ #endif - orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ #ifndef CONFIG_SYS_ICACHE_OFF orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ #endif diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index b55395a..214cd8c 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -86,7 +86,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ - orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 879390b..24b6ad1 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -100,7 +100,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index eebff66..408b70d 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -112,7 +112,7 @@ cpu_init_crit: bic r0, r0, #0x00002000 @ clear bit 13 (X) bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) orr r0, r0, #0x00001000 @ set bit 12 (I) Icache - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align mcr p15,0,r0,c1,c0 /* -- 1.7.10.4

2 1

[U-Boot] [PATCH] ARM: DRA7xx: Enable NFS boot command
by Andrew F. Davis 01 Mar '16

01 Mar '16

NFS loading works on DRA7 variants, remove the undefinition. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- configs/dra72_evm_defconfig | 1 - configs/dra7xx_evm_defconfig | 1 - configs/dra7xx_evm_qspiboot_defconfig | 1 - configs/dra7xx_evm_uart3_defconfig | 1 - 4 files changed, 4 deletions(-) diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig index b5bd798..a8a2b65 100644 --- a/configs/dra72_evm_defconfig +++ b/configs/dra72_evm_defconfig @@ -9,7 +9,6 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index f98e7b7..b69dc53 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -7,6 +7,5 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig index f14fa62..c823fe6 100644 --- a/configs/dra7xx_evm_qspiboot_defconfig +++ b/configs/dra7xx_evm_qspiboot_defconfig @@ -8,5 +8,4 @@ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig index 8882260..4c6aeb6 100644 --- a/configs/dra7xx_evm_uart3_defconfig +++ b/configs/dra7xx_evm_uart3_defconfig @@ -9,5 +9,4 @@ CONFIG_SYS_EXTRA_OPTIONS="SPL_YMODEM_SUPPORT" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set CONFIG_SPI_FLASH=y -- 2.7.2

3 2

[U-Boot] [PATCH 00/17] driver model bring-up of musb on AM335x GP and BBB and usb_ether DM conversion
by Mugunthan V N 01 Mar '16

01 Mar '16

This patch series enables musb driver to adopt driver model. This has been tested on the following evms (logs [1]) by loading kernel and dtb from sata hard-disk. * AM335x GP evm * AM335x BBB Also pushed a branch for testing [2] [1] - http://pastebin.ubuntu.com/15239811/ [2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-musb Mugunthan V N (17): configs: am335x: usb: do not define CONFIG_DM_USB for spl am33xx: board: do not register usb devices when CONFIG_DM_USB is defined drivers: usb: musb: add ti musb misc driver for wrapper am33xx: board: probe misc drivers to register musb devices drivers: usb: musb: adopt musb backend driver to driver model drivers: usb: musb: add ti musb host driver with driver model support drivers: usb: musb: add ti musb peripheral driver with driver model support drivers: usb: gadget: ether: adopt to usb driver model drivers: usb: gadget: ether: access network_started using local variable drivers: usb: gadget: ether: consolidate global devices to single struct drivers: usb: gadget: ether: use net device priv to pass usb ether priv drivers: usb: gadget: ether: prepare driver for driver model migration drivers: usb: gadget: ether/rndis: convert driver to adopt device driver model am33xx: board: init usb ether gadget for rndis support am335x_evm: enable usb ether gadget as it supports DM_ETH defconfig: am335x_boneblack: enable usb driver model defconfig: am335x_gp_evm: enable usb driver model arch/arm/cpu/armv7/am33xx/board.c | 20 +- arch/arm/include/asm/omap_musb.h | 7 + configs/am335x_boneblack_vboot_defconfig | 4 + configs/am335x_gp_evm_defconfig | 4 + drivers/usb/gadget/ether.c | 314 +++++++++++++++++++----- drivers/usb/gadget/rndis.c | 13 +- drivers/usb/gadget/rndis.h | 19 +- drivers/usb/musb-new/Kconfig | 9 + drivers/usb/musb-new/Makefile | 1 + drivers/usb/musb-new/am35x.c | 35 +++ drivers/usb/musb-new/musb_dsps.c | 20 ++ drivers/usb/musb-new/musb_uboot.c | 2 + drivers/usb/musb-new/ti-musb.c | 393 +++++++++++++++++++++++++++++++ include/configs/am335x_evm.h | 4 +- include/net.h | 7 + 15 files changed, 783 insertions(+), 69 deletions(-) create mode 100644 drivers/usb/musb-new/ti-musb.c -- 2.7.2.333.g70bd996

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[U-Boot] pull request: u-boot-uniphier/master (2nd round)
by Masahiro Yamada 01 Mar '16

01 Mar '16

Hi Tom, Here is a bunch of UniPhier updates which include GPIO driver support, MMC driver support, DRAM init code clean-ups, etc. Please pull. Changes for 2nd round: - Fix a build error when CONFIG_DEBUG_LL is defined The following changes since commit 50dc8677d769be6e2b34f49b6c43ad1e977bdc51: Merge git://git.denx.de/u-boot-usb (2016-02-26 18:08:43 -0500) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to 11d3ede42ceccef9b5941ea7907f398cb97ed361: ARM: uniphier: fix warnings reported by aarch64 compiler (2016-03-01 00:33:29 +0900) ---------------------------------------------------------------- Masahiro Yamada (38): ARM: dts: uniphier: rework System Bus nodes gpio: uniphier: add driver for UniPhier GPIO controller gpio: do not include <asm/arch/gpio.h> for UniPhier ARM: uniphier: enable GPIO command and driver for UniPhier SoCs ARM: dts: uniphier: add GPIO controller nodes mmc: uniphier: add driver for UniPhier SD/MMC host controller ARM: uniphier: enable UniPhier SD/MMC host driver ARM: dts: uniphier: add SD/MMC host controller nodes ARM: uniphier: add eMMC boot support ARM: uniphier: add a command to find the first MMC (non-SD) device ARM: uniphier: add emmcupdate command ARM: uniphier: default to environment in eMMC ARM: uniphier: remove unused umc_polling() ARM: uniphier: rework struct uniphier_board_data ARM: uniphier: optimize ProXstream2 UMC init code with "for" loop ARM: uniphier: use pr_err() where possible ARM: uniphier: refactor UMC init code for ProXstream2 ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings ARM: uniphier: disable debug circuit clocks for PH1-Pro4 ARM: uniphier: add a field to specify DDR3+ ARM: uniphier: merge DDR PHY init code for 3 SoCs ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init() ARM: uniphier: refactor DDR-PHY init code ARM: uniphier: refactor UMC init code for PH1-sLD8 ARM: uniphier: support more DRAM use cases for PH1-sLD8 ARM: uniphier: refactor UMC init code for PH1-LD4 ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loop ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loop ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loop ARM: uniphier: rework DRAM size handling in UMC init code ARM: uniphier: remove unused macros for UMC base addresses ARM: uniphier: deprecate umc_dram_init_{start, poll} ARM: uniphier: rename variable for DRAM controller base address ARM: uniphier: merge two defconfig files ARM: uniphier: rework UniPhier SoC select in Kconfig ARM: uniphier: rename PH1-LD10/PH1-sLD11 to PH1-LD20/PH1-LD11 ARM: uniphier: prepare directory structure for ARMv8 SoC support ARM: uniphier: fix warnings reported by aarch64 compiler arch/arm/Kconfig | 3 +- arch/arm/dts/uniphier-common32.dtsi | 19 +- arch/arm/dts/uniphier-ph1-ld4-ref.dts | 4 + arch/arm/dts/uniphier-ph1-ld4.dtsi | 137 +++++ arch/arm/dts/uniphier-ph1-ld6b-ref.dts | 4 + arch/arm/dts/uniphier-ph1-pro4-ace.dts | 4 + arch/arm/dts/uniphier-ph1-pro4-ref.dts | 8 + arch/arm/dts/uniphier-ph1-pro4-sanji.dts | 16 + arch/arm/dts/uniphier-ph1-pro4.dtsi | 240 ++++++++ arch/arm/dts/uniphier-ph1-pro5-4kbox.dts | 8 + arch/arm/dts/uniphier-ph1-pro5.dtsi | 227 ++++++++ arch/arm/dts/uniphier-ph1-sld3-ref.dts | 4 + arch/arm/dts/uniphier-ph1-sld3.dtsi | 151 +++++- arch/arm/dts/uniphier-ph1-sld8-ref.dts | 4 + arch/arm/dts/uniphier-ph1-sld8.dtsi | 137 +++++ arch/arm/dts/uniphier-pinctrl.dtsi | 15 + arch/arm/dts/uniphier-proxstream2-gentil.dts | 16 + arch/arm/dts/uniphier-proxstream2-vodka.dts | 16 + arch/arm/dts/uniphier-proxstream2.dtsi | 220 ++++++++ arch/arm/include/asm/gpio.h | 2 + arch/arm/mach-uniphier/Kconfig | 66 ++- arch/arm/mach-uniphier/Makefile | 9 +- arch/arm/mach-uniphier/arm32/Makefile | 13 + arch/arm/mach-uniphier/{ => arm32}/arm-mpcore.h | 0 arch/arm/mach-uniphier/{ => arm32}/cache_uniphier.c | 0 arch/arm/mach-uniphier/{ => arm32}/debug_ll.S | 6 +- arch/arm/mach-uniphier/{ => arm32}/late_lowlevel_init.S | 0 arch/arm/mach-uniphier/{ => arm32}/lowlevel_init.S | 0 arch/arm/mach-uniphier/{ => arm32}/ssc-regs.h | 0 arch/arm/mach-uniphier/{ => arm32}/timer.c | 0 arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c | 2 +- arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c | 2 +- arch/arm/mach-uniphier/boards.c | 178 +++--- arch/arm/mach-uniphier/boot-mode/boot-mode.c | 64 +++ arch/arm/mach-uniphier/cpu_info.c | 4 +- arch/arm/mach-uniphier/dram/Makefile | 4 +- arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c | 80 +-- arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c | 67 --- arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c | 78 --- arch/arm/mach-uniphier/dram/ddrphy-regs.h | 5 +- arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 225 ++++---- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 182 +++---- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 218 +++++--- arch/arm/mach-uniphier/dram/umc-proxstream2.c | 217 ++++---- arch/arm/mach-uniphier/dram/umc-regs.h | 48 +- arch/arm/mach-uniphier/dram_init.c | 5 +- arch/arm/mach-uniphier/init.h | 24 +- arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c | 6 +- arch/arm/mach-uniphier/memconf/memconf-proxstream2.c | 6 +- arch/arm/mach-uniphier/memconf/memconf.c | 14 +- arch/arm/mach-uniphier/micro-support-card.c | 3 +- arch/arm/mach-uniphier/sg-regs.h | 2 +- arch/arm/mach-uniphier/soc-info.h | 16 +- arch/arm/mach-uniphier/soc_info.c | 8 +- configs/uniphier_ld4_sld8_defconfig | 6 +- configs/uniphier_pro4_defconfig | 3 + configs/uniphier_pro5_defconfig | 30 - configs/uniphier_pxs2_ld6b_defconfig | 6 +- configs/uniphier_sld3_defconfig | 3 + doc/README.uniphier | 20 +- drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-uniphier.c | 147 +++++ drivers/mmc/Kconfig | 6 + drivers/mmc/Makefile | 1 + drivers/mmc/uniphier-sd.c | 751 ++++++++++++++++++++++++++ include/configs/uniphier.h | 26 +- 67 files changed, 2956 insertions(+), 837 deletions(-) create mode 100644 arch/arm/mach-uniphier/arm32/Makefile rename arch/arm/mach-uniphier/{ => arm32}/arm-mpcore.h (100%) rename arch/arm/mach-uniphier/{ => arm32}/cache_uniphier.c (100%) rename arch/arm/mach-uniphier/{ => arm32}/debug_ll.S (98%) rename arch/arm/mach-uniphier/{ => arm32}/late_lowlevel_init.S (100%) rename arch/arm/mach-uniphier/{ => arm32}/lowlevel_init.S (100%) rename arch/arm/mach-uniphier/{ => arm32}/ssc-regs.h (100%) rename arch/arm/mach-uniphier/{ => arm32}/timer.c (100%) delete mode 100644 arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c delete mode 100644 arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c delete mode 100644 configs/uniphier_pro5_defconfig create mode 100644 drivers/gpio/gpio-uniphier.c create mode 100644 drivers/mmc/uniphier-sd.c -- Best Regards Masahiro Yamada

2 1

[U-Boot] [PATCH V2] OMAP3: Various: Update serial platdata to update reg_offset to 0
by Adam Ford 29 Feb '16

29 Feb '16

V2: I hastily copy-pasted the boards without looking at the UART number. This addresses 3 boards that use UART3 and not UART1. With commit: d9a3bec682f9 "dm: ns16550: Add support for reg-offset property" reg_offset is added to the struct ns16550_platdata to be dt compatible with Linux kernel driver. A variety of OMAP3 boards are broken as the serial platdata is missing offsets. By explicitly naming the entry, this should also help 'future-proof' if more entries get added but are not needed for OMAP3. Tested on the Logic PD Torpedo + Wireless. I only changed a handful of devices that used the same syntax as the Logic board. Appologies if I missed one or stepped on toes. Thanks to Derald Woods and Alexander Graf. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- board/isee/igep00x0/igep00x0.c | 7 ++++--- board/logicpd/omap3som/omap3logic.c | 7 ++++--- board/logicpd/zoom1/zoom1.c | 7 ++++--- board/overo/overo.c | 7 ++++--- board/quipos/cairo/cairo.c | 7 ++++--- board/ti/beagle/beagle.c | 7 ++++--- board/timll/devkit8000/devkit8000.c | 7 ++++--- 7 files changed, 28 insertions(+), 21 deletions(-) diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index e2fce50..63489e5 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -34,9 +34,10 @@ static const u32 gpmc_lan_config[] = { #endif static const struct ns16550_platdata igep_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART1, + .reg_offset = 0, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(igep_uart) = { diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 668f684..0e72a5a 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -47,9 +47,10 @@ DECLARE_GLOBAL_DATA_PTR; */ static const struct ns16550_platdata omap3logic_serial = { - OMAP34XX_UART1, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART1, + .reg_offset = 0, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(omap3logic_uart) = { diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 4040114..3d34919 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -44,9 +44,10 @@ static const u32 gpmc_lab_enet[] = { }; static const struct ns16550_platdata zoom1_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART1, + .reg_offset = 0, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(zoom1_uart) = { diff --git a/board/overo/overo.c b/board/overo/overo.c index a38b959..3da80e9 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -68,9 +68,10 @@ static struct { } expansion_config = {0x0}; static const struct ns16550_platdata overo_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART3, + .reg_offset = 0, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(overo_uart) = { diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c index 21793e8..15d68c1 100644 --- a/board/quipos/cairo/cairo.c +++ b/board/quipos/cairo/cairo.c @@ -91,9 +91,10 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) #endif static const struct ns16550_platdata cairo_serial = { - OMAP34XX_UART2, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART1, + .reg_offset = 0, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(cairo_uart) = { diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index ff317ef..a5f2af7 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -73,9 +73,10 @@ static struct { } expansion_config; static const struct ns16550_platdata beagle_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART3, + .reg_offset = 0, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(beagle_uart) = { diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 1a447c7..fb8e357 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -46,9 +46,10 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = { }; static const struct ns16550_platdata devkit8000_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART3, + .reg_offset = 0, + .reg_shift = 2, + .clock = V_NS16550_CLK }; U_BOOT_DEVICE(devkit8000_uart) = { -- 1.9.1

5 7

[U-Boot] [PATCH 00/10] arm64: Unify MMU code
by Alexander Graf 29 Feb '16

29 Feb '16

Howdy, Currently on arm64 there is a big pile of mess when it comes to MMU support and page tables. Each board does its own little thing and the generic code is pretty dumb and nobody actually uses it. This patch set tries to clean that up. After this series is applied, all boards except for the FSL Layerscape ones are converted to the new generic page table logic and have icache+dcache enabled. The new code always uses 4k page size. It dynamically allocates 1G or 2M pages for ranges that fit. When a dcache attribute request comes in that requires a smaller granularity than our previous allocation could fulfill, pages get automatically split. I have tested and verified the code works on HiKey (bare metal), vexpress64 (Foundation Model) and zynqmp (QEMU). The TX1 target is untested, but given the simplicity of the maps I doubt it'll break. ThunderX in theory should also work, but I haven't tested it. I would be very happy if people with access to those system could give the patch set a try. With this we're a big step closer to a good base line for EFI payload support, since we can now just require that all boards always have dcache enabled. I would also be incredibly happy if some Freescale people could look at their MMU code and try to unify it into the now cleaned up generic code. I don't think we're far off here. Alex v1 -> v2: - Fix comment for create_table() - Rework page table size calculation - Move mmu tables into board files - New patch: thunderx: Move mmu table into board file Alexander Graf (10): thunderx: Calculate TCR dynamically arm64: Make full va map code more dynamic thunderx: Move mmu table into board file zymqmp: Replace home grown mmu code with generic table approach tegra: Replace home grown mmu code with generic table approach vexpress64: Add MMU tables dwmmc: Increase retry timeout hikey: Add MMU tables arm64: Remove non-full-va map code arm64: Only allow dcache disabled in SPL builds arch/arm/cpu/armv8/cache_v8.c | 495 +++++++++++++++++++------ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 37 +- arch/arm/cpu/armv8/zynqmp/cpu.c | 217 +++-------- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 94 ++--- arch/arm/include/asm/armv8/mmu.h | 122 ++---- arch/arm/include/asm/global_data.h | 6 +- arch/arm/include/asm/system.h | 7 +- arch/arm/mach-tegra/arm64-mmu.c | 132 +------ board/armltd/vexpress64/vexpress64.c | 21 ++ board/cavium/thunderx/thunderx.c | 24 ++ board/hisilicon/hikey/hikey.c | 21 ++ doc/README.arm64 | 20 - drivers/mmc/dw_mmc.c | 2 +- include/configs/hikey.h | 4 +- include/configs/thunderx_88xx.h | 30 -- include/configs/vexpress_aemv8a.h | 5 +- 16 files changed, 627 insertions(+), 610 deletions(-) -- 1.8.5.6

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