October 2016 - U-Boot

[U-Boot] [PATCH] Add workaround for USB PHY errata
by Suresh Gupta 07 Nov '16

07 Nov '16

The patch set implement USB PHY errata workaround which are required for LS series of freescale platforms which have Synopsis UTMI PHY Suresh Gupta (8): armv8: Add workaround for USB erratum A-009008 armv8: Add workaround for USB erratum A-009798 armv8: Add workaround for USB erratum A-008997 armv8: Add workaround for USB erratum A-009007 armv7: Add workaround for USB erratum A-009008 armv7: Add workaround for USB erratum A-009798 armv7: Add workaround for USB erratum A-008997 armv7: Add workaround for USB erratum A-009007 arch/arm/cpu/armv7/ls102xa/Kconfig | 16 +++ arch/arm/cpu/armv7/ls102xa/soc.c | 50 +++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 118 +++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 20 ++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 +++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 19 ++++ 7 files changed, 259 insertions(+) -- 1.9.3

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[U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization
by Pratiyush Srivastava 07 Nov '16

07 Nov '16

Clear the content to zero and the ECC error bit of OCRAM1/2. The OCRAM must be initialized to ZERO by the unit of 8-Byte before accessing it, or else it will generate ECC error. And the IBR has accessed the OCRAM before this initialization, so the ECC error status bit should to be cleared. Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava(a)nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- arch/arm/cpu/armv8/start.S | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 19c771d..24fed46 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -11,6 +11,9 @@ #include <asm/macro.h> #include <asm/armv8/mmu.h> +#define DCSR_SYS_DCFG_SBEESR2 0x20140534 +#define DCSR_SYS_DCFG_MBEESR2 0x20140544 + /************************************************************************* * * Startup Code (reset vector) @@ -259,10 +262,46 @@ WEAK(lowlevel_init) #endif /* CONFIG_ARMV8_MULTIENTRY */ 2: +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) + bl fsl_ocram_init +#endif mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +ENTRY(fsl_ocram_init) + mov x28, lr /* Save LR */ + bl fsl_clear_ocram + bl fsl_ocram_clear_ecc_err + mov lr, x28 /* Restore LR */ + ret +ENDPROC(fsl_ocram_init) + +ENTRY(fsl_clear_ocram) +/* Clear OCRAM */ + ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE + ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE) + mov x2, #0 +clear_loop: + str x2, [x0] + add x0, x0, #8 + cmp x0, x1 + b.lo clear_loop + ret +ENDPROC(fsl_clear_ocram) + +ENTRY(fsl_ocram_clear_ecc_err) + /* OCRAM1/2 ECC status bit */ + mov w1, #0x60 + ldr x0, =DCSR_SYS_DCFG_SBEESR2 + str w1, [x0] + ldr x0, =DCSR_SYS_DCFG_MBEESR2 + str w1, [x0] + ret +ENDPROC(fsl_ocram_init) +#endif + WEAK(smp_kick_all_cpus) /* Kick secondary cpus up by SGI 0 interrupt */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) -- 2.7.4

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[U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
by Minghuan Lian 07 Nov '16

07 Nov '16

for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus. Signed-off-by: Minghuan Lian <Minghuan.Lian(a)nxp.com> --- drivers/pci/pci_compat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c index ddaf358..25bc095 100644 --- a/drivers/pci/pci_compat.c +++ b/drivers/pci/pci_compat.c @@ -49,5 +49,5 @@ struct pci_controller *pci_bus_to_hose(int busnum) return NULL; } - return dev_get_uclass_priv(bus); + return dev_get_uclass_priv(pci_get_controller(bus)); } -- 1.9.1

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[U-Boot] [PATCH] net: mvgbe: Fix build error with CONFIG_PHYLIB
by Chris Packham 07 Nov '16

07 Nov '16

Commit 5a49f17481bb ("net: mii: Use spatch to update miiphy_register") updated the mvgbe implementation of smi_reg_read/smi_reg_write. Prior to that change mvgbe_phy_read and mvgbe_phy_write where used as wrappers to satisfy the phylib APIs. Because these functions weren't updated in that commit build errors where triggered when CONFIG_PHYLIB was enabled. Fix these build errors by removing mvgbe_phy_read and mvgbe_phy_write and using smi_reg_read/smi_reg_write directly. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- Looking at this closer it actually appears that the mvgbe driver has 2 places where a mii_dev is created. The first in mvgbe_phylib_init() which is triggered when CONFIG_PHYLIB is enabled (this is where I first noticed the build error), the second in mvgbe_initialize() which is triggered when CONFIG_MII or CONFIG_CMD_MII is enabled. I think this could do with some more cleaning up. But perhaps the build error should be fixed first and then we can tackle the cleanup. drivers/net/mvgbe.c | 25 +++---------------------- 1 file changed, 3 insertions(+), 22 deletions(-) diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index c784cdcae265..f833efbe6779 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -177,25 +177,6 @@ static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad, } #endif -#if defined(CONFIG_PHYLIB) -int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, - int reg_addr) -{ - u16 data; - int ret; - ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data); - if (ret) - return ret; - return data; -} - -int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, - int reg_addr, u16 data) -{ - return smi_reg_write(bus->name, phy_addr, reg_addr, data); -} -#endif - /* Stop and checks all queues */ static void stop_queue(u32 * qreg) { @@ -676,8 +657,8 @@ int mvgbe_phylib_init(struct eth_device *dev, int phyid) printf("mdio_alloc failed\n"); return -ENOMEM; } - bus->read = mvgbe_phy_read; - bus->write = mvgbe_phy_write; + bus->read = smi_reg_read; + bus->write = smi_reg_write; strcpy(bus->name, dev->name); ret = mdio_register(bus); @@ -688,7 +669,7 @@ int mvgbe_phylib_init(struct eth_device *dev, int phyid) } /* Set phy address of the port */ - mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid); + smi_reg_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid); phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII); if (!phydev) { -- 2.10.2

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[U-Boot] [PATCH] net: phy: micrel: center FLP burst timing at 16ms
by Ash Charles 07 Nov '16

07 Nov '16

Like [1], reset the FLP burst timing for the KSZ9031 to the 16ms specified by the IEEE802.3 standard from the chip's default of 8ms. For more details, see the "Auto-Negotiation Timing" section of the KSZ9031RNX datasheet. [1] https://patchwork.kernel.org/patch/6558371/ Change-Id: I122ee33300db3a617cc527070b4e97b88563d7a7 Signed-off-by: Ash Charles <ash.charles(a)savoirfairelinux.com> --- drivers/net/phy/micrel.c | 23 +++++++++++++++++++++++ include/micrel.h | 3 +++ 2 files changed, 26 insertions(+) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 6b313a9..28a1401 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -415,11 +415,31 @@ static int ksz9031_of_config(struct phy_device *phydev) return 0; } + +static int ksz9031_center_flp_timing(struct phy_device *phydev) +{ + struct phy_driver *drv = phydev->drv; + int ret = 0; + + if (!drv || !drv->writeext) + return -EOPNOTSUPP; + + ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80); + if (ret) + return ret; + + ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6); + return ret; +} #else static int ksz9031_of_config(struct phy_device *phydev) { return 0; } +static int ksz9031_center_flp_timing(struct phy_device *phydev) +{ + return 0; +} #endif /* Accessors to extended registers*/ @@ -472,6 +492,9 @@ static int ksz9031_config(struct phy_device *phydev) ret = ksz9031_of_config(phydev); if (ret) return ret; + ret = ksz9031_center_flp_timing(phydev); + if (ret) + return ret; return genphy_config(phydev); } diff --git a/include/micrel.h b/include/micrel.h index e6d145d..3e6b531 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -20,6 +20,9 @@ #define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6 #define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8 +#define MII_KSZ9031_FLP_BURST_TX_LO 0x3 +#define MII_KSZ9031_FLP_BURST_TX_HI 0x4 + /* Registers */ #define MMD_ACCESS_CONTROL 0xd #define MMD_ACCESS_REG_DATA 0xe -- 2.7.4

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[U-Boot] [PATCH 1/4] ARM: tegra: add SoC-level hook for board_late_init()
by Stephen Warren 07 Nov '16

07 Nov '16

From: Stephen Warren <swarren(a)nvidia.com> Extend the Tegra186 implementation of board_late_init() to call a per-SoC "hook" function. This will allow SoC-specific (rather than Tegra-wide) functionality to be implemented without the core Tegra code needing to be aware of the details. While board186.c is currently only used for Tegra186, it should be applicable to any other future SoC, and perhaps its simple design could be back-ported to older SoCs in the future too. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- This series logically relies on the DWC EQOS driver series that I just sent in order for the device to actually work. However, the code should compile and even run (albeit without yet enabling Ethernet) even without both series applied. So, the two series don't need to be applied in any particular order, nor in the same branch. arch/arm/mach-tegra/board186.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c index 1b9799fd80c2..38261e421cc1 100644 --- a/arch/arm/mach-tegra/board186.c +++ b/arch/arm/mach-tegra/board186.c @@ -26,11 +26,16 @@ int board_init(void) return tegra_board_init(); } -int board_late_init(void) +__weak int tegra_soc_board_init_late(void) { return 0; } +int board_late_init(void) +{ + return tegra_soc_board_init_late(); +} + void pad_init_mmc(struct mmc_host *host) { } -- 2.9.3

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[U-Boot] [PATCH V3 1/2] dt: net: add DWC EQoS binding
by Stephen Warren 07 Nov '16

07 Nov '16

From: Stephen Warren <swarren(a)nvidia.com> The Synopsys DWC EQoS is a configurable Ethernet MAC/DMA IP block which supports multiple options for bus type, clocking and reset structure, and feature list. This patch imports the binding from the Linux kernel, including my V3 patch to extend the binding to cover the Tegra186, which is applied for next-20160912. So far, my changes have been acked by Lars Persson, the original author of the binding. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- v2: No change. --- .../net/snps,dwc-qos-ethernet.txt | 166 +++++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt diff --git a/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt b/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt new file mode 100644 index 000000000000..d93f71ce8346 --- /dev/null +++ b/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt @@ -0,0 +1,166 @@ +* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC) + +This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service) +IP block. The IP supports multiple options for bus type, clocking and reset +structure, and feature list. Consequently, a number of properties and list +entries in properties are marked as optional, or only required in specific HW +configurations. + +Required properties: +- compatible: One of: + - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10" + Represents the IP core when integrated into the Axis ARTPEC-6 SoC. + - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10" + Represents the IP core when integrated into the NVIDIA Tegra186 SoC. + - "snps,dwc-qos-ethernet-4.10" + This combination is deprecated. It should be treated as equivalent to + "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be + compatible with earlier revisions of this binding. +- reg: Address and length of the register set for the device +- clocks: Phandle and clock specifiers for each entry in clock-names, in the + same order. See ../clock/clock-bindings.txt. +- clock-names: May contain any/all of the following depending on the IP + configuration, in any order: + - "tx" + The EQOS transmit path clock. The HW signal name is clk_tx_i. + In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX + path. In other configurations, other clocks (such as tx_125, rmii) may + drive the PHY TX path. + - "rx" + The EQOS receive path clock. The HW signal name is clk_rx_i. + In some configurations (e.g. GMII/RGMII), this clock is derived from the + PHY's RX clock output. In other configurations, other clocks (such as + rx_125, rmii) may drive the EQOS RX path. + In cases where the PHY clock is directly fed into the EQOS receive path + without intervening logic, the DT need not represent this clock, since it + is assumed to be fully under the control of the PHY device/driver. In + cases where SoC integration adds additional logic to this path, such as a + SW-controlled clock gate, this clock should be represented in DT. + - "slave_bus" + The CPU/slave-bus (CSR) interface clock. This applies to any bus type; + APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other + buses). + - "master_bus" + The master bus interface clock. Only required in configurations that use a + separate clock for the master and slave bus interfaces. The HW signal name + is hclk_i (AHB) or aclk_i (AXI). + - "ptp_ref" + The PTP reference clock. The HW signal name is clk_ptp_ref_i. + - "phy_ref_clk" + This clock is deprecated and should not be used by new compatible values. + It is equivalent to "tx". + - "apb_pclk" + This clock is deprecated and should not be used by new compatible values. + It is equivalent to "slave_bus". + + Note: Support for additional IP configurations may require adding the + following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i, + clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i. + Configurations exist where multiple similar clocks are used at once, e.g. all + of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to + extend the binding with a separate clock-names entry for each of those RX + clocks, rather than repurposing the existing "rx" clock-names entry as a + generic/logical clock in a similar fashion to "master_bus" and "slave_bus". + This will allow easy support for configurations that support multiple PHY + interfaces using a mux, and hence need to have explicit control over + specific RX clocks. + + The following compatible values require the following set of clocks: + - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": + - "slave_bus" + - "master_bus" + - "rx" + - "tx" + - "ptp_ref" + - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": + - "slave_bus" + - "master_bus" + - "tx" + - "ptp_ref" + - "snps,dwc-qos-ethernet-4.10" (deprecated): + - "phy_ref_clk" + - "apb_clk" +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device +- interrupts: Should contain the core's combined interrupt signal +- phy-mode: See ethernet.txt file in the same directory +- resets: Phandle and reset specifiers for each entry in reset-names, in the + same order. See ../reset/reset.txt. +- reset-names: May contain any/all of the following depending on the IP + configuration, in any order: + - "eqos". The reset to the entire module. The HW signal name is hreset_n + (AHB) or aresetn_i (AXI). + + The following compatible values require the following set of resets: + (the reset properties may be omitted if empty) + - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": + - "eqos". + - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": + - None. + - "snps,dwc-qos-ethernet-4.10" (deprecated): + - None. + +Optional properties: +- dma-coherent: Present if dma operations are coherent +- mac-address: See ethernet.txt in the same directory +- local-mac-address: See ethernet.txt in the same directory +- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY. + See ../gpio/gpio.txt. +- snps,en-lpi: If present it enables use of the AXI low-power interface +- snps,write-requests: Number of write requests that the AXI port can issue. + It depends on the SoC configuration. +- snps,read-requests: Number of read requests that the AXI port can issue. + It depends on the SoC configuration. +- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB + representing 4, then 8 etc. +- snps,txpbl: DMA Programmable burst length for the TX DMA +- snps,rxpbl: DMA Programmable burst length for the RX DMA +- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during + TX low-power mode. +- phy-handle: See ethernet.txt file in the same directory +- mdio device tree subnode: When the GMAC has a phy connected to its local + mdio, there must be device tree subnode with the following + required properties: + - compatible: Must be "snps,dwc-qos-ethernet-mdio". + - #address-cells: Must be <1>. + - #size-cells: Must be <0>. + + For each phy on the mdio bus, there must be a node with the following + fields: + + - reg: phy id used to communicate to phy. + - device_type: Must be "ethernet-phy". + - fixed-mode device tree subnode: see fixed-link.txt in the same directory + +Examples: +ethernet2@40010000 { + clock-names = "phy_ref_clk", "apb_pclk"; + clocks = <&clkc 17>, <&clkc 15>; + compatible = "snps,dwc-qos-ethernet-4.10"; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + reg = <0x40010000 0x4000>; + phy-handle = <&phy2>; + phy-mode = "gmii"; + phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>; + + snps,en-tx-lpi-clockgating; + snps,en-lpi; + snps,write-requests = <2>; + snps,read-requests = <16>; + snps,burst-map = <0x7>; + snps,txpbl = <8>; + snps,rxpbl = <2>; + + dma-coherent; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + phy2: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x1>; + }; + }; +}; -- 2.10.1

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Re: [U-Boot] [Resend RFC PATCH 1/2] armv8: Fix dcache disable function
by york sun 07 Nov '16

07 Nov '16

On 10/26/2016 02:02 PM, york.sun(a)nxp.com wrote: > > I came back from my testing and I have more questions than answers. > > For _this_ patch, I proposed to flush cache before disabling them, > noting once the dcache is disabled, the staled data in dirty cache is > not visible to the core. My argument was if we flush L1/L2, they could > end up in L3 (I don't know for sure). If I want to skip flushing L3, I > have to fix it. > > During this discussion, I thought I made a mistake by flushing L1/L2 by > way/set first, then flushing by VA. Actually I didn't. I flushed by VA > first. > > With my today's test, the baseline (working in the sense of booting > Linux) is > > PATCH 1/2 armv8: Fix dcache disable function > PATCH 2/2 armv8: Fix flush_dcache_all function > > With these two patches, I flush the stack up to top of U-Boot by VA, > followed by flush by set/way. L3 is not flushed. Then d-cache is > disabled. I know this is not a real "flush all" procedure. With this > modified procedure, I can continue to boot Linux. > > If I revert patch 1, i.e. to disable dcache before flushing, I can see > the data is not visible from the core (debug with JTAG tool). My hope > was the staled data should be flushed to main memory if flushed by VA. > That's not the case. The main memory doesn't have the correct data. So > my new question is, why flushing by VA doesn't flush the data to main > memory? Do I need to flush the cache while cache is enabled? > Guys, I think I found the root cause of my data loss. Current code disables D-cache and MMU before flushing the cache. I think the problem is turning off MMU. MMU should stay on when we flush D-cache. We can turn it off after the flushing. Once I make this change, I can see the correct data in memory after flushing (by VA). Do you agree we should leave MMU on during flushing? York

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[U-Boot] [PATCH 1/6] x86: Add implementations of setjmp() and longjmp()
by Simon Glass 07 Nov '16

07 Nov '16

Bring in these functions from Linux v4.4. They will be needed for EFI loader support. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/setjmp.S | 71 +++++++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/setjmp.h | 24 +++++++++++++++ 3 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/setjmp.S create mode 100644 arch/x86/include/asm/setjmp.h diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 2667e0b..f5b8c9e 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -10,7 +10,7 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o -obj-y += interrupts.o cpu.o cpu_x86.o call64.o +obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) diff --git a/arch/x86/cpu/setjmp.S b/arch/x86/cpu/setjmp.S new file mode 100644 index 0000000..24e7d8a --- /dev/null +++ b/arch/x86/cpu/setjmp.S @@ -0,0 +1,71 @@ +/* + * Written by H. Peter Anvin <hpa(a)zytor.com> + * Brought in from Linux v4.4 and modified for U-Boot + * From Linux arch/um/sys-i386/setjmp.S + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm/global_data.h> +#include <asm/msr-index.h> +#include <asm/processor-flags.h> + +#define _REGPARM + +/* + * The jmp_buf is assumed to contain the following, in order: + * %ebx + * %esp + * %ebp + * %esi + * %edi + * <return address> + */ + + /* + * rdi - 32-bit code segment selector + * rsi - target address + * rdx - table address (0 if none) + */ + .text + .align 4 + .globl setjmp + .type setjmp, @function +setjmp: +#ifdef _REGPARM + movl %eax,%edx +#else + movl 4(%esp),%edx +#endif + popl %ecx # Return address, and adjust the stack + xorl %eax,%eax # Return value + movl %ebx,(%edx) + movl %esp,4(%edx) # Post-return %esp! + pushl %ecx # Make the call/return stack happy + movl %ebp,8(%edx) + movl %esi,12(%edx) + movl %edi,16(%edx) + movl %ecx,20(%edx) # Return address + ret + + .size setjmp,.-setjmp + + .text + .align 4 + .globl longjmp + .type longjmp, @function +longjmp: +#ifdef _REGPARM + xchgl %eax,%edx +#else + movl 4(%esp),%edx # jmp_ptr address + movl 8(%esp),%eax # Return value +#endif + movl (%edx),%ebx + movl 4(%edx),%esp + movl 8(%edx),%ebp + movl 12(%edx),%esi + movl 16(%edx),%edi + jmp *20(%edx) + + .size longjmp,.-longjmp diff --git a/arch/x86/include/asm/setjmp.h b/arch/x86/include/asm/setjmp.h new file mode 100644 index 0000000..deef67e --- /dev/null +++ b/arch/x86/include/asm/setjmp.h @@ -0,0 +1,24 @@ +/* + * Written by H. Peter Anvin <hpa(a)zytor.com> + * Brought in from Linux v4.4 and modified for U-Boot + * From Linux arch/um/sys-i386/setjmp.S + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __setjmp_h +#define __setjmp_h + +struct jmp_buf_data { + unsigned int __ebx; + unsigned int __esp; + unsigned int __ebp; + unsigned int __esi; + unsigned int __edi; + unsigned int __eip; +}; + +int setjmp(struct jmp_buf_data *jmp_buf); +void longjmp(struct jmp_buf_data *jmp_buf); + +#endif -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2 1/8] x86: Add implementations of setjmp() and longjmp()
by Simon Glass 07 Nov '16

07 Nov '16

Bring in these functions from Linux v4.4. They will be needed for EFI loader support. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Drop irrelevant comment - Add a comment about .size - Drop unnecessary .text directive - Make longjmp() always cause setjmp() to return 1 arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/setjmp.S | 66 +++++++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/setjmp.h | 24 ++++++++++++++++ 3 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/setjmp.S create mode 100644 arch/x86/include/asm/setjmp.h diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 2667e0b..f5b8c9e 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -10,7 +10,7 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o -obj-y += interrupts.o cpu.o cpu_x86.o call64.o +obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) diff --git a/arch/x86/cpu/setjmp.S b/arch/x86/cpu/setjmp.S new file mode 100644 index 0000000..7443274 --- /dev/null +++ b/arch/x86/cpu/setjmp.S @@ -0,0 +1,66 @@ +/* + * Written by H. Peter Anvin <hpa(a)zytor.com> + * Brought in from Linux v4.4 and modified for U-Boot + * From Linux arch/um/sys-i386/setjmp.S + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm/global_data.h> +#include <asm/msr-index.h> +#include <asm/processor-flags.h> + +#define _REGPARM + +/* + * The jmp_buf is assumed to contain the following, in order: + * %ebx + * %esp + * %ebp + * %esi + * %edi + * <return address> + */ + + .text + .align 4 + .globl setjmp + .type setjmp, @function +setjmp: +#ifdef _REGPARM + movl %eax, %edx +#else + movl 4(%esp), %edx +#endif + popl %ecx /* Return address, and adjust the stack */ + xorl %eax, %eax /* Return value */ + movl %ebx, (%edx) + movl %esp, 4(%edx) /* Post-return %esp! */ + pushl %ecx /* Make the call/return stack happy */ + movl %ebp, 8(%edx) + movl %esi, 12(%edx) + movl %edi, 16(%edx) + movl %ecx, 20(%edx) /* Return address */ + ret + + /* Provide function size if needed */ + .size setjmp, .-setjmp + + .align 4 + .globl longjmp + .type longjmp, @function +longjmp: +#ifdef _REGPARM + xchgl %eax, %edx +#else + movl 4(%esp), %edx /* jmp_ptr address */ +#endif + movl 1, %eax + movl (%edx), %ebx + movl 4(%edx), %esp + movl 8(%edx), %ebp + movl 12(%edx), %esi + movl 16(%edx), %edi + jmp *20(%edx) + + .size longjmp, .-longjmp diff --git a/arch/x86/include/asm/setjmp.h b/arch/x86/include/asm/setjmp.h new file mode 100644 index 0000000..deef67e --- /dev/null +++ b/arch/x86/include/asm/setjmp.h @@ -0,0 +1,24 @@ +/* + * Written by H. Peter Anvin <hpa(a)zytor.com> + * Brought in from Linux v4.4 and modified for U-Boot + * From Linux arch/um/sys-i386/setjmp.S + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __setjmp_h +#define __setjmp_h + +struct jmp_buf_data { + unsigned int __ebx; + unsigned int __esp; + unsigned int __ebp; + unsigned int __esi; + unsigned int __edi; + unsigned int __eip; +}; + +int setjmp(struct jmp_buf_data *jmp_buf); +void longjmp(struct jmp_buf_data *jmp_buf); + +#endif -- 2.8.0.rc3.226.g39d4020

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