August 2015 - U-Boot

[U-Boot] [PATCH 0/3] CAAM RNG fixes
by Alex Porosanu 04 Aug '15

04 Aug '15

This set of patches fixes some issues identified with the usage of the RNG block of the CAAM in newer SoCs e.g. T2080. Alex Porosanu (3): crypto/fsl - disable RNG oscillator maximum frequency check crypto/fsl - change starting entropy delay value crypto/fsl - enable raw data instead of von Neumann data drivers/crypto/fsl/jr.c | 15 ++++++++++++--- include/fsl_sec.h | 13 ++++++++++++- 2 files changed, 24 insertions(+), 4 deletions(-) -- 1.9.1

2 6

[U-Boot] [PATCH] ls1021a: etsec: Enable Tx Data and TxBD snooping
by Alison Wang 04 Aug '15

04 Aug '15

To improve eTSEC performance on LS1021A Rev2.0, snooping of all transmit frames from memory and all transmit BD memory accesses in enabled. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- include/tsec.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/tsec.h b/include/tsec.h index 58cdc19..1119d2c 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -129,11 +129,7 @@ #define MINFLR_INIT_SETTINGS 0x00000040 -#ifdef CONFIG_LS102XA -#define DMACTRL_INIT_SETTINGS 0x00000003 -#else #define DMACTRL_INIT_SETTINGS 0x000000c3 -#endif #define DMACTRL_GRS 0x00000010 #define DMACTRL_GTS 0x00000008 #define DMACTRL_LE 0x00008000 -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] arm: ls1021a: allow OCRAM access permission as R/W in SPL
by Alison Wang 04 Aug '15

04 Aug '15

On LS1021A Rev2.0, OCRAM's security level needs to be changed to non-secure access for SD boot. This patch will allow OCRAM access permission as R/W in SPL. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- board/freescale/ls1021aqds/ls1021aqds.c | 178 +++++++++++++++++--------------- board/freescale/ls1021atwr/ls1021atwr.c | 177 ++++++++++++++++--------------- 2 files changed, 184 insertions(+), 171 deletions(-) diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 92f613a..2d96770 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -54,6 +54,92 @@ enum { GE1_CLK125, }; +#ifdef CONFIG_LS102XA_NS_ACCESS +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; +#endif + int checkboard(void) { #ifndef CONFIG_QSPI_BOOT @@ -289,6 +375,12 @@ void board_init_f(ulong dummy) dram_init(); + /* Allow OCRAM access permission as R/W */ +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(&ns_dev[4], 1); + enable_devices_ns_access(&ns_dev[7], 1); +#endif + board_init_r(NULL, 0); } #endif @@ -441,92 +533,6 @@ int misc_init_r(void) return 0; } -#ifdef CONFIG_LS102XA_NS_ACCESS -static struct csu_ns_dev ns_dev[] = { - { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, - { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, - { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, - { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, - { CSU_CSLX_OCRAM, CSU_ALL_RW }, - { CSU_CSLX_GIC, CSU_ALL_RW }, - { CSU_CSLX_PCIE1, CSU_ALL_RW }, - { CSU_CSLX_OCRAM2, CSU_ALL_RW }, - { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, - { CSU_CSLX_PCIE2, CSU_ALL_RW }, - { CSU_CSLX_SATA, CSU_ALL_RW }, - { CSU_CSLX_USB3, CSU_ALL_RW }, - { CSU_CSLX_SERDES, CSU_ALL_RW }, - { CSU_CSLX_QDMA, CSU_ALL_RW }, - { CSU_CSLX_LPUART2, CSU_ALL_RW }, - { CSU_CSLX_LPUART1, CSU_ALL_RW }, - { CSU_CSLX_LPUART4, CSU_ALL_RW }, - { CSU_CSLX_LPUART3, CSU_ALL_RW }, - { CSU_CSLX_LPUART6, CSU_ALL_RW }, - { CSU_CSLX_LPUART5, CSU_ALL_RW }, - { CSU_CSLX_DSPI2, CSU_ALL_RW }, - { CSU_CSLX_DSPI1, CSU_ALL_RW }, - { CSU_CSLX_QSPI, CSU_ALL_RW }, - { CSU_CSLX_ESDHC, CSU_ALL_RW }, - { CSU_CSLX_2D_ACE, CSU_ALL_RW }, - { CSU_CSLX_IFC, CSU_ALL_RW }, - { CSU_CSLX_I2C1, CSU_ALL_RW }, - { CSU_CSLX_USB2, CSU_ALL_RW }, - { CSU_CSLX_I2C3, CSU_ALL_RW }, - { CSU_CSLX_I2C2, CSU_ALL_RW }, - { CSU_CSLX_DUART2, CSU_ALL_RW }, - { CSU_CSLX_DUART1, CSU_ALL_RW }, - { CSU_CSLX_WDT2, CSU_ALL_RW }, - { CSU_CSLX_WDT1, CSU_ALL_RW }, - { CSU_CSLX_EDMA, CSU_ALL_RW }, - { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, - { CSU_CSLX_DDR, CSU_ALL_RW }, - { CSU_CSLX_QUICC, CSU_ALL_RW }, - { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, - { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, - { CSU_CSLX_SFP, CSU_ALL_RW }, - { CSU_CSLX_TMU, CSU_ALL_RW }, - { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, - { CSU_CSLX_RESERVED0, CSU_ALL_RW }, - { CSU_CSLX_ETSEC1, CSU_ALL_RW }, - { CSU_CSLX_SEC5_5, CSU_ALL_RW }, - { CSU_CSLX_ETSEC3, CSU_ALL_RW }, - { CSU_CSLX_ETSEC2, CSU_ALL_RW }, - { CSU_CSLX_GPIO2, CSU_ALL_RW }, - { CSU_CSLX_GPIO1, CSU_ALL_RW }, - { CSU_CSLX_GPIO4, CSU_ALL_RW }, - { CSU_CSLX_GPIO3, CSU_ALL_RW }, - { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, - { CSU_CSLX_CSU, CSU_ALL_RW }, - { CSU_CSLX_ASRC, CSU_ALL_RW }, - { CSU_CSLX_SPDIF, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, - { CSU_CSLX_SAI2, CSU_ALL_RW }, - { CSU_CSLX_SAI1, CSU_ALL_RW }, - { CSU_CSLX_SAI4, CSU_ALL_RW }, - { CSU_CSLX_SAI3, CSU_ALL_RW }, - { CSU_CSLX_FTM2, CSU_ALL_RW }, - { CSU_CSLX_FTM1, CSU_ALL_RW }, - { CSU_CSLX_FTM4, CSU_ALL_RW }, - { CSU_CSLX_FTM3, CSU_ALL_RW }, - { CSU_CSLX_FTM6, CSU_ALL_RW }, - { CSU_CSLX_FTM5, CSU_ALL_RW }, - { CSU_CSLX_FTM8, CSU_ALL_RW }, - { CSU_CSLX_FTM7, CSU_ALL_RW }, - { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, - { CSU_CSLX_EPU, CSU_ALL_RW }, - { CSU_CSLX_GDI, CSU_ALL_RW }, - { CSU_CSLX_DDI, CSU_ALL_RW }, - { CSU_CSLX_RESERVED1, CSU_ALL_RW }, - { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, - { CSU_CSLX_RESERVED2, CSU_ALL_RW }, -}; -#endif - struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 043d938..4e8ecae 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -66,6 +66,92 @@ DECLARE_GLOBAL_DATA_PTR; #define PIN_QE_LCD_MUX_LCD 0x0 #define PIN_QE_LCD_MUX_QE 0x1 +#ifdef CONFIG_LS102XA_NS_ACCESS +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; +#endif + struct cpld_data { u8 cpld_ver; /* cpld revision */ u8 cpld_ver_sub; /* cpld sub revision */ @@ -400,95 +486,16 @@ void board_init_f(ulong dummy) dram_init(); + /* Allow OCRAM access permission as R/W */ +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(&ns_dev[4], 1); + enable_devices_ns_access(&ns_dev[7], 1); +#endif + board_init_r(NULL, 0); } #endif -#ifdef CONFIG_LS102XA_NS_ACCESS -static struct csu_ns_dev ns_dev[] = { - { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, - { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, - { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, - { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, - { CSU_CSLX_OCRAM, CSU_ALL_RW }, - { CSU_CSLX_GIC, CSU_ALL_RW }, - { CSU_CSLX_PCIE1, CSU_ALL_RW }, - { CSU_CSLX_OCRAM2, CSU_ALL_RW }, - { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, - { CSU_CSLX_PCIE2, CSU_ALL_RW }, - { CSU_CSLX_SATA, CSU_ALL_RW }, - { CSU_CSLX_USB3, CSU_ALL_RW }, - { CSU_CSLX_SERDES, CSU_ALL_RW }, - { CSU_CSLX_QDMA, CSU_ALL_RW }, - { CSU_CSLX_LPUART2, CSU_ALL_RW }, - { CSU_CSLX_LPUART1, CSU_ALL_RW }, - { CSU_CSLX_LPUART4, CSU_ALL_RW }, - { CSU_CSLX_LPUART3, CSU_ALL_RW }, - { CSU_CSLX_LPUART6, CSU_ALL_RW }, - { CSU_CSLX_LPUART5, CSU_ALL_RW }, - { CSU_CSLX_DSPI2, CSU_ALL_RW }, - { CSU_CSLX_DSPI1, CSU_ALL_RW }, - { CSU_CSLX_QSPI, CSU_ALL_RW }, - { CSU_CSLX_ESDHC, CSU_ALL_RW }, - { CSU_CSLX_2D_ACE, CSU_ALL_RW }, - { CSU_CSLX_IFC, CSU_ALL_RW }, - { CSU_CSLX_I2C1, CSU_ALL_RW }, - { CSU_CSLX_USB2, CSU_ALL_RW }, - { CSU_CSLX_I2C3, CSU_ALL_RW }, - { CSU_CSLX_I2C2, CSU_ALL_RW }, - { CSU_CSLX_DUART2, CSU_ALL_RW }, - { CSU_CSLX_DUART1, CSU_ALL_RW }, - { CSU_CSLX_WDT2, CSU_ALL_RW }, - { CSU_CSLX_WDT1, CSU_ALL_RW }, - { CSU_CSLX_EDMA, CSU_ALL_RW }, - { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, - { CSU_CSLX_DDR, CSU_ALL_RW }, - { CSU_CSLX_QUICC, CSU_ALL_RW }, - { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, - { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, - { CSU_CSLX_SFP, CSU_ALL_RW }, - { CSU_CSLX_TMU, CSU_ALL_RW }, - { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, - { CSU_CSLX_RESERVED0, CSU_ALL_RW }, - { CSU_CSLX_ETSEC1, CSU_ALL_RW }, - { CSU_CSLX_SEC5_5, CSU_ALL_RW }, - { CSU_CSLX_ETSEC3, CSU_ALL_RW }, - { CSU_CSLX_ETSEC2, CSU_ALL_RW }, - { CSU_CSLX_GPIO2, CSU_ALL_RW }, - { CSU_CSLX_GPIO1, CSU_ALL_RW }, - { CSU_CSLX_GPIO4, CSU_ALL_RW }, - { CSU_CSLX_GPIO3, CSU_ALL_RW }, - { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, - { CSU_CSLX_CSU, CSU_ALL_RW }, - { CSU_CSLX_ASRC, CSU_ALL_RW }, - { CSU_CSLX_SPDIF, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, - { CSU_CSLX_SAI2, CSU_ALL_RW }, - { CSU_CSLX_SAI1, CSU_ALL_RW }, - { CSU_CSLX_SAI4, CSU_ALL_RW }, - { CSU_CSLX_SAI3, CSU_ALL_RW }, - { CSU_CSLX_FTM2, CSU_ALL_RW }, - { CSU_CSLX_FTM1, CSU_ALL_RW }, - { CSU_CSLX_FTM4, CSU_ALL_RW }, - { CSU_CSLX_FTM3, CSU_ALL_RW }, - { CSU_CSLX_FTM6, CSU_ALL_RW }, - { CSU_CSLX_FTM5, CSU_ALL_RW }, - { CSU_CSLX_FTM8, CSU_ALL_RW }, - { CSU_CSLX_FTM7, CSU_ALL_RW }, - { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, - { CSU_CSLX_EPU, CSU_ALL_RW }, - { CSU_CSLX_GDI, CSU_ALL_RW }, - { CSU_CSLX_DDI, CSU_ALL_RW }, - { CSU_CSLX_RESERVED1, CSU_ALL_RW }, - { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, - { CSU_CSLX_RESERVED2, CSU_ALL_RW }, -}; -#endif struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] arm/layerscape: Fix non-boot cpus cannot correctly fall in spin table
by Dongsheng Wang 04 Aug '15

04 Aug '15

From: Wang Dongsheng <dongsheng.wang(a)freescale.com> Bootrom will put cpus into WFE state when boot cpu release cpus, so target cpu cannot correctly go to spin state. Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target cpu can fall into u-boot spin table. Signed-off-by: Wang Dongsheng <dongsheng.wang(a)freescale.com> diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 75f0d8c..1f82893 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -344,5 +344,13 @@ void smp_kick_all_cpus(void) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); out_be32(&gur->brrl, 0x2); + + /* + * LS1 STANDBYWFE is not captured outside the ARM module in the soc. + * So add a delay to wait bootrom execute WFE. + */ + udelay(1); + + asm volatile("sev"); } #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] arm: ls1021atwr: program the regulator for deep sleep
by Chenhui Zhao 04 Aug '15

04 Aug '15

Program the external regulator to switch off voltage in deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao(a)freescale.com> --- board/freescale/ls1021atwr/ls1021atwr.c | 34 +++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 2c8d6d1..37ec0ba 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -578,6 +578,37 @@ struct smmu_stream_id dev_stream_id[] = { { 0x18c, 0x0e, "DEBUG" }, }; +#ifdef CONFIG_DEEP_SLEEP +/* program the regulator (MC34VR500) to support deep sleep */ +void ls1twr_program_regulator(void) +{ + unsigned int i2c_bus; + u8 i2c_device_id; + +#define LS1TWR_I2C_BUS_MC34VR500 1 +#define MC34VR500_ADDR 0x8 +#define MC34VR500_DEVICEID 0x4 +#define MC34VR500_DEVICEID_MASK 0x0f + + i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); + i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & + MC34VR500_DEVICEID_MASK; + if (i2c_device_id != MC34VR500_DEVICEID) { + printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); + return; + } + + i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4); + i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4); + i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38); + i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37); + i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); + + i2c_set_bus_num(i2c_bus); +} +#endif + int board_init(void) { #ifndef CONFIG_SYS_FSL_NO_SERDES @@ -600,6 +631,9 @@ int board_init(void) u_qe_init(); #endif +#ifdef CONFIG_DEEP_SLEEP + ls1twr_program_regulator(); +#endif return 0; } -- 1.9.1

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[U-Boot] [PATCH] ls1021atwr: added deep sleep support in uboot
by Yuantian.Tang＠freescale.com 04 Aug '15

04 Aug '15

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++ board/freescale/ls1021atwr/ls1021atwr.c | 68 ++++++++++++++++++++++- include/configs/ls1021atwr.h | 7 ++- 3 files changed, 75 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index a8122c1..bbd5955 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -370,6 +370,10 @@ struct ccsr_serdes { #define DDR_DDR_ZQ_CNTL 0x89080600 #define DDR_CS0_CONFIG_2 0 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG_BI 0x00000001 /* DDR memory controller registers */ struct ccsr_ddr { diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index ed5bd27..2c8d6d1 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -21,6 +21,7 @@ #include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" #endif @@ -147,6 +148,7 @@ unsigned int get_soc_major_rev(void) void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + u32 temp_sdram_cfg; out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); @@ -160,7 +162,22 @@ void ddrmc_init(void) out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); - out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + out_be32(&ddr->sdram_cfg_2, + DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); + out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_ext_addr, (1 << 31)); + + /* DRAM VRef will not be trained */ + out_be32(&ddr->ddr_cdr2, + DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + } out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); @@ -173,14 +190,35 @@ void ddrmc_init(void) out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); - out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); udelay(1); - out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); + + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif } int dram_init(void) @@ -190,6 +228,11 @@ int dram_init(void) #endif gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return 0; } @@ -384,6 +427,11 @@ int board_early_init_f(void) out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); } +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + return 0; } @@ -395,6 +443,11 @@ void board_init_f(ulong dummy) get_clocks(); +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + preloader_console_init(); dram_init(); @@ -563,6 +616,15 @@ int misc_init_r(void) } #endif +#if defined(CONFIG_DEEP_SLEEP) +void board_sleep_prepare(void) +{ +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#endif +} +#endif + int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 729205f..4b96feb 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -18,6 +18,10 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DEEP_SLEEP +#ifdef CONFIG_DEEP_SLEEP +#define CONFIG_SILENT_CONSOLE +#endif /* * Size of malloc() pool @@ -60,7 +64,8 @@ #define CONFIG_SPL_PAD_TO 0x1c000 #define CONFIG_SYS_TEXT_BASE 0x82000000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] LS1021atwr: Enable bootscript for secure boot
by Gaurav Rana 04 Aug '15

04 Aug '15

Enable bootscript support in secure boot for establishing chain of trust on LS1021atwr. Signed-off-by: Gaurav Rana <gaurav.rana(a)freescale.com> --- include/configs/ls1021atwr.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 729205f..f637b59 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -444,6 +444,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB +#include <asm/fsl_secure_boot.h> #endif #endif -- 1.8.1.4

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[U-Boot] [PATCH 1/2] qe: transform parameter to compatible type
by Zhao Qiang 04 Aug '15

04 Aug '15

when using printf, the parameter type need to be compatible type, so transform them to compatible type Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- drivers/qe/qe.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 84e1433..f1df0a4 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -313,9 +313,10 @@ static void qe_upload_microcode(const void *base, if (ucode->major || ucode->minor || ucode->revision) printf("QE: uploading microcode '%s' version %u.%u.%u\n", - ucode->id, ucode->major, ucode->minor, ucode->revision); + (char *)ucode->id, (u16)ucode->major, (u16)ucode->minor, + (u16)ucode->revision); else - printf("QE: uploading microcode '%s'\n", ucode->id); + printf("QE: uploading microcode '%s'\n", (char *)ucode->id); /* Use auto-increment */ out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) | -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] arm:ls1021a: Reserve secure code into RAM instead of OCRAM
by Zhuoyu Zhang 04 Aug '15

04 Aug '15

For ls1021a, Reserve secure code in to memory in case OCRAM is needed by other usage. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang(a)freescale.com> --- include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 3dc4da3..42439a4 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -554,7 +554,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_LS102XA_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 -#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a13876b..dccc661 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -347,7 +347,6 @@ #define CONFIG_LS102XA_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 -#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] fdt: Fix fdtdec_get_addr_size() for 64-bit
by Stephen Warren 04 Aug '15

04 Aug '15

From: Thierry Reding <treding(a)nvidia.com> Signed-off-by: Thierry Reding <treding(a)nvidia.com> Signed-off-by: Tom Warren <twarren(a)nvidia.com> Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- Simon, When Thierry first posted this patch, you responded: > > + parent = fdt_parent_offset(blob, node); > > This function is very slow as it must scan the whole tree. Can we > instead pass in the parent node? I don't think that's possible in general. This function is called from fdtdec_get_addr(), and it's easy to find call sites of that function that don't have the parent node available. IIRC, the first couple of example I found scan the DT for a node with a certain compatible value, or look up nodes via aliases, rather than being called while parsing the DT in a top-down tree-like fashion, where the parent node is easily available. I didn't do an exhaustive search after I found a few problematic cases. > Also, how about (in addition) a > version of this function that works for devices? Like: > > device_get_addr_size(struct udevice *dev, ...) > > so that it can handle this for you. That sounds like a separate patch? Equally, I see that struct udevice contains an of_offset field, but no parent_of_offset or similar. There is a struct udevice *parent though; is the struct udevice hierarchy guaranteed to 100% match the DT hierarchy? I know this isn't necessarily guaranteed in Linux's device model for example. As such, this patch seems OK to me as-is. --- lib/fdtdec.c | 56 ++++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 36 insertions(+), 20 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9c6b3619da24..56e72eafaade 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -88,29 +88,45 @@ const char *fdtdec_get_compatible(enum fdt_compat_id id) fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, const char *prop_name, fdt_size_t *sizep) { - const fdt_addr_t *cell; - int len; + const fdt32_t *ptr, *end; + int parent, na, ns, len; + fdt_addr_t addr; debug("%s: %s: ", __func__, prop_name); - cell = fdt_getprop(blob, node, prop_name, &len); - if (cell && ((!sizep && len == sizeof(fdt_addr_t)) || - len == sizeof(fdt_addr_t) * 2)) { - fdt_addr_t addr = fdt_addr_to_cpu(*cell); - if (sizep) { - const fdt_size_t *size; - - size = (fdt_size_t *)((char *)cell + - sizeof(fdt_addr_t)); - *sizep = fdt_size_to_cpu(*size); - debug("addr=%08lx, size=%llx\n", - (ulong)addr, (u64)*sizep); - } else { - debug("%08lx\n", (ulong)addr); - } - return addr; + + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("(no parent found)\n"); + return FDT_ADDR_T_NONE; } - debug("(not found)\n"); - return FDT_ADDR_T_NONE; + + na = fdt_address_cells(blob, parent); + ns = fdt_size_cells(blob, parent); + + ptr = fdt_getprop(blob, node, prop_name, &len); + if (!ptr) { + debug("(not found)\n"); + return FDT_ADDR_T_NONE; + } + + end = ptr + len / sizeof(*ptr); + + if (ptr + na + ns > end) { + debug("(not enough data: expected %d bytes, got %d bytes)\n", + (na + ns) * 4, len); + return FDT_ADDR_T_NONE; + } + + addr = fdtdec_get_number(ptr, na); + + if (sizep) { + *sizep = fdtdec_get_number(ptr + na, ns); + debug("addr=%pa, size=%pa\n", &addr, sizep); + } else { + debug("%pa\n", &addr); + } + + return addr; } fdt_addr_t fdtdec_get_addr(const void *blob, int node, -- 1.9.1

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