August 2015 - U-Boot

[U-Boot] [linux-sunxi][PATCH v2] sunxi: Add support for the Olimex A20 EVB
by codekipper＠gmail.com 27 Aug '15

27 Aug '15

From: Marcus Cooper <codekipper(a)gmail.com> Signed-off-by: Marcus Cooper <codekipper(a)gmail.com> --- Changes since v1: - modified dtb to reflect changes in the kernel --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun7i-a20-olimex-som-evb.dts | 244 ++++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/A20-Olimex-SOM-EVB_defconfig | 17 +++ 4 files changed, 267 insertions(+) create mode 100644 arch/arm/dts/sun7i-a20-olimex-som-evb.dts create mode 100644 configs/A20-Olimex-SOM-EVB_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d9a2f5f..731d3c1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -120,6 +120,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-m3.dtb \ sun7i-a20-m5.dtb \ sun7i-a20-mk808c.dtb \ + sun7i-a20-olimex-som-evb.dtb \ sun7i-a20-olinuxino-lime.dtb \ sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-micro.dtb \ diff --git a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts new file mode 100644 index 0000000..6904dbd --- /dev/null +++ b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts @@ -0,0 +1,244 @@ +/* + * Copyright 2015 - Marcus Cooper <codekipper(a)gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Olimex A20-Olimex-SOM-EVB"; + compatible = "olimex,a20-olimex-som-evb", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olimex_som_evb>; + + green { + label = "a20-olimex-som-evb:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_axp_ipsout: axp_ipsout { + compatible = "regulator-fixed"; + regulator-name = "axp-ipsout"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&ahci { + target-supply = <&reg_ahci_5v>; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin@1 { + allwinner,pins = "PC3"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + led_pins_olimex_som_evb: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_20_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH04"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH05"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&reg_ahci_5v { + pinctrl-0 = <&ahci_pwr_pin_olimex_som_evb>; + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +#include "axp209.dtsi" + +&reg_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1425000>; + regulator-name = "vdd-cpu"; +}; + +&reg_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +&reg_ldo1 { + regulator-name = "vdd-rtc"; +}; + +&reg_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +&reg_usb0_vbus { + status = "okay"; +}; + +&reg_usb1_vbus { + status = "okay"; +}; + +&reg_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpios = <&pio 7 04 GPIO_ACTIVE_HIGH>; /* PH04 */ + usb0_vbus_det-gpios = <&pio 7 05 GPIO_ACTIVE_HIGH>; /* PH05 */ + usb0_vbus-supply = <&reg_usb0_vbus>; + usb1_vbus-supply = <&reg_usb1_vbus>; + usb2_vbus-supply = <&reg_usb2_vbus>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1b44ce8..0c2f9b4 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -45,6 +45,11 @@ F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig F: include/configs/sun9i.h F: configs/Merrii_A80_Optimus_defconfig +A20-OLIMEX-SOM-EVB BOARD +M: Marcus Cooper <codekipper(a)gmail.com> +S: Maintained +F: configs/A20-Olimex-SOM-EVB_defconfig + A20-OLINUXINO-LIME BOARD M: FUKAUMI Naoki <naobsd(a)gmail.com> S: Maintained diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig new file mode 100644 index 0000000..d155a38 --- /dev/null +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=480 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_USB0_VBUS_PIN="PB9" +CONFIG_USB0_VBUS_DET="PH5" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_ETH_DESIGNWARE=y +CONFIG_USB_EHCI_HCD=y + -- 2.5.0

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[U-Boot] [PATCH v5 0/5] spi: cadence_qspi: optimize & fix indirect rd-writes
by Vikas Manocha 27 Aug '15

27 Aug '15

This patchset: - fixes trigger base & transfer start address register programming. This fix superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger address setting". - adds support to get fifo width from device tree Changes in v5: - fixed compilation warnings. Changes in v4: - fifo-width & trigger address alligned to linux device tree binding. - removed un-necessary casting. - renaming of one parameter splitted to separate patch. - trigger address of socfpga reverted back to 0x0. - code formatting done to avoid checkpatch CHECKS. Changes in v3: - removed two patches which were bypassing the sram level check. - format string in patch corrected 3/4 - added commit message in patch 1/4 Changes in v2: - rebased to master. - removed patch "spi: cadence_qspi: read can be independent of fifo width", it was implemented in other patchset, in mainline now. Vikas Manocha (5): spi: cadence_qspi: move trigger base configuration in init spi: cadence_qspi: fix indirect read/write start address spi: cadence_qspi: fix base trigger address & transfer start address spi: cadence_qspi: rename ahbbase to flashbase for clarity spi: cadence_qspi: get fifo width from device tree arch/arm/dts/socfpga.dtsi | 2 ++ arch/arm/dts/stv0991.dts | 2 ++ drivers/spi/cadence_qspi.c | 14 ++++++++------ drivers/spi/cadence_qspi.h | 6 ++++-- drivers/spi/cadence_qspi_apb.c | 42 ++++++++++++++++------------------------ 5 files changed, 33 insertions(+), 33 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH 1/6] armv8: Make COUNTER_FREQUENCY optional
by Thierry Reding 27 Aug '15

27 Aug '15

From: Thierry Reding <treding(a)nvidia.com> Some platforms have the means to determine the counter frequency at runtime, so give them an opportunity to do so. Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- arch/arm/cpu/armv8/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e70bed462a59..da45d984d01a 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -54,8 +54,10 @@ reset: orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ msr scr_el3, x0 msr cptr_el3, xzr /* Enable FP/SIMD */ +#ifdef COUNTER_FREQUENCY ldr x0, =COUNTER_FREQUENCY msr cntfrq_el0, x0 /* Initialize CNTFRQ */ +#endif b 0f 2: msr vbar_el2, x0 mov x0, #0x33ff -- 2.4.5

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Re: [U-Boot] [PATCH 1/3] drivers: Introduce a simplified remoteproc framework
by Simon Glass 27 Aug '15

27 Aug '15

+U-Boot On 26 August 2015 at 16:51, Nishanth Menon <nm(a)ti.com> wrote: > On Tue, Aug 25, 2015 at 9:26 PM, Simon Glass <sjg(a)chromium.org> wrote: >> >>>>> +#include <dm/platdata.h> /* For platform data support - non dt world */ >>>> >>>> Does this need to be supported for a new uclass? >>> >>> we do have platforms that are not using DT yet... they will need to pass >>> platform data. >> >> Is this a good opportunity to convert them? > > It might be better not to hold the platforms hostage yet -> at least > the TI ones(which depend on this series) are already in the pipe for > conversion - the journey will take some time to complete though. That seems OK, but please add a comment that new platforms should not use the platform data. Regards, Simon

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Re: [U-Boot] ROM build failure on Galileo
by Bin Meng 27 Aug '15

27 Aug '15

Hi Andy, On Thu, Aug 27, 2015 at 11:46 PM, Andy Pont <andy.pont(a)sdcsystems.com> wrote: > Hi Bin, > >> Please check http://patchwork.ozlabs.org/patch/511333/ which should >> fix this issue. > > The compilation of the .rom file for Galileo now succeeds with the application of this patch. Thanks for testing. > Not sure this is the official and proper way to do it but: Yes, but you need reply the patch thread [1] with the following 'Tested-by' :-) > > Tested-by: Andy Pont <andy.pont(a)sdcsystems.com> > [1] http://lists.denx.de/pipermail/u-boot/2015-August/225557.html Regards, Bin

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Re: [U-Boot] ROM build failure on Galileo
by Bin Meng 27 Aug '15

27 Aug '15

Hi Andy, On Thu, Aug 27, 2015 at 4:26 PM, Andy Pont <andy.pont(a)sdcsystems.com> wrote: > Hello, > > Following the latest merges to the Master branch the ROM build now appears > to fail on Galileo (built with gcc v4.8.4). > > The build output terminates with: > > OBJCOPY u-boot.srec > OBJCOPY u-boot.bin > OBJCOPY u-boot-x86-16bit.bin > CAT u-boot-dtb.bin > IFDTOOL u-boot.rom > U-Boot image overlaps with region './board/intel/galileo/rmu.bin' > U-Boot finishes at offset 7025a, file starts at 0 oops! > make: *** [u-boot.rom] Error 1 > > Any ideas why? > I've reproduced this. I will work on a patch soon. Regards, Bin

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[U-Boot] [PATCH 00/15] sunxi_nand_spl: cleanups, auto config and bad block handling
by Hans de Goede 27 Aug '15

27 Aug '15

Hi All, As promised I've been working on cleaning up the sunxi nand spl driver, as well as adding bad block handling in the same way as the BROM does, as the SPL + u-boot must be placed in a BROM compatible nand partition. This series is a bit of a patch bomb, but as you will see they are all nice and small (which is why there are quite a few). Regards, Hans

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[U-Boot] Pull request: nand flash master
by Scott Wood 27 Aug '15

27 Aug '15

The following changes since commit c851a2458fbc12495f4f786d4eabb612850a5143: Merge git://git.denx.de/u-boot-socfpga (2015-08-23 20:44:25 -0400) are available in the git repository at: git://git.denx.de/u-boot-nand-flash.git for you to fetch changes up to ecfb8768b16ebf6781ee0df45742674bda8a9543: mtd: nand: mxs invalidate dcache before DMA read (2015-08-25 22:53:59 -0500) ---------------------------------------------------------------- Ezequiel Garcia (1): mtd: Introduce mtd_block_isreserved() Peng Fan (2): mtd: nand: mxs support oobsize bigger than 512 mtd: nand: mxs invalidate dcache before DMA read Scott Wood (2): nand: Remove __UBOOT__ ifdefs nand: Sync with Linux v4.1 Siva Durga Prasad Paladugu (1): mtd: nand: Increase max sizes of OOB and Page size Stefan Roese (2): mtd: nand: Add mvebu (PXA / AXP / A38x) NAND device driver arm: mvebu: Enable NAND on db-mv784mp-gp arch/arm/include/asm/imx-common/regs-bch.h | 2 + configs/db-mv784mp-gp_defconfig | 1 + drivers/mtd/mtdcore.c | 14 +- drivers/mtd/mtdpart.c | 9 + drivers/mtd/nand/Kconfig | 7 + drivers/mtd/nand/Makefile | 2 + drivers/mtd/nand/atmel_nand_ecc.h | 3 + drivers/mtd/nand/denali.c | 209 ++-- drivers/mtd/nand/denali.h | 8 +- drivers/mtd/nand/docg4.c | 6 +- drivers/mtd/nand/fsl_elbc_nand.c | 14 + drivers/mtd/nand/fsl_ifc_nand.c | 33 +- drivers/mtd/nand/mxs_nand.c | 38 +- drivers/mtd/nand/nand_base.c | 615 +++-------- drivers/mtd/nand/nand_bbt.c | 75 +- drivers/mtd/nand/nand_ids.c | 10 +- drivers/mtd/nand/nand_timings.c | 252 +++++ drivers/mtd/nand/pxa3xx_nand.c | 1621 ++++++++++++++++++++++++++++ drivers/mtd/nand/pxa3xx_nand.h | 64 ++ include/configs/db-mv784mp-gp.h | 5 + include/fsl_ifc.h | 2 + include/linux/mtd/mtd.h | 4 +- include/linux/mtd/nand.h | 126 ++- 23 files changed, 2448 insertions(+), 672 deletions(-) create mode 100644 drivers/mtd/nand/nand_timings.c create mode 100644 drivers/mtd/nand/pxa3xx_nand.c create mode 100644 drivers/mtd/nand/pxa3xx_nand.h

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[U-Boot] [PATCH] usb: ehci: remember init mode
by Stephen Warren 27 Aug '15

27 Aug '15

From: Stephen Warren <swarren(a)nvidia.com> When an EHCI device is registered in device mode, the HW isn't actually initialized at all, and hence isn't left in a running state. Consequently, when the device is deregistered, ehci_shutdown() will fail, since the HW bits it expects to see set in response to its shutdown requests will not be sent, and the message "EHCI failed to shut down host controller." will be printed. Fix ehci-hcd.c to remember whether the device was registered in host or device mode, and only call ehci_shutdown() for host mode registrations. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- drivers/usb/host/ehci-hcd.c | 7 ++++++- drivers/usb/host/ehci.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 3a0d32ee2ba1..88b670b7f8a7 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1645,8 +1645,10 @@ int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, ctrl->hcor = hcor; ctrl->priv = ctrl; - if (init == USB_INIT_DEVICE) + ctrl->init = init; + if (ctrl->init == USB_INIT_DEVICE) goto done; + ret = ehci_reset(ctrl); if (ret) goto err; @@ -1666,6 +1668,9 @@ int ehci_deregister(struct udevice *dev) { struct ehci_ctrl *ctrl = dev_get_priv(dev); + if (ctrl->init == USB_INIT_DEVICE) + return 0; + ehci_shutdown(ctrl); return 0; diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 3379c293c4df..b41c04a8b30a 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -242,6 +242,7 @@ struct ehci_ops { }; struct ehci_ctrl { + enum usb_init_type init; struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ struct ehci_hcor *hcor; int rootdev; -- 1.9.1

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[U-Boot] Exynos 5800/5422 CPU ID inconsistency.
by Przemyslaw Marczak 27 Aug '15

27 Aug '15

Hello, The s5p_cpu_id variable is set in here: arch/arm/mach-exynos/include/mach/cpu.h For value 0x422, found in pro id register, the s5p_cpu_id is set as 0x5800. I think, that hiding the real info is wrong and misleading. I don't have documentation for E5800, but maybe there is some additional register like package id to recognise the SoC variant. I'm pointing this issue, because for older boards, we used this information to set the $fdtfile environment variable name, to next load proper fdt from partition before boot the kernel. Now, I would like use the s5p_cpu_id to set the fdtfile name for Odroid XU3/4, but the value is bad. I would like fix this value to the real one, but then, the CPU name will change on Chromebooks. To fix this we could add "cpu-name" property to device tree, and then print it. What do you think about this? Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marczak(a)samsung.com

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