August 2015 - U-Boot

[U-Boot] [PATCH v3] taurus: board updates
by Heiko Schocher 11 Sep '15

11 Sep '15

taurus changes: - rename at91_spl_board_init to spl_board_init fixes problems with recovery button and nand erase sector 0 - adapt CONFIG_SPL_MAX_SIZE and CONFIG_SPL_BSS_MAX_SIZE - add CONFIG_AT91_HW_WDT_TIMEOUT 15 - CONFIG_SF_DEFAULT_MODE SPI_MODE_3 not mode 0 Signed-off-by: Heiko Schocher <hs(a)denx.de> --- Changes in v3: - use SZ_X defines for sizes Changes in v2: - add comments from Andreas Biessmann: - rebase to 0d339cf9a969f0c249713d3697e735184f1bd955 board/siemens/taurus/taurus.c | 6 +++--- include/configs/taurus.h | 21 +++++++++++---------- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 781727e..edeb15b 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -99,7 +99,7 @@ static int at91_is_recovery(void) } #endif -void at91_spl_board_init(void) +void spl_board_init(void) { taurus_nand_hw_init(); at91_spi0_hw_init(TAURUS_SPI_MASK); @@ -124,13 +124,13 @@ void at91_spl_board_init(void) if (at91_is_recovery() == 1) { struct spi_flash *flash; - debug("Recovery button pressed\n"); + puts("Recovery button pressed\n"); nand_init(); spl_nand_erase_one(0, 0); flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, 0, CONFIG_SF_DEFAULT_SPEED, - SPI_MODE_3); + CONFIG_SF_DEFAULT_MODE); if (!flash) { puts("no flash\n"); } else { diff --git a/include/configs/taurus.h b/include/configs/taurus.h index fb7c575..c1fed9a 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -81,14 +81,14 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) /* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, * leaving the correct space for initial global data structure above * that address while providing maximum stack area below. */ -# define CONFIG_SYS_INIT_SP_ADDR \ +#define CONFIG_SYS_INIT_SP_ADDR \ (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) /* NAND flash */ @@ -112,6 +112,7 @@ #define CONFIG_AT91_WANTS_COMMON_PHY #define CONFIG_AT91SAM9_WATCHDOG +#define CONFIG_AT91_HW_WDT_TIMEOUT 15 #if !defined(CONFIG_SPL_BUILD) /* Enable the watchdog */ #define CONFIG_HW_WATCHDOG @@ -146,8 +147,8 @@ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 #endif /* load address */ @@ -157,7 +158,7 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x100000 #define CONFIG_ENV_OFFSET_REDUND 0x180000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_ENV_SIZE (SZ_128K) /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" #if defined(CONFIG_BOARD_TAURUS) @@ -241,7 +242,7 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, 0x1000) /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK @@ -253,7 +254,7 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024) +#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512) #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT @@ -275,9 +276,9 @@ #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_SIZE (256*1024*1024) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M) +#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K +#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -- 2.1.0

2 1

[U-Boot] [PATCH v3] arm, at91: add axm extensions
by Heiko Schocher 11 Sep '15

11 Sep '15

add extensions for the axm board: - power on LED on power up - press both recovery buttons on power up to enter recovery mode - detect 64 MiB and 128 MiB ramsize - PHY rest at reboot because of ATMEL bug - use siemens update concept - add axm default environment - set CONFIG_SPL_MAX_SIZE to 15k Signed-off-by: Heiko Schocher <hs(a)denx.de> --- Changes in v3: - add comments from Andreas Biessmann: - remove compile error Changes in v2: - add comments from Andreas Biessmann: - set stack into second sram segment - fix some Coding Style issues - reworked "suspect code indent" warning - reworked update concept - rebase against 0d339cf9a969f0c249713d3697e735184f1bd955 board/siemens/taurus/taurus.c | 196 ++++++++++++++++++++++++++++++++++++++---- include/configs/taurus.h | 71 ++++++++++++++- 2 files changed, 249 insertions(+), 18 deletions(-) diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 013dac2..781727e 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -12,6 +12,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <command.h> #include <common.h> #include <asm/io.h> #include <asm/arch/at91sam9260_matrix.h> @@ -79,16 +80,48 @@ void matrix_init(void) &mat->scfg[3]); } +#if defined(CONFIG_BOARD_AXM) +static int at91_is_recovery(void) +{ + if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) && + (at91_get_gpio_value(AT91_PIN_PA27) == 0)) + return 1; + + return 0; +} +#elif defined(CONFIG_BOARD_TAURUS) +static int at91_is_recovery(void) +{ + if (at91_get_gpio_value(AT91_PIN_PA31) == 0) + return 1; + + return 0; +} +#endif + void at91_spl_board_init(void) { taurus_nand_hw_init(); at91_spi0_hw_init(TAURUS_SPI_MASK); +#if defined(CONFIG_BOARD_AXM) + /* Configure LED PINs */ + at91_set_gpio_output(AT91_PIN_PA6, 0); + at91_set_gpio_output(AT91_PIN_PA8, 0); + at91_set_gpio_output(AT91_PIN_PA9, 0); + at91_set_gpio_output(AT91_PIN_PA10, 0); + at91_set_gpio_output(AT91_PIN_PA11, 0); + at91_set_gpio_output(AT91_PIN_PA12, 0); + /* Configure recovery button PINs */ + at91_set_gpio_input(AT91_PIN_PA26, 1); + at91_set_gpio_input(AT91_PIN_PA27, 1); +#elif defined(CONFIG_BOARD_TAURUS) at91_set_gpio_input(AT91_PIN_PA31, 1); +#endif - /* check if button is pressed */ - if (at91_get_gpio_value(AT91_PIN_PA31) == 0) { + /* check for recovery mode */ + if (at91_is_recovery() == 1) { struct spi_flash *flash; debug("Recovery button pressed\n"); @@ -108,35 +141,72 @@ void at91_spl_board_init(void) } } -void mem_init(void) +#define SDRAM_BASE_CONF (AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \ + |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ + | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \ + | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \ + | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10)) + +void sdramc_configure(unsigned int mask) { struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; struct sdramc_reg setting; at91_sdram_hw_init(); - setting.cr = (AT91_SDRAMC_NC_9 | - AT91_SDRAMC_NR_13 | - AT91_SDRAMC_CAS_3 | - AT91_SDRAMC_NB_4 | - AT91_SDRAMC_DBW_32 | - AT91_SDRAMC_TWR_VAL(3) | - AT91_SDRAMC_TRC_VAL(9) | - AT91_SDRAMC_TRP_VAL(3) | - AT91_SDRAMC_TRCD_VAL(3) | - AT91_SDRAMC_TRAS_VAL(6) | - AT91_SDRAMC_TXSR_VAL(10)); + setting.cr = SDRAM_BASE_CONF | mask; setting.mdr = AT91_SDRAMC_MD_SDRAM; setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; - writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, &ma->ebicsa); + sdramc_initialize(ATMEL_BASE_CS1, &setting); } + +void mem_init(void) +{ + unsigned int ram_size = 0; + + /* Configure SDRAM for 128MB */ + sdramc_configure(AT91_SDRAMC_NC_10); + + /* Do memtest for 128MB */ + ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + /* + * If 32MB or 16MB should be supported check also for + * expected mirroring at A16 and A17 + * To find mirror addresses depends how the collumns are connected + * at RAM (internaly or externaly) + * If the collumns are not in inverted order the mirror size effect + * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal + */ + + /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/ + if (ram_size == 0x800) { + printf("\n\r 64MB"); + sdramc_configure(AT91_SDRAMC_NC_9); + } else { + /* Size already initialized */ + printf("\n\r 128MB"); + } +} #endif #ifdef CONFIG_MACB +static void siemens_phy_reset(void) +{ + /* + * we need to reset PHY for 200us + * because of bug in ATMEL G20 CPU (undefined initial state of GPIO) + */ + if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) == + AT91_RSTC_RSTTYP_GENERAL) + at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */ +} + static void taurus_macb_hw_init(void) { /* Enable EMAC clock */ @@ -160,6 +230,8 @@ static void taurus_macb_hw_init(void) at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0); at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0); + siemens_phy_reset(); + at91_phy_reset(); at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */ @@ -244,3 +316,97 @@ int board_eth_init(bd_t *bis) #endif return rc; } + +#if !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_BOARD_AXM) +/* + * Booting the Fallback Image. + * + * The function is used to provide and + * boot the image with the fallback + * parameters, incase if the faulty image + * in upgraded over the base firmware. + * + */ +static int upgrade_failure_fallback(void) +{ + char *partitionset_active = NULL; + char *rootfs = NULL; + char *rootfs_fallback = NULL; + char *kern_off; + char *kern_off_fb; + char *kern_size; + char *kern_size_fb; + + partitionset_active = getenv("partitionset_active"); + if (partitionset_active) { + if (partitionset_active[0] == 'A') + setenv("partitionset_active", "B"); + else + setenv("partitionset_active", "A"); + } else { + printf("partitionset_active missing.\n"); + return -ENOENT; + } + + rootfs = getenv("rootfs"); + rootfs_fallback = getenv("rootfs_fallback"); + setenv("rootfs", rootfs_fallback); + setenv("rootfs_fallback", rootfs); + + kern_size = getenv("kernel_size"); + kern_size_fb = getenv("kernel_size_fallback"); + setenv("kernel_size", kern_size_fb); + setenv("kernel_size_fallback", kern_size); + + kern_off = getenv("kernel_Off"); + kern_off_fb = getenv("kernel_Off_fallback"); + setenv("kernel_Off", kern_off_fb); + setenv("kernel_Off_fallback", kern_off); + + setenv("bootargs", '\0'); + setenv("upgrade_available", '\0'); + setenv("boot_retries", '\0'); + saveenv(); + + return 0; +} + +static int do_upgrade_available(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned long upgrade_available = 0; + unsigned long boot_retry = 0; + char boot_buf[10]; + + upgrade_available = simple_strtoul(getenv("upgrade_available"), NULL, + 10); + if (upgrade_available) { + boot_retry = simple_strtoul(getenv("boot_retries"), NULL, 10); + boot_retry++; + sprintf(boot_buf, "%lx", boot_retry); + setenv("boot_retries", boot_buf); + saveenv(); + + /* + * Here the boot_retries count is checked, and if the + * count becomes greater than 2 switch back to the + * fallback, and reset the board. + */ + + if (boot_retry > 2) { + if (upgrade_failure_fallback() == 0) + do_reset(NULL, 0, 0, NULL); + return -1; + } + } + return 0; +} + +U_BOOT_CMD( + upgrade_available, 1, 1, do_upgrade_available, + "check Siemens update", + "no parameters" +); +#endif +#endif diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 2c9f5da..fb7c575 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -20,6 +20,7 @@ * In this case SoC is defined in boards.cfg. */ #include <asm/hardware.h> +#include <linux/sizes.h> #define CONFIG_SYS_GENERIC_BOARD @@ -158,12 +159,75 @@ #define CONFIG_ENV_OFFSET_REDUND 0x180000 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" -#define CONFIG_BOOTARGS \ + +#if defined(CONFIG_BOARD_TAURUS) +#define CONFIG_BOOTARGS_TAURUS \ "console=ttyS0,115200 earlyprintk " \ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ "256k(env),256k(env_redundant),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "root=/dev/mtdblock7 rw rootfstype=jffs2" +#endif + +#if defined(CONFIG_BOARD_AXM) +#define CONFIG_BOOTARGS_AXM \ + "\0" \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \ + "addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \ + "baudrate=115200\0" \ + "boot_file=setenv bootfile /${project_dir}/kernel/uImage\0" \ + "boot_retries=0\0" \ + "bootcmd=run flash_self\0" \ + "bootdelay=3\0" \ + "ethact=macb0\0" \ + "flash_nfs=run nand_kernel;run nfsargs;run addip;upgrade_available;"\ + "bootm ${kernel_ram};reset\0" \ + "flash_self=run nand_kernel;run setbootargs;upgrade_available;" \ + "bootm ${kernel_ram};reset\0" \ + "flash_self_test=run nand_kernel;run setbootargs addtest; " \ + "upgrade_available;bootm ${kernel_ram};reset\0" \ + "hostname=systemone\0" \ + "kernel_Off=0x00200000\0" \ + "kernel_Off_fallback=0x03800000\0" \ + "kernel_ram=0x21500000\0" \ + "kernel_size=0x00400000\0" \ + "kernel_size_fallback=0x00400000\0" \ + "loads_echo=1\0" \ + "nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} " \ + "${kernel_size}\0" \ + "net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};" \ + "run nfsargs;run addip;upgrade_available;bootm " \ + "${kernel_ram};reset\0" \ + "netdev=eth0\0" \ + "nfsargs=run root_path;setenv bootargs ${bootargs} " \ + "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "at91sam9_wdt.wdt_timeout=16\0" \ + "partitionset_active=A\0" \ + "preboot=echo;echo Type 'run flash_self' to use kernel and root "\ + "filesystem on memory;echo Type 'run flash_nfs' to use kernel " \ + "from memory and root filesystem over NFS;echo Type 'run net_nfs' "\ + "to get Kernel over TFTP and mount root filesystem over NFS;echo\0"\ + "project_dir=systemone\0" \ + "root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0"\ + "rootfs=/dev/mtdblock5\0" \ + "rootfs_fallback=/dev/mtdblock7\0" \ + "setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops "\ + "root=${rootfs} rootfstype=jffs2 panic=7 " \ + "at91sam9_wdt.wdt_timeout=16\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "upgrade_available=0\0" +#endif + +#if defined(CONFIG_BOARD_TAURUS) +#define CONFIG_BOOTARGS CONFIG_BOOTARGS_TAURUS +#endif + +#if defined(CONFIG_BOARD_AXM) +#define CONFIG_BOOTARGS CONFIG_BOOTARGS_AXM +#endif #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 @@ -182,8 +246,8 @@ /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x0 -#define CONFIG_SPL_MAX_SIZE (14 * 1024) -#define CONFIG_SPL_STACK (16 * 1024) +#define CONFIG_SPL_MAX_SIZE (31 * SZ_512) +#define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K) #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN @@ -232,4 +296,5 @@ #define CONFIG_SYS_MCKR 0x1300 #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) #define CONFIG_SYS_AT91_PLLB 0x10193F05 + #endif -- 2.1.0

2 1

[U-Boot] [PATCH v3 0/2] arm, at91: add DFU support for the corvus board
by Heiko Schocher 11 Sep '15

11 Sep '15

add DFU support for the corvus board. While at it, do some minor board updates for this board, posted in the first patch of this series. Changes in v3: - add cover letter and post this patch in a patchserie with the DFU support - add a cover letter and post this patch with the board updates patch in a patchserie Changes in v2: - rebase to 0d339cf9a969f0c249713d3697e735184f1bd955 - use SZ_xM defines as Lukasz Majewski suggested - rebase to 0d339cf9a969f0c249713d3697e735184f1bd955 - fix changes introduced through commit: 01acd6abbdd5: usb: USB download gadget and functions config options coherent naming Heiko Schocher (2): at91: corvus: board updates corvus, dfu: add dfu support board/siemens/corvus/board.c | 23 ++++++++++++++++++++++- include/configs/corvus.h | 44 +++++++++++++++++++++++++++++++++++--------- 2 files changed, 57 insertions(+), 10 deletions(-) -- 2.1.0

2 4

[U-Boot] commit 620776d causes TFTP error: 'Unsupported option(s) requested' (8)
by Bin Meng 11 Sep '15

11 Sep '15

Hi, With latest u-boot/master, TFTP is seriously broken. => tftp 100000 bzImage Speed: 100, full duplex Using pch_gbe device TFTP from server 10.10.0.8; our IP address is 10.10.0.100; sending through gateway 10.10.0.1 Filename 'bzImage'. Load address: 0x100000 Loading: T TFTP error: 'Unsupported option(s) requested' (8) Starting again git bisect shows the following commit broke the TFTP commit 620776d734e4b126c407f636bda825a594a17723 Author: Pavel Machek <pavel(a)denx.de> Date: Tue Aug 18 14:34:26 2015 +0200 tftp: adjust settings to be suitable for 100Mbit ethernet Adjust timouts and retry counts to be suitable for loaded ethernet network. With 5 seconds timeout, 10 retries maximum, tftp is impossible even on local network with single full-speed TCP connection. 100msec timeout should be suitable for most networks tftp is used on, that is local ethernets. Timeout count really needs to be way higher, as lost packets are normal when TCP is running over the same network. Enforce 10msec minimum. Signed-off-by: Pavel Machek <pavel(a)denx.de> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> Can we get this fixed ASAP? Thanks, Regards, Bin

7 19

[U-Boot] [PATCH 0/8] x86: quark: Convert to driver model
by Bin Meng 10 Sep '15

10 Sep '15

This series converts to use driver model for PCI/USB/ETH on Intel Galileo board. Note this series depend on Simon's patch [1] below, which fixes the issue that pci enumeration is not automatically triggered when using pci config read/write apis. Boot time performance degradation is observed with the conversion to use dm pci. Intel Quark SoC has a low end x86 processor with only 400MHz frequency and the most time consuming part is with MRC. Each MRC register programming requires indirect access via pci bus. With dm pci, accessing pci configuration space has some overhead. Unfortunately this single access overhead gets accumulated in the whole MRC process, and finally leads to twice boot time (25s) than before (12s). To speed up the boot, create an optimized version of pci config read/write routines without bothering to go through driver model. Now it only takes about 3 seconds to finish MRC, which is really fast (8 times faster than dm pci, or 4 times faster than before). [1]: http://patchwork.ozlabs.org/patch/509736/ Bin Meng (8): x86: quark: Make host bridge (b.d.f=0.0.0) visible dm: pci: Allow skipping device configuration x86: Convert to use driver model pci on quark/galileo x86: galileo: Convert to use CONFIG_DM_USB net: designware: Fix build warnings net: designware: Add support to PCI designware devices x86: Convert to use driver model eth on quark/galileo x86: quark: Optimize MRC execution time arch/x86/cpu/quark/msg_port.c | 59 +++++++++++++++++++++++++++---------------- arch/x86/cpu/quark/pci.c | 46 +-------------------------------- arch/x86/cpu/quark/quark.c | 27 +++----------------- arch/x86/dts/galileo.dts | 8 ++++-- configs/galileo_defconfig | 5 +++- drivers/net/designware.c | 47 +++++++++++++++++++++++++++++++--- drivers/pci/pci-uclass.c | 3 +++ include/configs/galileo.h | 12 --------- 8 files changed, 98 insertions(+), 109 deletions(-) -- 1.8.2.1

2 31

[U-Boot] [PATCH] usb: gadget: ci_udc: implement usb_ep_ops dequeue callback
by Peng Fan 10 Sep '15

10 Sep '15

Implement endpoint dequeue callback function. Without this function, uboot will hang when executing fastboot comamnd. See following flow: "fastboot_tx_write_str->fastboot_tx_write->usb_ep_dequeue->ep->ops->dequeue" without implement ci_udc dequeue function, ep->ops->dequeue is NULL, then uboot will hang. Tested on mx6qsabresd board with fastboot enabled. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: "Łukasz Majewski" <l.majewski(a)samsung.com> Cc: Marek Vasut <marex(a)denx.de> --- drivers/usb/gadget/ci_udc.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 3e8eb87..f9374b3 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -87,6 +87,7 @@ static int ci_ep_enable(struct usb_ep *ep, static int ci_ep_disable(struct usb_ep *ep); static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags); +static int ci_ep_dequeue(struct usb_ep *ep, struct usb_request *req); static struct usb_request * ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); @@ -99,6 +100,7 @@ static struct usb_ep_ops ci_ep_ops = { .enable = ci_ep_enable, .disable = ci_ep_disable, .queue = ci_ep_queue, + .dequeue = ci_ep_dequeue, .alloc_request = ci_ep_alloc_request, .free_request = ci_ep_free_request, }; @@ -525,6 +527,32 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) writel(bit, &udc->epprime); } +static int ci_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) +{ + struct ci_ep *ci_ep = container_of(_ep, struct ci_ep, ep); + struct ci_req *ci_req; + + list_for_each_entry(ci_req, &ci_ep->queue, queue) { + if (&ci_req->req == _req) + break; + } + + if (&ci_req->req != _req) + return -EINVAL; + + list_del_init(&ci_req->queue); + + if (ci_req->req.status == -EINPROGRESS) { + ci_req->req.status = -ECONNRESET; + if (ci_req->req.complete) + ci_req->req.complete(_ep, _req); + } + + debug("callback completed\n"); + + return 0; +} + static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags) { -- 1.8.4

4 11

[U-Boot] [PATCH V2] usb: gadget: ci_udc: implement usb_ep_ops dequeue callback
by Peng Fan 10 Sep '15

10 Sep '15

Implement endpoint dequeue callback function. Without this function, uboot will hang when executing fastboot comamnd. See following flow: "fastboot_tx_write_str->fastboot_tx_write->usb_ep_dequeue->ep->ops->dequeue" without implement ci_udc dequeue function, ep->ops->dequeue is NULL, then uboot will hang. Tested on mx6qsabresd board with fastboot enabled. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: "Łukasz Majewski" <l.majewski(a)samsung.com> Cc: Marek Vasut <marex(a)denx.de> --- Changes v2: discard useless "debug("callback completed\n")" info. drivers/usb/gadget/ci_udc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 3e8eb87..c0d23a4 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -87,6 +87,7 @@ static int ci_ep_enable(struct usb_ep *ep, static int ci_ep_disable(struct usb_ep *ep); static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags); +static int ci_ep_dequeue(struct usb_ep *ep, struct usb_request *req); static struct usb_request * ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); @@ -99,6 +100,7 @@ static struct usb_ep_ops ci_ep_ops = { .enable = ci_ep_enable, .disable = ci_ep_disable, .queue = ci_ep_queue, + .dequeue = ci_ep_dequeue, .alloc_request = ci_ep_alloc_request, .free_request = ci_ep_free_request, }; @@ -525,6 +527,30 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) writel(bit, &udc->epprime); } +static int ci_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) +{ + struct ci_ep *ci_ep = container_of(_ep, struct ci_ep, ep); + struct ci_req *ci_req; + + list_for_each_entry(ci_req, &ci_ep->queue, queue) { + if (&ci_req->req == _req) + break; + } + + if (&ci_req->req != _req) + return -EINVAL; + + list_del_init(&ci_req->queue); + + if (ci_req->req.status == -EINPROGRESS) { + ci_req->req.status = -ECONNRESET; + if (ci_req->req.complete) + ci_req->req.complete(_ep, _req); + } + + return 0; +} + static int ci_ep_queue(struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags) { -- 1.8.4

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[U-Boot] [PATCH v4 0/9] Add support for hi6220 SoC and HiKey 96boards CE board.
by Peter Griffin 09 Sep '15

09 Sep '15

Hi Albert / Tom, This series adds support for the first 96boards consumer edition HiKey board. More information can be found about this board at the following link https://www.96boards.org/products/hikey/. This initial port adds support for: - 1) Serial 2) eMMC and sd card 3) USB 4) GPIO It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable. Some instructions on exactly how to compile everything (l-loader, with Arm Trusted Firmware, which then loads u-boot) is documented in the README found in the board/hisilicon/hikey directory. A basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf A rather pleasant side effect of rebasing to v2015.07-rc2 is that the two main bugs with the v1 series (that I new about at least) are resolved. DHCP now works correctly, and USB mass storage devices are also enumerated). The plan is once basic support is merged to u-boot, and upstream Linux kernel has DT which supports GPIO, UART and MMC, we can migrate this u-boot port over to using DT for configuration. Changes since v3: - Update to use config_distro_bootcmd.h (Sjoerd) - Remove CONFIG_BOOTDELAY (Sjoerd) Changes since v2: - errno.h should go above malloc.h (Simon) - drop #ifdef CONFIG_DM_GPIO and add TODO (Simon) - remove gd->flags = 0; (Simon) - Remove icache_enable() (Simon / Rob) - Added a pinmux driver for hi6220 (Simon) - Added a pmic driver for hi6553 (Simon) - Convert to structs for register I/O (Simon) - Remove () around simple constants (Simon) - Update default bootcmd (Rob) - user kernel_addr_r etc in default env (Rob) - Various typo's (Rob) - use board_usb_init() to configure phy/clocks (Rob) - Remove some more unnecessary CONFIG_FS* options (Rob) - Update default kernel load address (Rob) - Update default kernel cmdline (Rob) Changes since v1: - Rename vendor to hisilicon not 96boards (Rob) - Get rid of aemv8a vexpress leftover (Rob) - Remove __weak on misc_init_r (Rob) - Remove unnecessary LINUX_BOOT_PARAM_ADDR (Rob) - COUNTER_FREQUENCY in decimal to avoid comment (Rob) - Remove leftover V2M* from vexpress (Rob) - Migrate configs/hikey.h over to use config_distro_defaults.h (Rob) - Remove custom u-boot prompt (Rob) - Enable icache - Remove custom delay function, as mdelay/udelay work fine (Rob) - Update CONFIG_SYS_LOAD_ADDR to 0x80000 (Rob) - Use suggested macro for declaring gpio addresses (Marek) - Zap dead Macros (Marek) - Use calloc instead of malloc (Marek) - Reduce PHYS_RAM by 16Mb to accomodate OPTEE in latest ATF code (Peter) - Rebase on v2015.07-rc2 (Peter) - Add CONFIG_NET=y so that env callbacks work (Peter) - Add a README on how to build / flash u-boot (Simon) kind regards, Peter. Peter Griffin (9): usb: dwc2: Call board_usb_init() from usb_lowlevel_init() dm: gpio: hi6220: Add a hi6220 GPIO driver model driver. ARM: hi6220: Add register and bitfield definition header files. hisilicon: hi6220: Add a hi6220 pinmux driver. pmic: pmic_hi6553: Add a driver for the hi6553 pmic found on hikey board. mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller. ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board. ARM64: hikey: Add a README for this board. hikey: Add hikey-u-boot.mak arch/arm/Kconfig | 8 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/hisilicon/Makefile | 9 + arch/arm/cpu/armv8/hisilicon/pinmux.c | 184 +++++++++ arch/arm/include/asm/arch-hi6220/dwmmc.h | 8 + arch/arm/include/asm/arch-hi6220/gpio.h | 29 ++ arch/arm/include/asm/arch-hi6220/hi6220.h | 387 +++++++++++++++++++ .../include/asm/arch-hi6220/hi6220_regs_alwayson.h | 420 +++++++++++++++++++++ arch/arm/include/asm/arch-hi6220/periph.h | 30 ++ arch/arm/include/asm/arch-hi6220/pinmux.h | 83 ++++ board/hisilicon/hikey/Kconfig | 15 + board/hisilicon/hikey/Makefile | 8 + board/hisilicon/hikey/README | 160 ++++++++ board/hisilicon/hikey/hikey.c | 356 +++++++++++++++++ configs/hikey_defconfig | 5 + drivers/gpio/Makefile | 2 + drivers/gpio/hi6220_gpio.c | 95 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/hi6220_dw_mmc.c | 56 +++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_hi6553.c | 133 +++++++ drivers/usb/host/dwc2.c | 4 + hikey-u-boot.mak | 33 ++ include/configs/hikey.h | 159 ++++++++ include/power/hi6553_pmic.h | 79 ++++ 25 files changed, 2266 insertions(+) create mode 100644 arch/arm/cpu/armv8/hisilicon/Makefile create mode 100644 arch/arm/cpu/armv8/hisilicon/pinmux.c create mode 100644 arch/arm/include/asm/arch-hi6220/dwmmc.h create mode 100644 arch/arm/include/asm/arch-hi6220/gpio.h create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220.h create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h create mode 100644 arch/arm/include/asm/arch-hi6220/periph.h create mode 100644 arch/arm/include/asm/arch-hi6220/pinmux.h create mode 100644 board/hisilicon/hikey/Kconfig create mode 100644 board/hisilicon/hikey/Makefile create mode 100644 board/hisilicon/hikey/README create mode 100644 board/hisilicon/hikey/hikey.c create mode 100644 configs/hikey_defconfig create mode 100644 drivers/gpio/hi6220_gpio.c create mode 100644 drivers/mmc/hi6220_dw_mmc.c create mode 100644 drivers/power/pmic/pmic_hi6553.c create mode 100644 hikey-u-boot.mak create mode 100644 include/configs/hikey.h create mode 100644 include/power/hi6553_pmic.h -- 1.9.1

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[U-Boot] [PATCH 0/3] Introduce TPM driver model and STMicroelectronics ST33ZP24 TPMs
by Christophe Ricard 08 Sep '15

08 Sep '15

Hi, This patch serie introduce TPM driver model allowing to instantiate a TPM using U_BOOT_DEVICE macro for platform_data or device tree. As an information, there is no TCG transport protocol official specification for i2c for TPM1.2. The TPM uclass allows to support different kind of bus (LPC, I2C, SPI) keeping the TPM command duration in common. Also, this serie introduce TPM1.2 from STMicroelectronics ST33ZP24 with I2C and SPI support. It has been ported from existing Linux drivers. This has been tested on Beagleboard xM. Best Regards Christophe Christophe Ricard (3): tpm: Move tpm_tis_i2c to tpm_i2c_infineon tpm: Initial work to introduce TPM driver model tpm: Add st33zp24 tpm with i2c and spi phy README | 23 +- drivers/tpm/Makefile | 5 +- drivers/tpm/st33zp24/Makefile | 7 + drivers/tpm/st33zp24/i2c.c | 226 +++++++++++ drivers/tpm/st33zp24/spi.c | 286 ++++++++++++++ drivers/tpm/st33zp24/st33zp24.c | 454 ++++++++++++++++++++++ drivers/tpm/st33zp24/st33zp24.h | 29 ++ drivers/tpm/tpm.c | 275 +++---------- drivers/tpm/{tpm_tis_i2c.c => tpm_i2c_infineon.c} | 271 ++++++++----- drivers/tpm/tpm_private.h | 23 +- include/dm/platform_data/st33zp24_i2c.h | 28 ++ include/dm/platform_data/st33zp24_spi.h | 30 ++ include/dm/platform_data/tpm_i2c_infineon.h | 23 ++ include/dm/uclass-id.h | 1 + include/fdtdec.h | 5 +- lib/fdtdec.c | 2 + 16 files changed, 1351 insertions(+), 337 deletions(-) create mode 100644 drivers/tpm/st33zp24/Makefile create mode 100644 drivers/tpm/st33zp24/i2c.c create mode 100644 drivers/tpm/st33zp24/spi.c create mode 100644 drivers/tpm/st33zp24/st33zp24.c create mode 100644 drivers/tpm/st33zp24/st33zp24.h rename drivers/tpm/{tpm_tis_i2c.c => tpm_i2c_infineon.c} (70%) create mode 100644 include/dm/platform_data/st33zp24_i2c.h create mode 100644 include/dm/platform_data/st33zp24_spi.h create mode 100644 include/dm/platform_data/tpm_i2c_infineon.h -- 2.1.4

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[U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel
by Chin Liang See 08 Sep '15

08 Sep '15

Enable SDMMC calibration to determine the best setting for drvsel and smpsel. It will be triggered whenever there is a change of card frequency and bus width. This is to ensure reliable transmission between the controller and the card. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- drivers/mmc/socfpga_dw_mmc.c | 187 ++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 180 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index eb69aed..15e537c 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -11,25 +11,140 @@ #include <asm/arch/dwmmc.h> #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h> +#include "mmc_private.h" static const struct socfpga_clock_manager *clock_manager_base = (void *)SOCFPGA_CLKMGR_ADDRESS; static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS; -static void socfpga_dwmci_clksel(struct dwmci_host *host) +#define CAL_ROWS 7 +#define CAL_COLS 8 + +/* + * This function determines the largest rectangle filled with 1's and returns + * the middle. This functon can be optimized, for example using the algorithm + * from http://www.drdobbs.com/database/the-maximal-rectangle-problem/184410529 + * It currently takes less than 1ms, while creating the input data takes ~5ms + * so there is not a real need to optimize it. + */ +int find_calibration_point(unsigned char cal_results[CAL_ROWS][CAL_COLS], +unsigned int sum, unsigned int * cal_row, unsigned int * cal_col) { - unsigned int drvsel; - unsigned int smplsel; + /* Structure containing a rectangle candidate */ + typedef struct + { + unsigned char height; + unsigned char width; + unsigned short area; + } rect_cand_t; + + /* Array with the rectangle candidates */ + rect_cand_t rect_cands[CAL_ROWS * CAL_COLS]; + unsigned char cr_rect_cand = 0; + unsigned char height, width, k; + + /* No solution if all combinations fail */ + if(sum == 0) + return 1; + + /* Simple solution if all combinations pass */ + if(sum == (CAL_ROWS * CAL_COLS)) { + *cal_row = (CAL_ROWS - 1) / 2; + *cal_col = (CAL_COLS - 1) / 2; + return 0; + } + + /* + * Create list of all possible sub-rectangles, in descending area + * order + */ + for(height = CAL_ROWS; height >= 1; height--) { + for(width = CAL_COLS; width >= 1 ; width--){ + /* Add a new rectangle candidate */ + rect_cands[cr_rect_cand].height = height; + rect_cands[cr_rect_cand].width = width; + rect_cands[cr_rect_cand].area = height * width; + cr_rect_cand++; + + /* First candidate it always in the right position */ + if(cr_rect_cand == 1) + continue; + + /* + * Put the candidate in right location to maintain + * descending order + */ + for(k = cr_rect_cand - 1; k > 1; k--){ + if(rect_cands[k-1].area < rect_cands[k].area){ + rect_cand_t tmp = rect_cands[k-1]; + rect_cands[k-1] = rect_cands[k]; + rect_cands[k] = tmp; + } else + break; + } + } + } + + /* Try to fit the rectangle candidates, in descending area order */ + for(k = 0; k < CAL_ROWS * CAL_COLS; k++) { + unsigned char start_row, start_col; + unsigned rect_width = rect_cands[k].width; + unsigned rect_height = rect_cands[k].height; + + /* Find the row and column where the candidate fits */ + for (start_col = 0; start_col < (CAL_COLS - rect_width + 1); + start_col++) { + for (start_row = 0; start_row < (CAL_ROWS - + rect_height + 1); start_row++) { + unsigned ok = 1; + unsigned add_col, add_row; + + /* Determine if the rectangle fits here */ + for (add_col = 0; (add_col < rect_width) && ok; + add_col++) { + for (add_row = 0; add_row < rect_height; + add_row++) { + if (!cal_results + [start_row+add_row][start_col + + add_col]) { + ok = 0; + break; + } + } + } + + /* + * Return 'middle' of rectangle in case of + * success + */ + if (ok) { + if(rect_width > 1) + rect_width--; + + if(rect_height > 1) + rect_height--; + + *cal_row = start_row + + (rect_height / 2); + *cal_col = start_col + (rect_width / 2); + + return 0; + } + } + } + } + + /* We could not fit any rectangle - return failure */ + return 1; +} +void socfpga_dwmmc_set_clksel(unsigned int drvsel, unsigned int smplsel) +{ /* Disable SDMMC clock. */ clrbits_le32(&clock_manager_base->per_pll.en, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); - /* Configures drv_sel and smpl_sel */ - drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; - smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; - debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), &system_manager_base->sdmmcgrp_ctrl); @@ -42,6 +157,64 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); } +/* + * This functions calirates the drvsel and smplsel by trying all possible + * values and selecting the best combnation + */ +void socfpga_dwmmc_calibrate(struct dwmci_host *host) +{ + int err = 0; + unsigned char cal_results[CAL_ROWS][CAL_COLS]; + unsigned int sum = 0; + unsigned int row, col, drvsel, smplsel; + + struct mmc *mmc = (struct mmc *)host->mmc; + if (mmc == NULL) { + printf("struct mmc is NULL\n"); + hang(); + } + + printf("%s: Calibration started.\n", __func__); + + for (row = 0; row < CAL_ROWS; row++) { + for (col = 0; col < CAL_COLS; col++) { + drvsel = row + 1; + smplsel = col; + socfpga_dwmmc_set_clksel(drvsel, smplsel); + cal_results[row][col] = !(mmc_set_blocklen(mmc, + mmc->read_bl_len)); + sum += cal_results[row][col]; + } + } + + debug("%s: Calibration raw data:\n", __func__); + for(row = 0; row < CAL_ROWS; row++) { + debug("\t"); + for(col = 0; col < CAL_COLS; col++) + debug("%d ", cal_results[row][col]); + debug("\n"); + } + + err = find_calibration_point(cal_results, sum, &drvsel, &smplsel); + + if(err) { + printf("%s: Calibration failed.\n", __func__); + hang(); + } else + printf("%s: Calibration passed: drvsel = %d " + "smplsel = %d.\n", __func__, drvsel, smplsel); + + socfpga_dwmmc_set_clksel(drvsel, smplsel); + + /* re-write in case accidentally overwrite with junk */ + mmc_set_blocklen(mmc, mmc->read_bl_len); +} + +void socfpga_dwmci_clksel(struct dwmci_host *host) +{ + socfpga_dwmmc_calibrate(host); +} + int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) { struct dwmci_host *host; -- 1.7.7.4

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