July 2015 - U-Boot

[U-Boot] [PATCH v2 07/20] sf: Kconfig: Add SPI_FLASH_DATAFLASH entry
by Jagan Teki 01 Jul '15

01 Jul '15

Added SPI_FLASH_DATAFLASH entry on Kconfig with help description. data flash driver comes with good decription, hence moved the same on to kconfig help decription. Signed-off-by: Jagan Teki <jteki(a)openedev.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Cc: Haikun Wang <haikun.wang(a)freescale.com> --- Changes for v2: - Added more help decription. drivers/mtd/spi/Kconfig | 15 +++++++++++++++ drivers/mtd/spi/sf_dataflash.c | 10 ---------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 80fe93e..a4160fd 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -34,6 +34,21 @@ config SPI_FLASH If unsure, say N +config SPI_FLASH_DATAFLASH + bool "AT45xxx DataFlash support" + depends on SPI_FLASH && DM_SPI_FLASH + help + Enable the access for SPI-flash-based AT45xxx DataFlash chips. + DataFlash is a kind of SPI flash. Most AT45 chips have two buffers + in each chip, which may be used for double buffered I/O; but this + driver doesn't (yet) use these for any kind of i/o overlap or prefetching. + + Sometimes DataFlash is packaged in MMC-format cards, although the + MMC stack can't (yet?) distinguish between MMC and DataFlash + protocols during enumeration. + + If unsure, say N + config SPI_FLASH_MTD bool "SPI Flash MTD support" depends on SPI_FLASH diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c index d287db8..3111f4f 100644 --- a/drivers/mtd/spi/sf_dataflash.c +++ b/drivers/mtd/spi/sf_dataflash.c @@ -19,16 +19,6 @@ #include "sf_internal.h" -/* - * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in - * each chip, which may be used for double buffered I/O; but this driver - * doesn't (yet) use these for any kind of i/o overlap or prefetching. - * - * Sometimes DataFlash is packaged in MMC-format cards, although the - * MMC stack can't (yet?) distinguish between MMC and DataFlash - * protocols during enumeration. - */ - /* reads can bypass the buffers */ #define OP_READ_CONTINUOUS 0xE8 #define OP_READ_PAGE 0xD2 -- 1.9.1

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[U-Boot] [PATCH 0/5] sf: defconfig/kconfig updates
by Jagan Teki 01 Jul '15

01 Jul '15

defconfig/kconfig changes related to sf. Jagan Teki (5): README: Remove CONFIG_SPI_FLASH_MTD help text defconfig: Move CONFIG_SPI_FLASH_BAR from configs sf: Kconfig: Add SPI_FLASH_BAR entry README: Remove CONFIG_SPI_FLASH_BAR help text README: Remove CONFIG_SPI_FLASH_DATAFLASH help text README | 19 ------------------- configs/alt_defconfig | 1 + configs/am43xx_evm_defconfig | 1 + configs/bg0900_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + configs/gose_defconfig | 1 + configs/koelsch_defconfig | 1 + configs/lager_defconfig | 1 + configs/maxbcm_defconfig | 1 + configs/mx6sxsabresd_defconfig | 1 + configs/porter_defconfig | 1 + configs/silk_defconfig | 1 + drivers/mtd/spi/Kconfig | 8 ++++++++ include/configs/alt.h | 1 - include/configs/am43xx_evm.h | 1 - include/configs/bg0900.h | 1 - include/configs/dra7xx_evm.h | 1 - include/configs/gose.h | 1 - include/configs/koelsch.h | 1 - include/configs/lager.h | 1 - include/configs/maxbcm.h | 1 - include/configs/mx6sxsabresd.h | 1 - include/configs/porter.h | 1 - include/configs/silk.h | 1 - 24 files changed, 19 insertions(+), 30 deletions(-) -- 1.9.1

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[U-Boot] [PATCH v2 05/20] sf: Kconfig: Update SPI_FLASH entry
by Jagan Teki 01 Jul '15

01 Jul '15

Updated SPI_FLASH entry on Kconfig with depends on and along with config help description. Signed-off-by: Jagan Teki <jteki(a)openedev.com> --- Changes for v2: - Removed "depends on CMD_SF" as it's not in defconfig drivers/mtd/spi/Kconfig | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index aa3468b..a8789a5 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -1,14 +1,5 @@ menu "SPI Flash Support" -config SPI_FLASH - bool "Enable SPI Flash support" - help - Enable the legacy SPI flash support. This will include basic - standard support for things like probing, read / write, and - erasing through the MTD layer. - - If unsure, say N - config DM_SPI_FLASH bool "Enable Driver Model for SPI flash" depends on DM && DM_SPI @@ -34,4 +25,13 @@ config SPI_FLASH_SANDBOX device. Typically the contents of the emulated SPI flash device is stored in a file on the host filesystem. +config SPI_FLASH + bool "Legacy SPI Flash Interface support" + help + Enable the legacy SPI flash support. This will include basic + standard support for things like probing, read / write, and + erasing through cmd_sf interface. + + If unsure, say N + endmenu # menu "SPI Flash Support" -- 1.9.1

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[U-Boot] [PATCH v4 14/16] dm: spi: xilinx_spi: Convert to driver model
by Jagan Teki 01 Jul '15

01 Jul '15

This converts the xilinx spi driver to use the driver model. Signed-off-by: Jagan Teki <jteki(a)openedev.com> Acked-by: Simon Glass <sjg(a)chromium.org> Cc: Michal Simek <michal.simek(a)xilinx.com> --- Changes for v4: - Removed cs_info ops, as it need to proper testing to verify. Changes for v3: - Get the cs number from xfer using dm_spi_slave_platdata Changes for v2: - Rebase to master drivers/spi/xilinx_spi.c | 200 ++++++++++++++++++++++++++--------------------- 1 file changed, 112 insertions(+), 88 deletions(-) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 650e494..4b0b50f 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -4,6 +4,7 @@ * Supports 8 bit SPI transfers only, with or w/o FIFO * * Based on bfin_spi.c, by way of altera_spi.c + * Copyright (c) 2015 Jagan Teki <jteki(a)openedev.com> * Copyright (c) 2012 Stephan Linz <linz(a)li-pro.net> * Copyright (c) 2010 Graeme Smecher <graeme.smecher(a)mail.mcgill.ca> * Copyright (c) 2010 Thomas Chou <thomas(a)wytron.com.tw> @@ -14,6 +15,8 @@ #include <config.h> #include <common.h> +#include <dm.h> +#include <errno.h> #include <malloc.h> #include <spi.h> @@ -79,7 +82,7 @@ #endif /* xilinx spi register set */ -struct xilinx_spi_reg { +struct xilinx_spi_regs { u32 __space0__[7]; u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */ u32 ipisr; /* IP Interrupt Status Register (IPISR) */ @@ -97,113 +100,75 @@ struct xilinx_spi_reg { u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */ }; -/* xilinx spi slave */ -struct xilinx_spi_slave { - struct spi_slave slave; - struct xilinx_spi_reg *regs; +/* xilinx spi priv */ +struct xilinx_spi_priv { + struct xilinx_spi_regs *regs; unsigned int freq; unsigned int mode; }; -static inline struct xilinx_spi_slave *to_xilinx_spi_slave( - struct spi_slave *slave) -{ - return container_of(slave, struct xilinx_spi_slave, slave); -} - static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST; -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +static int xilinx_spi_probe(struct udevice *bus) { - return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32; -} + struct xilinx_spi_priv *priv = dev_get_priv(bus); + struct xilinx_spi_regs *regs = priv->regs; -void spi_cs_activate(struct spi_slave *slave) -{ - struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq]; - writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr); -} + writel(SPISSR_RESET_VALUE, &regs->srr); -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); - - writel(SPISSR_OFF, &xilspi->regs->spissr); -} - -void spi_init(void) -{ - /* do nothing */ + return 0; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +static void spi_cs_activate(struct udevice *dev, uint cs) { - struct xilinx_spi_slave *xilspi; + struct udevice *bus = dev_get_parent(dev); + struct xilinx_spi_priv *priv = dev_get_priv(bus); + struct xilinx_spi_regs *regs = priv->regs; - if (!spi_cs_is_valid(bus, cs)) { - printf("XILSPI error: unsupported bus %d / cs %d\n", bus, cs); - return NULL; - } - - xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs); - if (!xilspi) { - printf("XILSPI error: malloc of SPI structure failed\n"); - return NULL; - } - xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus]; - xilspi->freq = max_hz; - xilspi->mode = mode; - debug("spi_setup_slave: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", - bus, cs, xilspi->regs, xilspi->mode, xilspi->freq); - - writel(SPISSR_RESET_VALUE, &xilspi->regs->srr); - - return &xilspi->slave; + writel(SPISSR_ACT(cs), &regs->spissr); } -void spi_free_slave(struct spi_slave *slave) +static void spi_cs_deactivate(struct udevice *dev) { - struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + struct udevice *bus = dev_get_parent(dev); + struct xilinx_spi_priv *priv = dev_get_priv(bus); + struct xilinx_spi_regs *regs = priv->regs; - free(xilspi); + writel(SPISSR_OFF, &regs->spissr); } -int spi_claim_bus(struct spi_slave *slave) +static int xilinx_spi_claim_bus(struct udevice *dev) { - struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); - u32 spicr; - - debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs); - writel(SPISSR_OFF, &xilspi->regs->spissr); + struct udevice *bus = dev_get_parent(dev); + struct xilinx_spi_priv *priv = dev_get_priv(bus); + struct xilinx_spi_regs *regs = priv->regs; - spicr = XILSPI_SPICR_DFLT_ON; - if (xilspi->mode & SPI_LSB_FIRST) - spicr |= SPICR_LSB_FIRST; - if (xilspi->mode & SPI_CPHA) - spicr |= SPICR_CPHA; - if (xilspi->mode & SPI_CPOL) - spicr |= SPICR_CPOL; - if (xilspi->mode & SPI_LOOP) - spicr |= SPICR_LOOP; + writel(SPISSR_OFF, &regs->spissr); + writel(XILSPI_SPICR_DFLT_ON, &regs->spicr); - writel(spicr, &xilspi->regs->spicr); return 0; } -void spi_release_bus(struct spi_slave *slave) +static int xilinx_spi_release_bus(struct udevice *dev) { - struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + struct udevice *bus = dev_get_parent(dev); + struct xilinx_spi_priv *priv = dev_get_priv(bus); + struct xilinx_spi_regs *regs = priv->regs; - debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs); - writel(SPISSR_OFF, &xilspi->regs->spissr); - writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr); + writel(SPISSR_OFF, &regs->spissr); + writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr); + + return 0; } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { - struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + struct udevice *bus = dev_get_parent(dev); + struct xilinx_spi_priv *priv = dev_get_priv(bus); + struct xilinx_spi_regs *regs = priv->regs; + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); /* assume spi core configured to do 8 bit transfers */ unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS; const unsigned char *txp = dout; @@ -212,7 +177,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, unsigned global_timeout; debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", - slave->bus, slave->cs, bitlen, bytes, flags); + bus->seq, slave_plat->cs, bitlen, bytes, flags); if (bitlen == 0) goto done; @@ -225,8 +190,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } /* empty read buffer */ - while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) { - readl(&xilspi->regs->spidrr); + while (rxecount && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { + readl(&regs->spidrr); rxecount--; } @@ -236,11 +201,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + spi_cs_activate(dev, slave_plat->cs); /* at least 1usec or greater, leftover 1 */ - global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : - (XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1; + global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : + (XILSPI_MAX_XFER_BITS * 1000000 / priv->freq) + 1; while (bytes--) { unsigned timeout = global_timeout; @@ -249,8 +214,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, debug("spi_xfer: tx:%x ", d); /* write out and wait for processing (receive data) */ - writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr); - while (timeout && readl(&xilspi->regs->spisr) + writel(d & SPIDTR_8BIT_MASK, &regs->spidtr); + while (timeout && readl(&regs->spisr) & SPISR_RX_EMPTY) { timeout--; udelay(1); @@ -262,7 +227,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } /* read Rx element and push into data in buffer */ - d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK; + d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK; if (rxp) *rxp++ = d; debug("spi_xfer: rx:%x\n", d); @@ -270,7 +235,66 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, done: if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + spi_cs_deactivate(dev); return 0; } + +static int xilinx_spi_set_speed(struct udevice *bus, uint speed) +{ + struct xilinx_spi_priv *priv = dev_get_priv(bus); + + priv->freq = speed; + + debug("xilinx_spi_set_speed: regs=%p, mode=%d\n", priv->regs, + priv->freq); + + return 0; +} + +static int xilinx_spi_set_mode(struct udevice *bus, uint mode) +{ + struct xilinx_spi_priv *priv = dev_get_priv(bus); + struct xilinx_spi_regs *regs = priv->regs; + uint32_t spicr; + + spicr = readl(&regs->spicr); + if (priv->mode & SPI_LSB_FIRST) + spicr |= SPICR_LSB_FIRST; + if (priv->mode & SPI_CPHA) + spicr |= SPICR_CPHA; + if (priv->mode & SPI_CPOL) + spicr |= SPICR_CPOL; + if (priv->mode & SPI_LOOP) + spicr |= SPICR_LOOP; + + writel(spicr, &regs->spicr); + priv->mode = mode; + + debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs, + priv->mode); + + return 0; +} + +static const struct dm_spi_ops xilinx_spi_ops = { + .claim_bus = xilinx_spi_claim_bus, + .release_bus = xilinx_spi_release_bus, + .xfer = xilinx_spi_xfer, + .set_speed = xilinx_spi_set_speed, + .set_mode = xilinx_spi_set_mode, +}; + +static const struct udevice_id xilinx_spi_ids[] = { + { .compatible = "xlnx,xilinx-spi" }, + { } +}; + +U_BOOT_DRIVER(xilinx_spi) = { + .name = "xilinx_spi", + .id = UCLASS_SPI, + .of_match = xilinx_spi_ids, + .ops = &xilinx_spi_ops, + .priv_auto_alloc_size = sizeof(struct xilinx_spi_priv), + .probe = xilinx_spi_probe, +}; -- 1.9.1

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[U-Boot] [PATCH v3 00/16] spi/sf: Cleansup and driver model
by Jagan Teki 01 Jul '15

01 Jul '15

Few minor updates and tested on zynq board for driver model zynq_spi driver. Changes for v3: - Remove spi_chip_select() from probe and get cs from spi_xfer - Add spi1 in dts alias Changes for v2: - One change suggested from Simon to use dev_get_parent Jagan Teki (16): spi: Zap andes_spi driver spi: Zap ftssp010_spi driver spi: Zap oc_tiny_spi driver spi: xilinx_spi: Move header code to driver spi: xilinx_spi: Driver clean-up spi: davinci_spi: Move header code to driver spi: davinci_spi: Driver cleanup spi/sf: Minor cleanups dm: spi: zynq_spi: Convert to driver model zynq: Kconfig: Enable dm spi and spi_flash dts: zynq: Add zynq spi controller nodes spi: zynq_spi: Add fdt support in driver dts: zynq: Enable spi1 for zc770_xm010 board dm: spi: xilinx_spi: Convert to driver model spi: xilinx_spi: Add asm/io.h include file spi: Kconfig: Add Zynq SPI controller entry arch/arm/Kconfig | 2 + arch/arm/dts/zynq-7000.dtsi | 26 ++ arch/arm/dts/zynq-zc770-xm010.dts | 5 + doc/device-tree-bindings/spi/spi-zynq.txt | 29 ++ drivers/mtd/spi/sf_internal.h | 18 +- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 3 - drivers/spi/andes_spi.c | 284 ----------------- drivers/spi/andes_spi.h | 115 ------- drivers/spi/davinci_spi.c | 369 ++++++++++++++-------- drivers/spi/davinci_spi.h | 121 -------- drivers/spi/ftssp010_spi.c | 498 ------------------------------ drivers/spi/oc_tiny_spi.c | 245 --------------- drivers/spi/xilinx_spi.c | 329 +++++++++++++------- drivers/spi/xilinx_spi.h | 138 --------- drivers/spi/zynq_spi.c | 300 ++++++++++-------- include/spi.h | 2 +- include/spi_flash.h | 10 +- 18 files changed, 713 insertions(+), 1789 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-zynq.txt delete mode 100644 drivers/spi/andes_spi.c delete mode 100644 drivers/spi/andes_spi.h delete mode 100644 drivers/spi/davinci_spi.h delete mode 100644 drivers/spi/ftssp010_spi.c delete mode 100644 drivers/spi/oc_tiny_spi.c delete mode 100644 drivers/spi/xilinx_spi.h -- 1.9.1

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[U-Boot] [PATCH] ARM: UniPhier: add IDs for PH1-Pro5, ProXstream2, PH1-LD6b
by Masahiro Yamada 01 Jul '15

01 Jul '15

This prepares for new SoCs support. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/cpu_info.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index c4ba6d2..5d9ed84 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -34,6 +34,15 @@ int print_cpuinfo(void) case 0x29: puts("PH1-sLD8 (MN2WS0270)"); break; + case 0x2A: + puts("PH1-Pro5 (MN2WS0300)"); + break; + case 0x2E: + puts("ProXstream2 (MN2WS0310)"); + break; + case 0x2F: + puts("PH1-LD6b (MN2WS0320)"); + break; default: printf("Unknown Processor ID (0x%x)\n", revision); return -1; -- 1.9.1

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[U-Boot] [PATCH 1/2] ARM: dts: UniPhier: sync device trees with the Linux kernel
by Masahiro Yamada 01 Jul '15

01 Jul '15

This makes code diff much easier. Device trees describe hardware attributes, which are independent of software architecture. It generally makes sense to synchronize them beyond software projects. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/dts/uniphier-ph1-ld4.dtsi | 47 +++++++++++++++++++++++++++++++++--- arch/arm/dts/uniphier-ph1-pro4.dtsi | 48 ++++++++++++++++++++++++++++++++++--- arch/arm/dts/uniphier-ph1-sld3.dtsi | 48 ++++++++++++++++++++++++++++++++++--- arch/arm/dts/uniphier-ph1-sld8.dtsi | 47 +++++++++++++++++++++++++++++++++--- 4 files changed, 178 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi index c200838..c355395 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi @@ -1,9 +1,7 @@ /* * Device Tree Source for UniPhier PH1-LD4 SoC * - * Copyright (C) 2014-2015 Panasonic Corporation - * Copyright (C) 2015 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> + * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro(a)socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -24,11 +22,26 @@ }; }; + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; uart0: serial@54006800 { compatible = "socionext,uniphier-uart"; @@ -94,6 +107,12 @@ status = "disabled"; }; + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; @@ -112,6 +131,28 @@ reg = <0x5a820100 0x100>; }; + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + }; + nand: nand@68000000 { compatible = "denali,denali-nand-dt"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index 8195266..5c82df7 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -1,9 +1,7 @@ /* * Device Tree Source for UniPhier PH1-Pro4 SoC * - * Copyright (C) 2014-2015 Panasonic Corporation - * Copyright (C) 2015 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> + * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro(a)socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,6 +14,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; @@ -30,11 +29,26 @@ }; }; + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; uart0: serial@54006800 { compatible = "socionext,uniphier-uart"; @@ -120,6 +134,12 @@ status = "ok"; }; + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + usb2: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; @@ -144,6 +164,28 @@ reg = <0x65c00000 0x100>; }; + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + }; + nand: nand@68000000 { compatible = "denali,denali-nand-dt"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index 44b1989..1f93bb9 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -1,9 +1,7 @@ /* * Device Tree Source for UniPhier PH1-sLD3 SoC * - * Copyright (C) 2014-2015 Panasonic Corporation - * Copyright (C) 2015 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> + * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro(a)socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,6 +14,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; @@ -30,11 +29,48 @@ }; }; + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + timer@20000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@20000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@20001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x20001000 0x1000>, + <0x20000100 0x100>; + }; uart0: serial@54006800 { compatible = "socionext,uniphier-uart"; @@ -93,6 +129,12 @@ status = "disabled"; }; + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi index d9f61c2..4f291f7 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi @@ -1,9 +1,7 @@ /* * Device Tree Source for UniPhier PH1-sLD8 SoC * - * Copyright (C) 2014-2015 Panasonic Corporation - * Copyright (C) 2015 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> + * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro(a)socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -24,11 +22,26 @@ }; }; + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + interrupt-parent = <&intc>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; uart0: serial@54006800 { compatible = "socionext,uniphier-uart"; @@ -94,6 +107,12 @@ status = "disabled"; }; + system-bus-controller-misc@59800000 { + compatible = "socionext,uniphier-system-bus-controller-misc", + "syscon"; + reg = <0x59800000 0x2000>; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; @@ -112,6 +131,28 @@ reg = <0x5a820100 0x100>; }; + timer@60000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x60000200 0x20>; + interrupts = <1 11 0x104>; + clocks = <&arm_timer_clk>; + }; + + timer@60000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x60000600 0x20>; + interrupts = <1 13 0x104>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@60001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x60001000 0x1000>, + <0x60000100 0x100>; + }; + nand: nand@68000000 { compatible = "denali,denali-nand-dt"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; -- 1.9.1

1 3

[U-Boot] [PATCH v2] ARM: UniPhier: drop special CONFIG_AUTOBOOT_ settings
by Masahiro Yamada 01 Jul '15

01 Jul '15

There is no good reason to use a particular key to stop autobooting. The default allows us to stop the autoboot with any key input. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- Changes in v2: - Rebase on commit 7853d76b0 configs/ph1_ld4_defconfig | 4 ---- configs/ph1_pro4_defconfig | 4 ---- configs/ph1_sld8_defconfig | 4 ---- 3 files changed, 12 deletions(-) diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 650201a..a71511c 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -7,10 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_XIMG is not set # CONFIG_CMD_ENV_EXISTS is not set CONFIG_CMD_NAND=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 7d8d9cc..d02712e 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -6,10 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_XIMG is not set # CONFIG_CMD_ENV_EXISTS is not set CONFIG_CMD_NAND=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 90c44ac..ee4cebc 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -7,10 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" -CONFIG_AUTOBOOT_DELAY_STR="d" -CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_XIMG is not set # CONFIG_CMD_ENV_EXISTS is not set CONFIG_CMD_NAND=y -- 1.9.1

1 2

[U-Boot] Marvell Armada XP SATA support
by Anton Schubert 01 Jul '15

01 Jul '15

Hello, we are trying to replace an old marvell uboot on mv78260 with the current version, but noticed that there doesn't seem to be a driver for the SATA controller. Are there any plans to support SATA on Armada XP or is our only option to migrate the old driver? Regards Anton

3 11

[U-Boot] [PATCH 11/11] x86: Configure VESA parameters before loading Linux kernel
by Bin Meng 01 Jul '15

01 Jul '15

Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Tested-by: Jian Luo <jian.luo4(a)boschrexroth.de> --- arch/x86/include/asm/zimage.h | 1 + arch/x86/lib/zimage.c | 2 ++ drivers/pci/pci_rom.c | 28 ++++++++++++++++++++++++++++ include/vbe.h | 4 ++-- 4 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 8e7dd42..bf351ed 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -38,5 +38,6 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, ulong *load_addressp); int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, unsigned long initrd_addr, unsigned long initrd_size); +void setup_video(struct screen_info *screen_info); #endif diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index c3f8a73..144471c 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -273,6 +273,8 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, build_command_line(cmd_line, auto_boot); } + setup_video(&setup_base->screen_info); + return 0; } diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 4a91033..a33efae 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -31,6 +31,7 @@ #include <pci_rom.h> #include <vbe.h> #include <video_fb.h> +#include <linux/screen_info.h> #ifdef CONFIG_HAVE_ACPI_RESUME #include <asm/acpi.h> @@ -229,6 +230,33 @@ int vbe_get_video_info(struct graphic_device *gdev) #endif } +void setup_video(struct screen_info *screen_info) +{ +#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE + struct vesa_mode_info *vesa = &mode_info.vesa; + + screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB; + + screen_info->lfb_width = vesa->x_resolution; + screen_info->lfb_height = vesa->y_resolution; + screen_info->lfb_depth = vesa->bits_per_pixel; + screen_info->lfb_linelength = vesa->bytes_per_scanline; + screen_info->lfb_base = vesa->phys_base_ptr; + screen_info->lfb_size = + ALIGN(screen_info->lfb_linelength * screen_info->lfb_height, + 65536); + screen_info->lfb_size >>= 16; + screen_info->red_size = vesa->red_mask_size; + screen_info->red_pos = vesa->red_mask_pos; + screen_info->green_size = vesa->green_mask_size; + screen_info->green_pos = vesa->green_mask_pos; + screen_info->blue_size = vesa->blue_mask_size; + screen_info->blue_pos = vesa->blue_mask_pos; + screen_info->rsvd_size = vesa->reserved_mask_size; + screen_info->rsvd_pos = vesa->reserved_mask_pos; +#endif +} + int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method) { struct pci_rom_header *rom, *ram; diff --git a/include/vbe.h b/include/vbe.h index c5deee9..1a86db8 100644 --- a/include/vbe.h +++ b/include/vbe.h @@ -12,7 +12,7 @@ #define _VBE_H /* these structs are for input from and output to OF */ -struct __packed screen_info { +struct __packed vbe_screen_info { u8 display_type; /* 0=NONE, 1= analog, 2=digital */ u16 screen_width; u16 screen_height; @@ -23,7 +23,7 @@ struct __packed screen_info { u8 edid_block_zero[128]; }; -struct __packed screen_info_input { +struct __packed vbe_screen_info_input { u8 signature[4]; u16 size_reserved; u8 monitor_number; -- 1.8.2.1

2 1