July 2015 - U-Boot

[U-Boot] [PATCH v2 1/3] ARM: cache: add an empty stub function for invalidate/flush dcache
by Josh Wu 12 Sep '15

12 Sep '15

Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu. And each cpu can implement its own implementation. If not implemented by default it will use an empty function. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- Changes in v2: new added arch/arm/lib/cache.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 74cfde6..bc48f53 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -53,6 +53,15 @@ __weak void enable_caches(void) puts("WARNING: Caches not enabled\n"); } +__weak void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + /* An empty stub, real implementation should be in platform code */ +} +__weak void flush_dcache_range(unsigned long start, unsigned long stop) +{ + /* An empty stub, real implementation should be in platform code */ +} + #ifdef CONFIG_SYS_NONCACHED_MEMORY /* * Reserve one MMU section worth of address space below the malloc() area that -- 1.9.1

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[U-Boot] [PATCH] fat: handle paths that include ../
by Stephen Warren 12 Sep '15

12 Sep '15

The FAT code contains a special case to parse the root directory. This is needed since the root directory location/layout on disk is special cased for FAT12/16. In particular, the location and size of the FAT12/16 root directory is hard-coded and contiguous, whereas all FAT12/16 non-root directories, and all FAT32 directories, are stored in a non-contiguous fashion, with the layout represented by a linked-list of clusters in the FAT. If a file path contains ../ (for example /extlinux/../bcm2835-rpi-cm.dtb), it is possible to need to parse the root directory for the first element in the path (requiring application of the special case), then a sub- directory (in the general way), then re-parse the root directory (again requiring the special case). However, the current code in U-Boot only applies the special case for the very first path element, and never for any later path element. When reparsing the root directory without applying the special case, any file in a sector (or cluster?) other than the first sector/cluster of the root directory will not be found. This change modifies the non-root-dir-parsing loop of do_fat_read_at() to detect if it's walked back to the root directory, and if so, jumps back to the special case code that handles parsing of the root directory. This change was tested using sandbox by executing: ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0" ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /" ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux" ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/" ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/.." ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../" ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../backup" ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../backup/" ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../backup/.." ./u-boot -c "host bind 0 ../sd-p1.bin; ls host 0:0 /extlinux/../backup/../" ./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /bcm2835-rpi-cm.dtb" ./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /extlinux/../bcm2835-rpi-cm.dtb" ./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /backup/../bcm2835-rpi-cm.dtb" ./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /extlinux/..backup/../bcm2835-rpi-cm.dtb" ./u-boot -c "host bind 0 ../sd-p1.bin; load host 0:0 0 /extlinux/../backup/../bcm2835-rpi-cm.dtb" (/extlinux and /backup are in different sectors so trigger some different cases, and bcm2835-rpi-cm.dtb is in a sector of the root directory other than the first). In all honesty, this change is a bit of a hack, using goto and all. However, as demonstrated above it appears to work well in practice, is quite minimal, likely doesn't introduce any risk of regressions, and hopefully doesn't introduce any maintenance issues. The correct fix would be to collapse the root and non-root loops in do_fat_read_at() and get_dentfromdir() into a single loop that has a small special-case when moving from one sector to the next, to handle the layout difference of root/non-root directories. AFAIK all other aspects of directory parsing are identical. However, that's a much larger change which needs significantly more thought before it's implemented. Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- fs/fat/fat.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index bccc3e3ed8fd..a863644d6480 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -895,6 +895,7 @@ int do_fat_read_at(const char *filename, loff_t pos, void *buffer, strcpy(fnamecopy, filename); downcase(fnamecopy); +root_reparse: if (*fnamecopy == '\0') { if (!dols) goto exit; @@ -1180,6 +1181,34 @@ rootdir_done: if (isdir && !(dentptr->attr & ATTR_DIR)) goto exit; + /* + * If we are looking for a directory, and found a directory + * type entry, and the entry is for the root directory (as + * denoted by a cluster number of 0), jump back to the start + * of the function, since at least on FAT12/16, the root dir + * lives in a hard-coded location and needs special handling + * to parse, rather than simply following the cluster linked + * list in the FAT, like other directories. + */ + if (isdir && (dentptr->attr & ATTR_DIR) && !START(dentptr)) { + /* + * Modify the filename to remove the prefix that gets + * back to the root directory, so the initial root dir + * parsing code can continue from where we are without + * confusion. + */ + strcpy(fnamecopy, nextname ?: ""); + /* + * Set up state the same way as the function does when + * first started. This is required for the root dir + * parsing code operates in its expected environment. + */ + subname = ""; + cursect = mydata->rootdir_sect; + isdir = 0; + goto root_reparse; + } + if (idx >= 0) subname = nextname; } -- 1.9.1

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[U-Boot] [PATCH] git-mailrc: add Alexey as ARC maintainer
by Masahiro Yamada 12 Sep '15

12 Sep '15

It's easier to Cc him on ARC-releated patches. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- doc/git-mailrc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/doc/git-mailrc b/doc/git-mailrc index ddc4513..1335612 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -12,6 +12,7 @@ alias u-boot uboot # things simple and easy to look up/coordinate. alias aaribaud Albert Aribaud <albert.u.boot(a)aribaud.net> alias abiessmann Andreas Bießmann <andreas.devel(a)googlemail.com> +alias abrodkin Alexey Brodkin <alexey.brodkin(a)synopsys.com> alias afleming Andy Fleming <afleming(a)gmail.com> alias ag Anatolij Gustschin <agust(a)denx.de> alias alisonwang Alison Wang <alison.wang(a)freescale.com> @@ -50,9 +51,11 @@ alias vapier Mike Frysinger <vapier(a)gentoo.org> alias wd Wolfgang Denk <wd(a)denx.de> # Architecture aliases -alias arch arm, avr32, bfin, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, sparc, x86 +alias arch arc, arm, avr32, bfin, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, sparc, x86 alias arches arch +alias arc uboot, abrodkin + alias arm uboot, aaribaud alias at91 uboot, abiessmann alias davinci ti -- 1.9.1

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[U-Boot] [PATCH v4 0/9] Add support for hi6220 SoC and HiKey 96boards CE board.
by Peter Griffin 09 Sep '15

09 Sep '15

Hi Albert / Tom, This series adds support for the first 96boards consumer edition HiKey board. More information can be found about this board at the following link https://www.96boards.org/products/hikey/. This initial port adds support for: - 1) Serial 2) eMMC and sd card 3) USB 4) GPIO It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable. Some instructions on exactly how to compile everything (l-loader, with Arm Trusted Firmware, which then loads u-boot) is documented in the README found in the board/hisilicon/hikey directory. A basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf A rather pleasant side effect of rebasing to v2015.07-rc2 is that the two main bugs with the v1 series (that I new about at least) are resolved. DHCP now works correctly, and USB mass storage devices are also enumerated). The plan is once basic support is merged to u-boot, and upstream Linux kernel has DT which supports GPIO, UART and MMC, we can migrate this u-boot port over to using DT for configuration. Changes since v3: - Update to use config_distro_bootcmd.h (Sjoerd) - Remove CONFIG_BOOTDELAY (Sjoerd) Changes since v2: - errno.h should go above malloc.h (Simon) - drop #ifdef CONFIG_DM_GPIO and add TODO (Simon) - remove gd->flags = 0; (Simon) - Remove icache_enable() (Simon / Rob) - Added a pinmux driver for hi6220 (Simon) - Added a pmic driver for hi6553 (Simon) - Convert to structs for register I/O (Simon) - Remove () around simple constants (Simon) - Update default bootcmd (Rob) - user kernel_addr_r etc in default env (Rob) - Various typo's (Rob) - use board_usb_init() to configure phy/clocks (Rob) - Remove some more unnecessary CONFIG_FS* options (Rob) - Update default kernel load address (Rob) - Update default kernel cmdline (Rob) Changes since v1: - Rename vendor to hisilicon not 96boards (Rob) - Get rid of aemv8a vexpress leftover (Rob) - Remove __weak on misc_init_r (Rob) - Remove unnecessary LINUX_BOOT_PARAM_ADDR (Rob) - COUNTER_FREQUENCY in decimal to avoid comment (Rob) - Remove leftover V2M* from vexpress (Rob) - Migrate configs/hikey.h over to use config_distro_defaults.h (Rob) - Remove custom u-boot prompt (Rob) - Enable icache - Remove custom delay function, as mdelay/udelay work fine (Rob) - Update CONFIG_SYS_LOAD_ADDR to 0x80000 (Rob) - Use suggested macro for declaring gpio addresses (Marek) - Zap dead Macros (Marek) - Use calloc instead of malloc (Marek) - Reduce PHYS_RAM by 16Mb to accomodate OPTEE in latest ATF code (Peter) - Rebase on v2015.07-rc2 (Peter) - Add CONFIG_NET=y so that env callbacks work (Peter) - Add a README on how to build / flash u-boot (Simon) kind regards, Peter. Peter Griffin (9): usb: dwc2: Call board_usb_init() from usb_lowlevel_init() dm: gpio: hi6220: Add a hi6220 GPIO driver model driver. ARM: hi6220: Add register and bitfield definition header files. hisilicon: hi6220: Add a hi6220 pinmux driver. pmic: pmic_hi6553: Add a driver for the hi6553 pmic found on hikey board. mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller. ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board. ARM64: hikey: Add a README for this board. hikey: Add hikey-u-boot.mak arch/arm/Kconfig | 8 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/hisilicon/Makefile | 9 + arch/arm/cpu/armv8/hisilicon/pinmux.c | 184 +++++++++ arch/arm/include/asm/arch-hi6220/dwmmc.h | 8 + arch/arm/include/asm/arch-hi6220/gpio.h | 29 ++ arch/arm/include/asm/arch-hi6220/hi6220.h | 387 +++++++++++++++++++ .../include/asm/arch-hi6220/hi6220_regs_alwayson.h | 420 +++++++++++++++++++++ arch/arm/include/asm/arch-hi6220/periph.h | 30 ++ arch/arm/include/asm/arch-hi6220/pinmux.h | 83 ++++ board/hisilicon/hikey/Kconfig | 15 + board/hisilicon/hikey/Makefile | 8 + board/hisilicon/hikey/README | 160 ++++++++ board/hisilicon/hikey/hikey.c | 356 +++++++++++++++++ configs/hikey_defconfig | 5 + drivers/gpio/Makefile | 2 + drivers/gpio/hi6220_gpio.c | 95 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/hi6220_dw_mmc.c | 56 +++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_hi6553.c | 133 +++++++ drivers/usb/host/dwc2.c | 4 + hikey-u-boot.mak | 33 ++ include/configs/hikey.h | 159 ++++++++ include/power/hi6553_pmic.h | 79 ++++ 25 files changed, 2266 insertions(+) create mode 100644 arch/arm/cpu/armv8/hisilicon/Makefile create mode 100644 arch/arm/cpu/armv8/hisilicon/pinmux.c create mode 100644 arch/arm/include/asm/arch-hi6220/dwmmc.h create mode 100644 arch/arm/include/asm/arch-hi6220/gpio.h create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220.h create mode 100644 arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h create mode 100644 arch/arm/include/asm/arch-hi6220/periph.h create mode 100644 arch/arm/include/asm/arch-hi6220/pinmux.h create mode 100644 board/hisilicon/hikey/Kconfig create mode 100644 board/hisilicon/hikey/Makefile create mode 100644 board/hisilicon/hikey/README create mode 100644 board/hisilicon/hikey/hikey.c create mode 100644 configs/hikey_defconfig create mode 100644 drivers/gpio/hi6220_gpio.c create mode 100644 drivers/mmc/hi6220_dw_mmc.c create mode 100644 drivers/power/pmic/pmic_hi6553.c create mode 100644 hikey-u-boot.mak create mode 100644 include/configs/hikey.h create mode 100644 include/power/hi6553_pmic.h -- 1.9.1

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[U-Boot] [PATCH 1/1] spi: tegra20: Add support for mode selection
by Mirza Krak 04 Sep '15

04 Sep '15

From: Mirza Krak <mirza.krak(a)hostmobility.com> Respect the mode passed in claim_bus call. Signed-off-by: Mirza Krak <mirza.krak(a)hostmobility.com> --- drivers/spi/tegra20_slink.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index f6fb89b393f0..271e2adbb2e1 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -36,6 +36,11 @@ DECLARE_GLOBAL_DATA_PTR; #define SLINK_CMD_ENB (1 << 31) #define SLINK_CMD_GO (1 << 30) #define SLINK_CMD_M_S (1 << 28) +#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24) +#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24) +#define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24) +#define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24) +#define SLINK_CMD_IDLE_SCLK_MASK (3 << 24) #define SLINK_CMD_CK_SDA (1 << 21) #define SLINK_CMD_CS_POL (1 << 13) #define SLINK_CMD_CS_VAL (1 << 12) @@ -146,6 +151,7 @@ static int tegra30_spi_claim_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct tegra30_spi_priv *priv = dev_get_priv(bus); struct spi_regs *regs = priv->regs; + unsigned int mode = priv->mode; u32 reg; /* Change SPI clock to correct frequency, PLLP_OUT0 source */ @@ -161,6 +167,17 @@ static int tegra30_spi_claim_bus(struct udevice *dev) /* Set master mode and sw controlled CS */ reg = readl(&regs->command); reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT; + + /* Set CPOL and CPHA */ + reg &= ~SLINK_CMD_IDLE_SCLK_MASK & ~SLINK_CMD_CK_SDA; + if (mode & SPI_CPHA) + reg |= SLINK_CMD_CK_SDA; + + if (mode & SPI_CPOL) + reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH; + else + reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW; + writel(reg, &regs->command); debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command)); -- 2.1.0

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[U-Boot] [PATCH 1/2][V2] pci: Add function to find an extended capability
by Minghuan Lian 02 Sep '15

02 Sep '15

PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- Change log: v2-v1: 1. add a descriptor of pci_find_next_ext_capability 2. fix a typo drivers/pci/pci.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/pci.h | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 157491c..df50b48 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -526,3 +526,56 @@ int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) } return 0; } + +/** + * pci_find_next_ext_capability - Find an extended capability + * + * Returns the address of the next matching extended capability structure + * within the device's PCI configuration space or 0 if the device does + * not support it. Some capabilities can occur several times, e.g., the + * vendor-specific capability, and this provides a way to find them all. + */ +int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev, + int start, int cap) +{ + u32 header; + int ttl, pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (start) + pos = start; + + pci_hose_read_config_dword(hose, dev, pos, &header); + if (header == 0xffffffff || header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap && pos != start) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + pci_hose_read_config_dword(hose, dev, pos, &header); + if (header == 0xffffffff || header == 0) + break; + } + + return 0; +} + +/** + * pci_hose_find_ext_capability - Find an extended capability + * + * Returns the address of the requested extended capability structure + * within the device's PCI configuration space or 0 if the device does + * not support it. + */ +int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev, + int cap) +{ + return pci_find_next_ext_capability(hose, dev, 0, cap); +} diff --git a/include/pci.h b/include/pci.h index 07b1e9a..2f88714 100644 --- a/include/pci.h +++ b/include/pci.h @@ -11,6 +11,9 @@ #ifndef _PCI_H #define _PCI_H +#define PCI_CFG_SPACE_SIZE 256 +#define PCI_CFG_SPACE_EXP_SIZE 4096 + /* * Under PCI, each device has 256 bytes of configuration address space, * of which the first 64 bytes are standardized as follows: @@ -413,6 +416,39 @@ #define PCI_FIND_CAP_TTL 0x48 #define CAP_START_POS 0x40 +/* Extended Capabilities (PCI-X 2.0 and Express) */ +#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) +#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) +#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) + +#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ +#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ +#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ +#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ +#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ +#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ +#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ +#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ +#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ +#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ +#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ +#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ +#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ +#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ +#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ +#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ +#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ +#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ +#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ +#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ +#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ +#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ +#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ +#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ +#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ +#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ +#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ + /* Include the ID list */ #include <pci_ids.h> @@ -674,6 +710,11 @@ extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap); +int pci_find_next_ext_capability(struct pci_controller *hose, + pci_dev_t dev, int start, int cap); +int pci_hose_find_ext_capability(struct pci_controller *hose, + pci_dev_t dev, int cap); + #ifdef CONFIG_PCI_FIXUP_DEV extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, unsigned short vendor, -- 1.9.1

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[U-Boot] [PATCH] pci/layerscape: Setup mmu-masters property for the PCIe
by Varun Sethi 02 Sep '15

02 Sep '15

Setup mmu-masters property for the PCIe controllers. This would be used by the Linux SMMU driver, while setting up stream ID table mappings for the PCIe devices. Signed-off-by: Varun Sethi <Varun.Sethi(a)freescale.com> --- drivers/pci/pcie_layerscape.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 95cfe8c..2f24a6a 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -689,6 +689,7 @@ void fdt_fixup_smmu_pcie(void *blob) { int count; u32 stream_ids[MAX_STREAM_IDS]; + u32 ctlr_streamid = 0x300; #ifdef CONFIG_PCIE1 /* PEX1 stream ID fixup */ @@ -696,6 +697,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000", + &ctlr_streamid, 1); #endif #ifdef CONFIG_PCIE2 @@ -704,6 +707,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000", + &ctlr_streamid, 1); #endif #ifdef CONFIG_PCIE3 @@ -712,6 +717,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000", + &ctlr_streamid, 1); #endif #ifdef CONFIG_PCIE4 @@ -720,6 +727,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000", + &ctlr_streamid, 1); #endif } #endif -- 1.7.9.5

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[U-Boot] [PATCH 4/4][v8] SECURE_BOOT: Disable IE Key feature for RAMBOOT
by Aneesh Bansal 02 Sep '15

02 Sep '15

ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v8: New Patch added in patchset arch/arm/include/asm/arch-ls102xa/config.h | 14 -------------- arch/arm/include/asm/fsl_secure_boot.h | 22 ++++++++++++++++++++++ arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++++-- 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index c55cdef..bcaf7bf 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -103,20 +103,6 @@ #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION -#define CONFIG_FSL_ISBC_KEY_EXT - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM -#define CONFIG_RSA -#define CONFIG_RSA_FREESCALE_EXP -#ifndef CONFIG_FSL_CAAM -#define CONFIG_FSL_CAAM -#endif -#endif #define DCU_LAYER_MAX_NUM 16 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index f097c81..f2d4c3c 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,6 +8,28 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_DM +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif + +#define CONFIG_KEY_REVOCATION +#ifndef CONFIG_SYS_RAMBOOT +/* The key used for verification of next level images + * is picked up from an Extension Table which has + * been verified by the ISBC (Internal Secure boot Code) + * in boot ROM of the SoC. + * The feature is only applicable in case of NOR boot and is + * not applicable in case of RAMBOOT (NAND, SD, SPI). + */ +#define CONFIG_FSL_ISBC_KEY_EXT +#endif + #ifndef CONFIG_FIT_SIGNATURE #define CONFIG_EXTRA_ENV \ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 6e55716..0985865 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -63,11 +63,13 @@ #define CONFIG_FSL_TRUST_ARCH_v1 #endif -#if defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) /* The key used for verification of next level images * is picked up from an Extension Table which has * been verified by the ISBC (Internal Secure boot Code) - * in boot ROM of the SoC + * in boot ROM of the SoC. + * The feature is only applicable in case of NOR boot and is + * not applicable in case of RAMBOOT (NAND, SD, SPI). */ #define CONFIG_FSL_ISBC_KEY_EXT #endif -- 1.8.1.4

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[U-Boot] [PATCH] armv8/ls2085a_simu: enable eSDHC
by Yangbo Lu 02 Sep '15

02 Sep '15

Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> --- include/configs/ls2085a_simu.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h index d0d2eed..bd15b3d 100644 --- a/include/configs/ls2085a_simu.h +++ b/include/configs/ls2085a_simu.h @@ -127,6 +127,17 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +/* MMC */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL -- 2.1.0.27.g96db324

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[U-Boot] [RESEND PATCH 1/1] armv8: Add framework for CCN-504 interconnect configuration
by Bhupesh Sharma 02 Sep '15

02 Sep '15

This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports. LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> --- arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 72 +++++++++++++++++++++++--- arch/arm/include/asm/arch-fsl-lsch3/config.h | 11 ++++ arch/arm/lib/Makefile | 1 + arch/arm/lib/ccn504.S | 61 ++++++++++++++++++++++ 4 files changed, 138 insertions(+), 7 deletions(-) create mode 100644 arch/arm/lib/ccn504.S diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 018c617..6b19d36 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -16,13 +16,71 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ /* Add fully-coherent masters to DVM domain */ - ldr x1, =CCI_MN_BASE - ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST] - str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] -1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] - mvn x0, x3 - tst x0, x3 /* Wait for domain addition to complete */ - b.ne 1b + ldr x0, =CCI_MN_BASE + ldr x1, =CCI_MN_RNF_NODEID_LIST + ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET + bl ccn504_add_masters_to_dvm + + /* Set all RN-I ports to QoS of 15 */ + ldr x0, =CCI_S0_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index ca8d38c..c47950c 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -132,6 +132,17 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) +#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) +#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) +#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) +#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) +#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) + +#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) +#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) +#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) + /* Device Configuration */ #define DCFG_BASE 0x01e00000 #define DCFG_PORSR1 0x000 diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 31a5c8d..51497cc 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -42,6 +42,7 @@ obj-y += stack.o ifdef CONFIG_CPU_V7M obj-y += interrupts_m.o else ifdef CONFIG_ARM64 +obj-y += ccn504.o obj-y += gic_64.o obj-y += interrupts_64.o else diff --git a/arch/arm/lib/ccn504.S b/arch/arm/lib/ccn504.S new file mode 100644 index 0000000..7570c7b --- /dev/null +++ b/arch/arm/lib/ccn504.S @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Extracted from gic_64.S + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> + +/************************************************************************* + * + * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST, + * CCI_MN_DVM_DOMAIN_CTL_SET); + * + * Add fully-coherent masters to DVM domain + * + *************************************************************************/ +ENTRY(ccn504_add_masters_to_dvm) + /* + * x0: CCI_MN_BASE + * x1: CCI_MN_RNF_NODEID_LIST + * x2: CCI_MN_DVM_DOMAIN_CTL_SET + */ + + /* Add fully-coherent masters to DVM domain */ + ldr x9, [x0, x1] + str x9, [x0, x2] +1: ldr x10, [x0, x2] + mvn x11, x10 + tst x11, x10 /* Wait for domain addition to complete */ + b.ne 1b + + ret +ENDPROC(ccn504_add_masters_to_dvm) + +/************************************************************************* + * + * void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value); + * + * Initialize QoS settings for AR/AW override. + * Right now, this function sets the same QoS value for all RN-I ports + * + *************************************************************************/ +ENTRY(ccn504_set_qos) + /* + * x0: CCI_Sx_QOS_CONTROL_BASE + * x1: QoS Value + */ + + /* Set all RN-I ports to QoS value denoted by x1 */ + ldr x9, [x0] + mov x10, x1 + orr x9, x9, x10 + str x9, [x0] + + ret +ENDPROC(ccn504_set_qos) + -- 1.7.9.5

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