April 2015 - U-Boot

[U-Boot] [PATCH v2 0/11] dm: net: Conversion patches for sunxi driver model Ethernet
by Simon Glass 09 Apr '15

09 Apr '15

This series enables driver model Ethernet for the pcDuino3, converting the designware Ethernet MAC in the process. It also moves all sunxi board to use Kconfig for their basic Ethernet settings. This series is based on u-boot-dm/next and requires Joe's patch here: http://patchwork.ozlabs.org/patch/458111/ It is available at u-boot-dm in branch net-working. Changes in v2: - Add Ethernet for Orangepi, galileo - Add Ethernet for Orangepi_mini, Wits_Pro_A20_DKT, Mele_I7 - Drop bugfix patches that were incorporated in the Ethernet dm conversion - Drop the CONFIG_BOOTP_VCI_STRING patch - Rebase on dm/next - Remove unwanted printf() - Use the new recv() method and the free_pkt() method Simon Glass (11): sunxi: Replace the pcDuino3 config with FDT version Kconfig: Move CONFIG_DESIGNWARE_ETH to Kconfig dts: sunxi: Bring in Ethernet device tree bindings dm: core: Support allocating driver-private data for DMA dm: net: Use existing Ethernet init for driver model Avoid calling print_eths() with driver model dm: net: Adjust PHY interface to work with CONFIG_DM_ETH dm: net: Tidy up designware driver ready for driver model dm: net: Adjust designware driver to support driver model dm: sunxi: Support driver model for Ethernet dm: sunxi: Use driver model for Ethernet on Linksprite pcDuino3 arch/arm/cpu/arm926ejs/spear/cpu.c | 2 +- arch/arm/cpu/armv7/socfpga/misc.c | 2 +- board/bf609-ezkit/bf609-ezkit.c | 2 +- board/spear/spear300/spear300.c | 2 +- board/spear/spear310/spear310.c | 2 +- board/spear/spear320/spear320.c | 2 +- board/spear/spear600/spear600.c | 2 +- board/st/stv0991/stv0991.c | 2 +- board/sunxi/gmac.c | 10 +- common/cmd_bdinfo.c | 2 +- common/miiphyutil.c | 1 + configs/A20-OLinuXino-Lime2_defconfig | 3 + configs/A20-OLinuXino-Lime_defconfig | 3 + configs/A20-OLinuXino_MICRO_defconfig | 3 + configs/Bananapi_defconfig | 3 + configs/Bananapro_defconfig | 3 + configs/CSQ_CS908_defconfig | 3 + configs/Colombus_defconfig | 3 + configs/Cubieboard2_defconfig | 3 + configs/Cubietruck_defconfig | 3 + configs/Hummingbird_A31_defconfig | 3 + configs/Linksprite_pcDuino3_Nano_defconfig | 3 + configs/Linksprite_pcDuino3_defconfig | 11 + configs/Linksprite_pcDuino3_fdt_defconfig | 15 -- configs/Mele_I7_defconfig | 3 + configs/Mele_M3_defconfig | 3 + configs/Mele_M5_defconfig | 3 + configs/Mele_M9_defconfig | 3 + configs/Orangepi_defconfig | 3 + configs/Orangepi_mini_defconfig | 3 + configs/Wits_Pro_A20_DKT_defconfig | 3 + configs/axs101_defconfig | 5 +- configs/axs103_defconfig | 3 + configs/bf609-ezkit_defconfig | 3 + configs/galileo_defconfig | 3 + configs/i12-tvbox_defconfig | 3 + configs/socfpga_cyclone5_defconfig | 3 + configs/socfpga_socrates_defconfig | 3 + configs/spear300_defconfig | 3 + configs/spear300_nand_defconfig | 3 + configs/spear300_usbtty_defconfig | 3 + configs/spear300_usbtty_nand_defconfig | 3 + configs/spear310_defconfig | 3 + configs/spear310_nand_defconfig | 3 + configs/spear310_pnor_defconfig | 3 + configs/spear310_usbtty_defconfig | 3 + configs/spear310_usbtty_nand_defconfig | 3 + configs/spear310_usbtty_pnor_defconfig | 3 + configs/spear320_defconfig | 3 + configs/spear320_nand_defconfig | 3 + configs/spear320_pnor_defconfig | 3 + configs/spear320_usbtty_defconfig | 3 + configs/spear320_usbtty_nand_defconfig | 3 + configs/spear320_usbtty_pnor_defconfig | 3 + configs/spear600_defconfig | 3 + configs/spear600_nand_defconfig | 3 + configs/spear600_usbtty_defconfig | 3 + configs/spear600_usbtty_nand_defconfig | 3 + configs/stv0991_defconfig | 3 + configs/tb100_defconfig | 3 + configs/x600_defconfig | 3 + .../net/allwinner,sun4i-emac.txt | 19 ++ .../net/allwinner,sun4i-mdio.txt | 27 +++ .../net/allwinner,sun7i-a20-gmac.txt | 27 +++ doc/device-tree-bindings/net/ethernet.txt | 25 +++ doc/device-tree-bindings/net/stmmac.txt | 63 ++++++ drivers/core/device.c | 11 +- drivers/net/Kconfig | 7 + drivers/net/Makefile | 2 +- drivers/net/designware.c | 250 +++++++++++++++++---- drivers/net/designware.h | 3 +- drivers/net/phy/phy.c | 22 ++ include/configs/axs101.h | 1 - include/configs/bf609-ezkit.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/spear-common.h | 1 - include/configs/stv0991.h | 1 - include/configs/sunxi-common.h | 1 - include/configs/tb100.h | 1 - include/configs/x600.h | 1 - include/dm/device.h | 3 + include/net.h | 2 + include/phy.h | 23 +- net/eth.c | 78 ++++--- 84 files changed, 647 insertions(+), 124 deletions(-) delete mode 100644 configs/Linksprite_pcDuino3_fdt_defconfig create mode 100644 doc/device-tree-bindings/net/allwinner,sun4i-emac.txt create mode 100644 doc/device-tree-bindings/net/allwinner,sun4i-mdio.txt create mode 100644 doc/device-tree-bindings/net/allwinner,sun7i-a20-gmac.txt create mode 100644 doc/device-tree-bindings/net/ethernet.txt create mode 100644 doc/device-tree-bindings/net/stmmac.txt -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH] Kconfig: Move CONFIG_BOOTSTAGE to Kconfig
by Simon Glass 09 Apr '15

09 Apr '15

Move CONFIG_BOOT_STAGE and its associated options to Kconfig. Adjust existing users and code. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- README | 49 -------------------- arch/x86/Kconfig | 9 ++++ arch/x86/cpu/cpu.c | 2 +- common/Kconfig | 106 +++++++++++++++++++++++++++++++++++++++++++ common/cmd_bootstage.c | 7 +-- configs/sandbox_defconfig | 1 + include/bootstage.h | 2 +- include/configs/sandbox.h | 1 - include/configs/x86-common.h | 3 -- 9 files changed, 119 insertions(+), 61 deletions(-) diff --git a/README b/README index febefb5..4848e13 100644 --- a/README +++ b/README @@ -3228,55 +3228,6 @@ CBFS (Coreboot Filesystem) support example, some LED's) on your board. At the moment, the following checkpoints are implemented: -- Detailed boot stage timing - CONFIG_BOOTSTAGE - Define this option to get detailed timing of each stage - of the boot process. - - CONFIG_BOOTSTAGE_USER_COUNT - This is the number of available user bootstage records. - Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...) - a new ID will be allocated from this stash. If you exceed - the limit, recording will stop. - - CONFIG_BOOTSTAGE_REPORT - Define this to print a report before boot, similar to this: - - Timer summary in microseconds: - Mark Elapsed Stage - 0 0 reset - 3,575,678 3,575,678 board_init_f start - 3,575,695 17 arch_cpu_init A9 - 3,575,777 82 arch_cpu_init done - 3,659,598 83,821 board_init_r start - 3,910,375 250,777 main_loop - 29,916,167 26,005,792 bootm_start - 30,361,327 445,160 start_kernel - - CONFIG_CMD_BOOTSTAGE - Add a 'bootstage' command which supports printing a report - and un/stashing of bootstage data. - - CONFIG_BOOTSTAGE_FDT - Stash the bootstage information in the FDT. A root 'bootstage' - node is created with each bootstage id as a child. Each child - has a 'name' property and either 'mark' containing the - mark time in microsecond, or 'accum' containing the - accumulated time for that bootstage id in microseconds. - For example: - - bootstage { - 154 { - name = "board_init_f"; - mark = <3575678>; - }; - 170 { - name = "lcd"; - accum = <33482>; - }; - }; - - Code in the Linux kernel can find this in /proc/devicetree. Legacy uImage format: diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 35d24e4..78a0532 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -455,4 +455,13 @@ config PCIE_ECAM_BASE assigned to PCI devices - i.e. the memory and prefetch regions, as passed to pci_set_region(). +config BOOTSTAGE + default y + +config BOOTSTAGE_REPORT + default y + +config CMD_BOOTSTAGE + default y + endmenu diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index ed7905c..a9ca50b 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -163,7 +163,7 @@ void setup_gdt(gd_t *id, u64 *gdt_addr) int __weak x86_cleanup_before_linux(void) { #ifdef CONFIG_BOOTSTAGE_STASH - bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH, + bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, CONFIG_BOOTSTAGE_STASH_SIZE); #endif diff --git a/common/Kconfig b/common/Kconfig index f82bc88..7a44272 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -335,4 +335,110 @@ config CMD_SETGETDCR endmenu +menu "Boot timing" + +config BOOTSTAGE + bool "Boot timing and reporting" + help + Enable recording of boot time while booting. To use it, insert + calls to bootstage_mark() with a suitable BOOTSTAGE_ID from + bootstage.h. Only a single entry is recorded for each ID. You can + give the entry a name with bootstage_mark_name(). You can also + record elapsed time in a particular stage using bootstage_start() + before starting and bootstage_accum() when finished. Bootstage will + add up all the accumated time and report it. + + Normally, IDs are defined in bootstage.h but a small number of + additional 'user' IDs can be used but passing BOOTSTAGE_ID_ALLOC + as the ID. + + Calls to show_boot_progress() wil also result in log entries but + these will not have names. + +config BOOTSTAGE_REPORT + bool "Display a detailed boot timing report before booting the OS" + depends on BOOTSTAGE + help + Enable output of a boot time report just before the OS is booted. + This shows how long it took U-Boot to go through each stage of the + boot process. The report looks something like this: + + Timer summary in microseconds: + Mark Elapsed Stage + 0 0 reset + 3,575,678 3,575,678 board_init_f start + 3,575,695 17 arch_cpu_init A9 + 3,575,777 82 arch_cpu_init done + 3,659,598 83,821 board_init_r start + 3,910,375 250,777 main_loop + 29,916,167 26,005,792 bootm_start + 30,361,327 445,160 start_kernel + +config BOOTSTAGE_USER_COUNT + hex "Number of boot ID numbers available for user use" + default 20 + help + This is the number of available user bootstage records. + Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...) + a new ID will be allocated from this stash. If you exceed + the limit, recording will stop. + +config CMD_BOOTSTAGE + bool "Enable the 'bootstage' command" + depends on BOOTSTAGE + help + Add a 'bootstage' command which supports printing a report + and un/stashing of bootstage data. + +config BOOTSTAGE_FDT + bool "Store boot timing information in the OS device tree" + depends on BOOTSTAGE + help + Stash the bootstage information in the FDT. A root 'bootstage' + node is created with each bootstage id as a child. Each child + has a 'name' property and either 'mark' containing the + mark time in microsecond, or 'accum' containing the + accumulated time for that bootstage id in microseconds. + For example: + + bootstage { + 154 { + name = "board_init_f"; + mark = <3575678>; + }; + 170 { + name = "lcd"; + accum = <33482>; + }; + }; + + Code in the Linux kernel can find this in /proc/devicetree. + +config BOOTSTAGE_STASH + bool "Stash the boot timing information in memory before booting OS" + depends on BOOTSTAGE + help + Some OSes do not support device tree. Bootstage can instead write + the boot timing information in a binary format at a given address. + This happens through a call to bootstage_stash(), typically in + the CPU's cleanup_before_linux() function. You can use the + 'bootstage stash' and 'bootstage unstash' commands to do this on + the command line. + +config BOOTSTAGE_STASH_ADDR + hex "Address to stash boot timing information" + default 0 + help + Provide an address which will not be overwritten by the OS when it + starts, so that it can read this information when ready. + +config BOOTSTAGE_STASH_SIZE + hex "Size of boot timing stash region" + default 4096 + help + This should be large enough to hold the bootstage stash. A value of + 4096 (4KiB) is normally plenty. + +endmenu + endmenu diff --git a/common/cmd_bootstage.c b/common/cmd_bootstage.c index 106894a..788ab16 100644 --- a/common/cmd_bootstage.c +++ b/common/cmd_bootstage.c @@ -6,11 +6,6 @@ #include <common.h> -#ifndef CONFIG_BOOTSTAGE_STASH -#define CONFIG_BOOTSTAGE_STASH -1UL -#define CONFIG_BOOTSTAGE_STASH_SIZE -1 -#endif - static int do_bootstage_report(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -24,7 +19,7 @@ static int get_base_size(int argc, char * const argv[], ulong *basep, { char *endp; - *basep = CONFIG_BOOTSTAGE_STASH; + *basep = CONFIG_BOOTSTAGE_STASH_ADDR; *sizep = CONFIG_BOOTSTAGE_STASH_SIZE; if (argc < 2) return 0; diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 70f5b86..3255003 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -12,3 +12,4 @@ CONFIG_DM_CROS_EC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_KEYB=y CONFIG_CMD_CROS_EC=y +CONFIG_BOOTSTAGE=y diff --git a/include/bootstage.h b/include/bootstage.h index 0276cb3..be44014 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -11,7 +11,7 @@ #ifndef _BOOTSTAGE_H #define _BOOTSTAGE_H -/* The number of boot stage records available for the user */ +/* Define this for host tools */ #ifndef CONFIG_BOOTSTAGE_USER_COUNT #define CONFIG_BOOTSTAGE_USER_COUNT 20 #endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index febbfb6..2dd198d 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_BOOTSTAGE #define CONFIG_BOOTSTAGE_REPORT #define CONFIG_SYS_STDIO_DEREGISTER diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 994874c..75108a9 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -238,9 +238,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTSTAGE -#define CONFIG_CMD_BOOTSTAGE - #define CONFIG_CMD_USB #define CONFIG_EXTRA_ENV_SETTINGS \ -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] Hi, Everyone. How to using Ti-edma Driver in u-boot
by kidd 09 Apr '15

09 Apr '15

I add the Ti-edmaDriver reference http://lists.denx.de/pipermail/u-boot/2014-October/191345.htmlarch/arm/incl… drivers/dma/ti-edma3.c My uboot Ver : U-Boot 2010.06My arch: DM8148 I want to know how to use ti-edma3.cdriverPlease give me a sample .Thanks.

1 0

[U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
by Gabriel Huau 09 Apr '15

09 Apr '15

Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau <contact(a)huau-gabriel.fr> --- arch/x86/cpu/baytrail/Makefile | 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++++++++++++++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++++++++++++++++++++++++++ arch/x86/include/asm/arch-baytrail/iomap.h | 73 ++++++ arch/x86/include/asm/arch-baytrail/irq.h | 119 +++++++++ arch/x86/include/asm/arch-baytrail/irqroute.h | 67 +++++ arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++++++++++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++++++++++++++++++ board/intel/minnowmax/minnowmax.c | 212 +++++++++++++++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile index 8914e8b..c20a616 100644 --- a/arch/x86/cpu/baytrail/Makefile +++ b/arch/x86/cpu/baytrail/Makefile @@ -8,3 +8,4 @@ obj-y += early_uart.o obj-y += fsp_configs.o obj-y += pci.o obj-y += valleyview.o +obj-y += gpio.o diff --git a/arch/x86/cpu/baytrail/gpio.c b/arch/x86/cpu/baytrail/gpio.c new file mode 100644 index 0000000..0ad41cc --- /dev/null +++ b/arch/x86/cpu/baytrail/gpio.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <pci.h> +#include <asm/arch/gpio.h> +#include <asm/arch/irqroute.h> +#include <asm/arch/pmc.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/pci.h> + +/* GPIO-to-Pad LUTs */ +static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = { + 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ + 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ + 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ + 2, 5, 9 /* [24:26] */ +}; + +static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = { + 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ + 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */ + 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */ + 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */ + 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */ + 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */ + 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */ + 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */ + 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */ + 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */ + 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */ + 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */ + 106, 87, 91, 104, 97, 100 /* [96:101] */ +}; + +static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = { + 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */ + 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */ + 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */ + 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */ + 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */ + 52, 53, 59, 40 /* [40:43] */ +}; + +/* GPIO bank descriptions */ +static const struct gpio_bank gpncore_bank = { + .gpio_count = GPNCORE_COUNT, + .gpio_to_pad = gpncore_gpio_to_pad, + .legacy_base = GP_LEGACY_BASE_NONE, + .pad_base = GPNCORE_PAD_BASE, + .has_wake_en = 0, + .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END, +}; + +static const struct gpio_bank gpscore_bank = { + .gpio_count = GPSCORE_COUNT, + .gpio_to_pad = gpscore_gpio_to_pad, + .legacy_base = GPSCORE_LEGACY_BASE, + .pad_base = GPSCORE_PAD_BASE, + .has_wake_en = 0, + .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END, +}; + +static const struct gpio_bank gpssus_bank = { + .gpio_count = GPSSUS_COUNT, + .gpio_to_pad = gpssus_gpio_to_pad, + .legacy_base = GPSSUS_LEGACY_BASE, + .pad_base = GPSSUS_PAD_BASE, + .has_wake_en = 1, + .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END, +}; + +static void setup_gpios(const struct byt_gpio_map *gpios, + const struct gpio_bank *bank) +{ + const struct byt_gpio_map *config; + int gpio = 0; + u32 reg, pad_conf0; + u8 set, bit; + + u32 use_sel[4] = {0}; + u32 io_sel[4] = {0}; + u32 gp_lvl[4] = {0}; + u32 tpe[4] = {0}; + u32 tne[4] = {0}; + u32 wake_en[4] = {0}; + + if (!gpios) + return; + + for (config = gpios; config->pad_conf0 != GPIO_LIST_END; + config++, gpio++) { + if (gpio > bank->gpio_count) + break; + + set = gpio >> 5; + bit = gpio % 32; + + if (bank->legacy_base != GP_LEGACY_BASE_NONE) { + /* Legacy IO configuration */ + use_sel[set] |= config->use_sel << bit; + io_sel[set] |= config->io_sel << bit; + gp_lvl[set] |= config->gp_lvl << bit; + tpe[set] |= config->tpe << bit; + tne[set] |= config->tne << bit; + + /* Some banks do not have wake_en ability */ + if (bank->has_wake_en) + wake_en[set] |= config->wake_en << bit; + } + + /* Pad configuration registers */ + reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio]; + + /* Add correct func to GPIO pad config */ + pad_conf0 = config->pad_conf0; + if (config->is_gpio) { + if (gpio >= bank->gpio_f1_range_start && + gpio <= bank->gpio_f1_range_end) + pad_conf0 |= PAD_FUNC1; + else + pad_conf0 |= PAD_FUNC0; + } + + writel(reg + PAD_CONF0_REG, pad_conf0); + writel(reg + PAD_CONF1_REG, config->pad_conf1); + writel(reg + PAD_VAL_REG, config->pad_val); + } + + if (bank->legacy_base != GP_LEGACY_BASE_NONE) + for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) { + reg = bank->legacy_base + 0x20 * set; + + outl(use_sel[set], reg + LEGACY_USE_SEL_REG); + outl(io_sel[set], reg + LEGACY_IO_SEL_REG); + outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG); + outl(tpe[set], reg + LEGACY_TPE_REG); + outl(tne[set], reg + LEGACY_TNE_REG); + + /* TS registers are WOC */ + outl(0, reg + LEGACY_TS_REG); + + if (bank->has_wake_en) + outl(wake_en[set], reg + LEGACY_WAKE_EN_REG); + } +} + +static void setup_gpio_route(const struct byt_gpio_map *sus, + const struct byt_gpio_map *core) +{ + uint32_t route_reg = 0; + int i; + + for (i = 0; i < 8; i++) { + /* SMI takes precedence and wake_en implies SCI. */ + if (sus[i].smi) + route_reg |= ROUTE_SMI << (2 * i); + else if (sus[i].sci) + route_reg |= ROUTE_SCI << (2 * i); + + if (core[i].smi) + route_reg |= ROUTE_SMI << (2 * (i + 8)); + else if (core[i].sci) + route_reg |= ROUTE_SCI << (2 * (i + 8)); + } +} + +static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], + const struct gpio_bank *bank) +{ + u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET; + u32 val; + int i; + + /* Write all four DIRQ registers */ + for (i = 0; i < 4; ++i) { + val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | + dirq[i * 4 + 1] << 8 | dirq[i * 4]; + writel(reg + i * 4, val); + } +} + +void setup_soc_gpios(struct byt_gpio_config *config) +{ + if (config) { + setup_gpios(config->ncore, &gpncore_bank); + setup_gpios(config->score, &gpscore_bank); + setup_gpios(config->ssus, &gpssus_bank); + setup_gpio_route(config->ssus, config->score); + + if (config->core_dirq) + setup_dirqs(*config->core_dirq, &gpscore_bank); + + if (config->sus_dirq) + setup_dirqs(*config->sus_dirq, &gpssus_bank); + } +} diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..40b0ffa 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -7,7 +7,371 @@ #ifndef _X86_ARCH_GPIO_H_ #define _X86_ARCH_GPIO_H_ +#include <common.h> +#include <asm/arch-baytrail/iomap.h> +#include <asm/io.h> + /* Where in config space is the register that points to the GPIO registers? */ #define PCI_CFG_GPIOBASE 0x44 +/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ +#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) +#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) +#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) + +/* DIRQ registers start at pad base + 0x980 */ +#define PAD_BASE_DIRQ_OFFSET 0x980 + +/* Pad register offset */ +#define PAD_CONF0_REG 0x0 +#define PAD_CONF1_REG 0x4 +#define PAD_VAL_REG 0x8 + +/* Legacy IO register base */ +#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) +#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) +/* Some banks have no legacy GPIO interface */ +#define GP_LEGACY_BASE_NONE 0xFFFF + +#define LEGACY_USE_SEL_REG 0x00 +#define LEGACY_IO_SEL_REG 0x04 +#define LEGACY_GP_LVL_REG 0x08 +#define LEGACY_TPE_REG 0x0C +#define LEGACY_TNE_REG 0x10 +#define LEGACY_TS_REG 0x14 +#define LEGACY_WAKE_EN_REG 0x18 + +/* Number of GPIOs in each bank */ +#define GPNCORE_COUNT 27 +#define GPSCORE_COUNT 102 +#define GPSSUS_COUNT 44 + +/* GPIO legacy IO register settings */ +#define GPIO_USE_MMIO 0 +#define GPIO_USE_LEGACY 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_PEDGE_DISABLE 0 +#define GPIO_PEDGE_ENABLE 1 + +#define GPIO_NEDGE_DISABLE 0 +#define GPIO_NEDGE_ENABLE 1 + +/* config0[29] - Disable second mask */ +#define PAD_MASK2_DISABLE (1 << 29) + +/* config0[27] - Direct Irq En */ +#define PAD_IRQ_EN (1 << 27) + +/* config0[26] - gd_tne */ +#define PAD_TNE_IRQ (1 << 26) + +/* config0[25] - gd_tpe */ +#define PAD_TPE_IRQ (1 << 25) + +/* config0[24] - Gd Level */ +#define PAD_LEVEL_IRQ (1 << 24) +#define PAD_EDGE_IRQ (0 << 24) + +/* config0[17] - Slow clkgate / glitch filter */ +#define PAD_SLOWGF_ENABLE (1 << 17) + +/* config0[16] - Fast clkgate / glitch filter */ +#define PAD_FASTGF_ENABLE (1 << 16) + +/* config0[15] - Hysteresis enable (inverted) */ +#define PAD_HYST_DISABLE (1 << 15) +#define PAD_HYST_ENABLE (0 << 15) + +/* config0[14:13] - Hysteresis control */ +#define PAD_HYST_CTRL_DEFAULT (2 << 13) + +/* config0[11] - Bypass Flop */ +#define PAD_FLOP_BYPASS (1 << 11) +#define PAD_FLOP_ENABLE (0 << 11) + +/* config0[10:9] - Pull str */ +#define PAD_PU_2K (0 << 9) +#define PAD_PU_10K (1 << 9) +#define PAD_PU_20K (2 << 9) +#define PAD_PU_40K (3 << 9) + +/* config0[8:7] - Pull assign */ +#define PAD_PULL_DISABLE (0 << 7) +#define PAD_PULL_UP (1 << 7) +#define PAD_PULL_DOWN (2 << 7) + +/* config0[2:0] - Func. pin mux */ +#define PAD_FUNC0 0x0 +#define PAD_FUNC1 0x1 +#define PAD_FUNC2 0x2 +#define PAD_FUNC3 0x3 +#define PAD_FUNC4 0x4 +#define PAD_FUNC5 0x5 +#define PAD_FUNC6 0x6 + +/* pad config0 power-on values - We will not often want to change these */ +#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ + PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ + PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) + +/* pad config1 reg power-on values - Shouldn't need to change this */ +#define PAD_CONFIG1_DEFAULT 0x8000 + +/* pad_val[2] - Iinenb - active low */ +#define PAD_VAL_INPUT_DISABLE (1 << 2) +#define PAD_VAL_INPUT_ENABLE (0 << 2) + +/* pad_val[1] - Ioutenb - active low */ +#define PAD_VAL_OUTPUT_DISABLE (1 << 1) +#define PAD_VAL_OUTPUT_ENABLE (0 << 1) + +/* Input / Output state should usually be mutually exclusive */ +#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) +#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) + +/* pad_val[0] - Value */ +#define PAD_VAL_HIGH (1 << 0) +#define PAD_VAL_LOW (0 << 0) + +/* pad_val reg power-on default varies by pad, and apparently can cause issues + * if not set correctly, even if the pin isn't configured as GPIO. */ +#define PAD_VAL_DEFAULT PAD_VAL_INPUT + +/* Configure GPIOs as MMIO by default */ +#define GPIO_INPUT_PU_10K(_func) \ + { .pad_conf0 = PAD_FUNC##_func | PAD_PU_10K | \ + PAD_PULL_UP | \ + PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_PD_10K \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_NOPU \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_LEGACY_NOPU \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .is_gpio = 1 } + +/* Direct / dedicated IRQ input - pass signal directly to apic */ +#define GPIO_DIRQ \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, } + + +#define GPIO_OUT_LOW \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_LOW, \ + .is_gpio = 1 } + +#define GPIO_OUT_HIGH \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_HIGH, \ + .is_gpio = 1 } + +/* Define no-pull / PU / PD configs for each functional config option */ +#define GPIO_FUNC(_func, _pudir, _str) \ + { .use_sel = GPIO_USE_MMIO, \ + .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \ + PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } + +/* Default functional configs -- no PU */ +#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 10K) +#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 10K) +#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 10K) +#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 10K) +#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 10K) +#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 10K) +#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 10K) + +/* ACPI GPIO routing. Assume everything is externally pulled and negative edge + * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ +#define GPIO_ACPI_SCI \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ + .sci = 1, \ + .wake_en = 1, } +#define GPIO_ACPI_WAKE \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ + .wake_en = 1, } +#define GPIO_ACPI_SMI \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ + .smi = 1} + +/* End marker */ +#define GPIO_LIST_END 0xffffffff + +#define GPIO_END \ + { .pad_conf0 = GPIO_LIST_END } + +/* Common default GPIO settings */ +#define GPIO_INPUT GPIO_INPUT_NOPU +#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU +#define GPIO_INPUT_PU GPIO_INPUT_PU_10K(0) +#define GPIO_INPUT_PD GPIO_INPUT_PD_10K +#define GPIO_NC GPIO_INPUT_PU_10K(0) +#define GPIO_NC1 GPIO_INPUT_PU_10K(1) +#define GPIO_DEFAULT GPIO_FUNC0 + +/* 16 DirectIRQs per supported bank */ +#define GPIO_MAX_DIRQS 16 + +/* Most pins are GPIO function 0. Some banks have a range of pins with GPIO + * function 1. Indicate first / last GPIOs with function 1. */ +#define GPIO_NONE 255 +/* All NCORE GPIOs are function 0 */ +#define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE +#define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE +/* SCORE GPIO [92:93] are function 1 */ +#define GPSCORE_GPIO_F1_RANGE_START 92 +#define GPSCORE_GPIO_F1_RANGE_END 93 +/* SSUS GPIO [11:21] are function 1 */ +#define GPSSUS_GPIO_F1_RANGE_START 11 +#define GPSSUS_GPIO_F1_RANGE_END 21 + +struct __packed byt_gpio_map { + u32 pad_conf0; + u32 pad_conf1; + u32 pad_val; + u32 use_sel:1; + u32 io_sel:1; + u32 gp_lvl:1; + u32 tpe:1; + u32 tne:1; + u32 wake_en:1; + u32 smi:1; + u32 is_gpio:1; + u32 sci:1; +}; + +struct byt_gpio_config { + const struct byt_gpio_map *ncore; + const struct byt_gpio_map *score; + const struct byt_gpio_map *ssus; + const u8 (*core_dirq)[GPIO_MAX_DIRQS]; + const u8 (*sus_dirq)[GPIO_MAX_DIRQS]; +}; + +/* Description of GPIO 'bank' ex. {ncore, score. ssus} */ +struct gpio_bank { + const int gpio_count; + const u8 *gpio_to_pad; + const int legacy_base; + const unsigned long pad_base; + const u8 has_wake_en:1; + const u8 gpio_f1_range_start; + const u8 gpio_f1_range_end; +}; + +/* Function to call to setup the GPIOs */ +void setup_soc_gpios(struct byt_gpio_config *config); + +/* Functions / defines for changing GPIOs in romstage */ +/* SCORE Pad definitions. */ +#define UART_RXD_PAD 82 +#define UART_TXD_PAD 83 +#define PCU_SMB_CLK_PAD 88 +#define PCU_SMB_DATA_PAD 90 + +static inline unsigned int score_pconf0(int pad_num) +{ + return GPSCORE_PAD_BASE + pad_num * 16; +} + +static inline unsigned int ssus_pconf0(int pad_num) +{ + return GPSSUS_PAD_BASE + pad_num * 16; +} + +static inline void score_select_func(int pad, int func) +{ + uint32_t reg; + uint32_t pconf0_addr = score_pconf0(pad); + + reg = readl(pconf0_addr); + reg &= ~0x7; + reg |= func & 0x7; + writel(pconf0_addr, reg); +} + +static inline void ssus_select_func(int pad, int func) +{ + uint32_t reg; + uint32_t pconf0_addr = ssus_pconf0(pad); + + reg = readl(pconf0_addr); + reg &= ~0x7; + reg |= func & 0x7; + writel(pconf0_addr, reg); +} + +/* These functions require that the input pad be configured as an input GPIO */ +static inline int score_get_gpio(int pad) +{ + uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG; + + return readl(val_addr) & PAD_VAL_HIGH; +} + +static inline int ssus_get_gpio(int pad) +{ + uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG; + + return readl(val_addr) & PAD_VAL_HIGH; +} + +static inline void ssus_disable_internal_pull(int pad) +{ + const uint32_t pull_mask = ~(0xf << 7); + writel(ssus_pconf0(pad), readl(ssus_pconf0(pad)) & pull_mask); +} + #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h new file mode 100644 index 0000000..9624929 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/iomap.h @@ -0,0 +1,73 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _BAYTRAIL_IOMAP_H_ +#define _BAYTRAIL_IOMAP_H_ + +/* + * Memory Mapped IO bases. + */ + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x10000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00100000 + +/* Power Management Controller */ +#define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed0c000 +#define IO_BASE_OFFSET_GPSCORE 0x0000 +#define IO_BASE_OFFSET_GPNCORE 0x1000 +#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_SIZE 0x4000 + +/* Intel Legacy Block */ +#define ILB_BASE_ADDRESS 0xfed08000 +#define ILB_BASE_SIZE 0x400 + +/* SPI Bus */ +#define SPI_BASE_ADDRESS 0xfed01000 +#define SPI_BASE_SIZE 0x400 + +/* MODPHY */ +#define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_SIZE 0x100000 + +/* Power Management Unit */ +#define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_SIZE 0x800 + +/* Root Complex Base Address */ +#define RCBA_BASE_ADDRESS 0xfed1c000 +#define RCBA_BASE_SIZE 0x400 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* Temporary Base Address */ +#define TEMP_BASE_ADDRESS 0xfd000000 + +/* + * IO Port bases. + */ +#define ACPI_BASE_ADDRESS 0x0400 +#define ACPI_BASE_SIZE 0x80 + +#define GPIO_BASE_ADDRESS 0x0500 +#define GPIO_BASE_SIZE 0x100 + +#define SMBUS_BASE_ADDRESS 0xefa0 + +#endif diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h new file mode 100644 index 0000000..d4d3612 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/irq.h @@ -0,0 +1,119 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _BAYTRAIL_IRQ_H_ +#define _BAYTRAIL_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 +/* The below IRQs are for when devices are in ACPI mode. Active low. */ +#define LPE_DMA0_IRQ 24 +#define LPE_DMA1_IRQ 25 +#define LPE_SSP0_IRQ 26 +#define LPE_SSP1_IRQ 27 +#define LPE_SSP2_IRQ 28 +#define LPE_IPC2HOST_IRQ 29 +#define LPSS_I2C1_IRQ 32 +#define LPSS_I2C2_IRQ 33 +#define LPSS_I2C3_IRQ 34 +#define LPSS_I2C4_IRQ 35 +#define LPSS_I2C5_IRQ 36 +#define LPSS_I2C6_IRQ 37 +#define LPSS_I2C7_IRQ 38 +#define LPSS_HSUART1_IRQ 39 +#define LPSS_HSUART2_IRQ 40 +#define LPSS_SPI_IRQ 41 +#define LPSS_DMA1_IRQ 42 +#define LPSS_DMA2_IRQ 43 +#define SCC_EMMC_IRQ 44 +#define SCC_SDIO_IRQ 46 +#define SCC_SD_IRQ 47 +#define GPIO_NC_IRQ 48 +#define GPIO_SC_IRQ 49 +#define GPIO_SUS_IRQ 50 +/* GPIO direct / dedicated IRQs. */ +#define GPIO_S0_DED_IRQ_0 51 +#define GPIO_S0_DED_IRQ_1 52 +#define GPIO_S0_DED_IRQ_2 53 +#define GPIO_S0_DED_IRQ_3 54 +#define GPIO_S0_DED_IRQ_4 55 +#define GPIO_S0_DED_IRQ_5 56 +#define GPIO_S0_DED_IRQ_6 57 +#define GPIO_S0_DED_IRQ_7 58 +#define GPIO_S0_DED_IRQ_8 59 +#define GPIO_S0_DED_IRQ_9 60 +#define GPIO_S0_DED_IRQ_10 61 +#define GPIO_S0_DED_IRQ_11 62 +#define GPIO_S0_DED_IRQ_12 63 +#define GPIO_S0_DED_IRQ_13 64 +#define GPIO_S0_DED_IRQ_14 65 +#define GPIO_S0_DED_IRQ_15 66 +#define GPIO_S5_DED_IRQ_0 67 +#define GPIO_S5_DED_IRQ_1 68 +#define GPIO_S5_DED_IRQ_2 69 +#define GPIO_S5_DED_IRQ_3 70 +#define GPIO_S5_DED_IRQ_4 71 +#define GPIO_S5_DED_IRQ_5 72 +#define GPIO_S5_DED_IRQ_6 73 +#define GPIO_S5_DED_IRQ_7 74 +#define GPIO_S5_DED_IRQ_8 75 +#define GPIO_S5_DED_IRQ_9 76 +#define GPIO_S5_DED_IRQ_10 77 +#define GPIO_S5_DED_IRQ_11 78 +#define GPIO_S5_DED_IRQ_12 79 +#define GPIO_S5_DED_IRQ_13 80 +#define GPIO_S5_DED_IRQ_14 81 +#define GPIO_S5_DED_IRQ_15 82 +/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ +#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot +#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot +#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) +#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) + +/* PIC IRQ settings. */ +#define PIRQ_PIC_IRQDISABLE 0x0 +#define PIRQ_PIC_IRQ3 0x3 +#define PIRQ_PIC_IRQ4 0x4 +#define PIRQ_PIC_IRQ5 0x5 +#define PIRQ_PIC_IRQ6 0x6 +#define PIRQ_PIC_IRQ7 0x7 +#define PIRQ_PIC_IRQ9 0x9 +#define PIRQ_PIC_IRQ10 0xa +#define PIRQ_PIC_IRQ11 0xb +#define PIRQ_PIC_IRQ12 0xc +#define PIRQ_PIC_IRQ14 0xe +#define PIRQ_PIC_IRQ15 0xf + +/* Overloaded term, but these values determine the per device route. */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* These registers live behind the ILB_BASE_ADDRESS */ +#define ACTL 0x00 +# define SCIS_MASK 0x07 +# define SCIS_IRQ9 0x00 +# define SCIS_IRQ10 0x01 +# define SCIS_IRQ11 0x02 +# define SCIS_IRQ20 0x04 +# define SCIS_IRQ21 0x05 +# define SCIS_IRQ22 0x06 +# define SCIS_IRQ23 0x07 + +#endif /* _BAYTRAIL_IRQ_H_ */ diff --git a/arch/x86/include/asm/arch-baytrail/irqroute.h b/arch/x86/include/asm/arch-baytrail/irqroute.h new file mode 100644 index 0000000..f129880 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/irqroute.h @@ -0,0 +1,67 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2014 Google, Inc + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef IRQROUTE_H +#define IRQROUTE_H + +#include <asm/arch/irq.h> +#include <asm/arch/pci_devs.h> + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 4), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) + +#endif /* IRQROUTE_H */ diff --git a/arch/x86/include/asm/arch-baytrail/pci_devs.h b/arch/x86/include/asm/arch-baytrail/pci_devs.h new file mode 100644 index 0000000..579a228 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/pci_devs.h @@ -0,0 +1,144 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _BAYTRAIL_PCI_DEVS_H_ +#define _BAYTRAIL_PCI_DEVS_H_ + +/* All these devices live on bus 0 with the associated device and function */ + +/* SoC transaction router */ +#define SOC_DEV 0x0 +#define SOC_FUNC 0 +# define SOC_DEVID 0x0f00 + +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +# define GFX_DEVID 0x0f31 + +/* SDIO Port */ +#define SDIO_DEV 0x11 +#define SDIO_FUNC 0 +# define SDIO_DEVID 0x0f15 + +/* SD Port */ +#define SD_DEV 0x12 +#define SD_FUNC 0 +# define SD_DEVID 0x0f16 + +/* SATA */ +#define SATA_DEV 0x13 +#define SATA_FUNC 0 +#define IDE1_DEVID 0x0f20 +#define IDE2_DEVID 0x0f21 +#define AHCI1_DEVID 0x0f22 +#define AHCI2_DEVID 0x0f23 + +/* xHCI */ +#define XHCI_DEV 0x14 +#define XHCI_FUNC 0 +# define XHCI_DEVID 0x0f35 + +/* LPE Audio */ +#define LPE_DEV 0x15 +#define LPE_FUNC 0 +# define LPE_DEVID 0x0f28 + +/* MMC Port */ +#define MMC_DEV 0x17 +#define MMC_FUNC 0 +# define MMC_DEVID 0x0f50 + +/* Serial IO 1 */ +#define SIO1_DEV 0x18 +# define SIO_DMA1_DEV SIO1_DEV +# define SIO_DMA1_FUNC 0 +# define SIO_DMA1_DEVID 0x0f40 +# define I2C1_DEV SIO1_DEV +# define I2C1_FUNC 1 +# define I2C1_DEVID 0x0f41 +# define I2C2_DEV SIO1_DEV +# define I2C2_FUNC 2 +# define I2C2_DEVID 0x0f42 +# define I2C3_DEV SIO1_DEV +# define I2C3_FUNC 3 +# define I2C3_DEVID 0x0f43 +# define I2C4_DEV SIO1_DEV +# define I2C4_FUNC 4 +# define I2C4_DEVID 0x0f44 +# define I2C5_DEV SIO1_DEV +# define I2C5_FUNC 5 +# define I2C5_DEVID 0x0f45 +# define I2C6_DEV SIO1_DEV +# define I2C6_FUNC 6 +# define I2C6_DEVID 0x0f46 +# define I2C7_DEV SIO1_DEV +# define I2C7_FUNC 7 +# define I2C7_DEVID 0x0f47 + +/* Trusted Execution Engine */ +#define TXE_DEV 0x1a +#define TXE_FUNC 0 +# define TXE_DEVID 0x0f18 + +/* HD Audio */ +#define HDA_DEV 0x1b +#define HDA_FUNC 0 +# define HDA_DEVID 0x0f04 + +/* PCIe Ports */ +#define PCIE_DEV 0x1c +# define PCIE_PORT1_DEV PCIE_DEV +# define PCIE_PORT1_FUNC 0 +# define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT2_DEV PCIE_DEV +# define PCIE_PORT2_FUNC 1 +# define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT3_DEV PCIE_DEV +# define PCIE_PORT3_FUNC 2 +# define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT4_DEV PCIE_DEV +# define PCIE_PORT4_FUNC 3 +# define PCIE_PORT4_DEVID 0x0f4e + +/* EHCI */ +#define EHCI_DEV 0x1d +#define EHCI_FUNC 0 +# define EHCI_DEVID 0x0f34 + +/* Serial IO 2 */ +#define SIO2_DEV 0x1e +# define SIO_DMA2_DEV SIO2_DEV +# define SIO_DMA2_FUNC 0 +# define SIO_DMA2_DEVID 0x0f06 +# define PWM1_DEV SIO2_DEV +# define PWM1_FUNC 1 +# define PWM1_DEVID 0x0f08 +# define PWM2_DEV SIO2_DEV +# define PWM2_FUNC 2 +# define PWM2_DEVID 0x0f09 +# define HSUART1_DEV SIO2_DEV +# define HSUART1_FUNC 3 +# define HSUART1_DEVID 0x0f0a +# define HSUART2_DEV SIO2_DEV +# define HSUART2_FUNC 4 +# define HSUART2_DEVID 0x0f0c +# define SPI_DEV SIO2_DEV +# define SPI_FUNC 5 +# define SPI_DEVID 0xf0e + +/* Platform Controller Unit */ +#define PCU_DEV 0x1f +# define LPC_DEV PCU_DEV +# define LPC_FUNC 0 +# define LPC_DEVID 0x0f1c +# define SMBUS_DEV PCU_DEV +# define SMBUS_FUNC 3 +# define SMBUS_DEVID 0x0f12 + +#endif /* _BAYTRAIL_PCI_DEVS_H_ */ diff --git a/arch/x86/include/asm/arch-baytrail/pmc.h b/arch/x86/include/asm/arch-baytrail/pmc.h new file mode 100644 index 0000000..16d4ce7 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/pmc.h @@ -0,0 +1,253 @@ +/* + * From Coreboot file of same name + * + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _BAYTRAIL_PMC_H_ +#define _BAYTRAIL_PMC_H_ + + +#define IOCOM1 0x3f8 + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x00 +# define PMC_WDT_STS (1 << 15) +# define SEC_GBLRST_STS (1 << 7) +# define SEC_WDT_STS (1 << 6) +# define WOL_OVR_WK_STS (1 << 5) +# define PMC_WAKE_STS (1 << 4) +#define PMC_CFG 0x08 +# define SPS (1 << 5) +# define NO_REBOOT (1 << 4) +# define SX_ENT_TO_EN (1 << 3) +# define TIMING_T581_SHIFT (0) +# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) +# define TIMING_T581_10US (0 << TIMING_T581_SHIFT) +# define TIMING_T581_100US (1 << TIMING_T581_SHIFT) +# define TIMING_T581_1MS (2 << TIMING_T581_SHIFT) +# define TIMING_T581_10MS (3 << TIMING_T581_SHIFT) +#define VLV_PM_STS 0x0c +# define PMC_MSG_FULL_STS (1 << 24) +# define PMC_MSG_4_FULL_STS (1 << 23) +# define PMC_MSG_3_FULL_STS (1 << 22) +# define PMC_MSG_2_FULL_STS (1 << 21) +# define PMC_MSG_1_FULL_STS (1 << 20) +# define CODE_REQ (1 << 8) +# define HPR_ENT_TO (1 << 2) +# define SX_ENT_TO (1 << 1) +#define GEN_PMCON1 0x20 +# define UART_EN (1 << 24) +# define DISB (1 << 23) +# define MEM_SR (1 << 21) +# define SRS (1 << 20) +# define CTS (1 << 19) +# define MS4V (1 << 18) +# define PWR_FLR (1 << 16) +# define PME_B0_S5_DIS (1 << 15) +# define SUS_PWR_FLR (1 << 14) +# define WOL_EN_OVRD (1 << 13) +# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +# define GEN_RST_STS (1 << 9) +# define RPS (1 << 2) +# define AFTERG3_EN (1 << 0) +#define GEN_PMCON2 0x24 +# define SLPSX_STR_POL_LOCK (1 << 18) +# define BIOS_PCI_EXP_EN (1 << 10) +# define PWRBTN_LVL (1 << 9) +# define SMI_LOCK (1 << 4) +#define ETR 0x48 +# define CF9LOCK (1 << 31) +# define LTR_DEF (1 << 22) +# define IGNORE_HPET (1 << 21) +# define CF9GR (1 << 20) +# define CWORWRE (1 << 18) +#define FUNC_DIS 0x34 +# define SIO_DMA2_DIS (1 << 0) +# define PWM1_DIS (1 << 1) +# define PWM2_DIS (1 << 2) +# define HSUART1_DIS (1 << 3) +# define HSUART2_DIS (1 << 4) +# define SPI_DIS (1 << 5) +# define SDIO_DIS (1 << 9) +# define SD_DIS (1 << 10) +# define MMC_DIS (1 << 11) +# define HDA_DIS (1 << 12) +# define LPE_DIS (1 << 13) +# define OTG_DIS (1 << 14) +# define XHCI_DIS (1 << 15) +# define SATA_DIS (1 << 17) +# define EHCI_DIS (1 << 18) +# define TXE_DIS (1 << 19) +# define PCIE_PORT1_DIS (1 << 20) +# define PCIE_PORT2_DIS (1 << 21) +# define PCIE_PORT3_DIS (1 << 22) +# define PCIE_PORT4_DIS (1 << 23) +# define SIO_DMA1_DIS (1 << 24) +# define I2C1_DIS (1 << 25) +# define I2C2_DIS (1 << 26) +# define I2C3_DIS (1 << 27) +# define I2C4_DIS (1 << 28) +# define I2C5_DIS (1 << 29) +# define I2C6_DIS (1 << 30) +# define I2C7_DIS (1 << 31) +#define FUNC_DIS2 0x38 +# define USH_SS_PHY_DIS (1 << 2) +# define OTG_SS_PHY_DIS (1 << 1) +# define SMBUS_DIS (1 << 0) +#define GPIO_ROUT 0x58 +# define ROUTE_MASK 3 +# define ROUTE_NONE 0 +# define ROUTE_SMI 1 +# define ROUTE_SCI 2 +#define PLT_CLK_CTL_0 0x60 +#define PLT_CLK_CTL_1 0x64 +#define PLT_CLK_CTL_2 0x68 +#define PLT_CLK_CTL_3 0x6c +#define PLT_CLK_CTL_4 0x70 +#define PLT_CLK_CTL_5 0x74 +# define CLK_FREQ_25MHZ (0x0 << 2) +# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_CTL_D3_LPE (0x0 << 0) +# define CLK_CTL_ON (0x1 << 0) +# define CLK_CTL_OFF (0x2 << 0) +#define PME_STS 0xc0 +#define GPE_LEVEL_EDGE 0xc4 +# define GPE_EDGE 0 +# define GPE_LEVEL 1 +#define GPE_POLARITY 0xc8 +# define GPE_ACTIVE_HIGH 1 +# define GPE_ACTIVE_LOW 0 +#define LOCK 0xcc + +/* IO Mapped registers behind ACPI_BASE_ADDRESS */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define USB_STS (1 << 13) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define USB_WAKE_EN (1 << 13) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define GPE0_STS 0x20 +#define CORE_GPIO_STS7 (1 << 31) +#define CORE_GPIO_STS6 (1 << 30) +#define CORE_GPIO_STS5 (1 << 29) +#define CORE_GPIO_STS4 (1 << 28) +#define CORE_GPIO_STS3 (1 << 27) +#define CORE_GPIO_STS2 (1 << 26) +#define CORE_GPIO_STS1 (1 << 25) +#define CORE_GPIO_STS0 (1 << 24) +#define SUS_GPIO_STS7 (1 << 23) +#define SUS_GPIO_STS6 (1 << 22) +#define SUS_GPIO_STS5 (1 << 21) +#define SUS_GPIO_STS4 (1 << 20) +#define SUS_GPIO_STS3 (1 << 19) +#define SUS_GPIO_STS2 (1 << 18) +#define SUS_GPIO_STS1 (1 << 17) +#define SUS_GPIO_STS0 (1 << 16) +#define PME_B0_STS (1 << 13) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define PCIE_WAKE3_STS (1 << 8) +#define PCIE_WAKE2_STS (1 << 7) +#define PCIE_WAKE1_STS (1 << 6) +#define GUNIT_SCI_STS (1 << 5) +#define PUNIT_SCI_STS (1 << 4) +#define PCIE_WAKE0_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN 0x28 +#define CORE_GPIO_EN7 (1 << 31) +#define CORE_GPIO_EN6 (1 << 30) +#define CORE_GPIO_EN5 (1 << 29) +#define CORE_GPIO_EN4 (1 << 28) +#define CORE_GPIO_EN3 (1 << 27) +#define CORE_GPIO_EN2 (1 << 26) +#define CORE_GPIO_EN1 (1 << 25) +#define CORE_GPIO_EN0 (1 << 24) +#define SUS_GPIO_EN7_BIT 23 +#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) +#define SUS_GPIO_EN6_BIT 22 +#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) +#define SUS_GPIO_EN5_BIT 21 +#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) +#define SUS_GPIO_EN4_BIT 20 +#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) +#define SUS_GPIO_EN3_BIT 19 +#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) +#define SUS_GPIO_EN2_BIT 18 +#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) +#define SUS_GPIO_EN1_BIT 17 +#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) +#define SUS_GPIO_EN0_BIT 16 +#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) +#define PME_B0_EN (1 << 13) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define PCIE_WAKE3_EN (1 << 8) +#define PCIE_WAKE2_EN (1 << 7) +#define PCIE_WAKE1_EN (1 << 6) +#define PCIE_WAKE0_EN (1 << 3) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) +#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT +#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) +#define SMI_EN 0x30 +#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ +#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ +#define SMI_STS 0x34 +#define ALT_GPIO_SMI 0x38 +#define UPRWC 0x3c +# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ +#define GPE_CTRL 0x40 +#define PM2A_CNT_BLK 0x50 +#define TCO_RLD 0x60 +#define TCO_STS 0x64 +# define SECOND_TO_STS (1 << 17) +# define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 +# define TCO_LOCK (1 << 12) +# define TCO_TMR_HALT (1 << 11) +#define TCO_TMR 0x70 + +/* I/O ports */ +#define RST_CNT 0xcf9 +# define FULL_RST (1 << 3) +# define RST_CPU (1 << 2) +# define SYS_RST (1 << 1) + +#endif /* _BAYTRAIL_PMC_H_ */ + diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index 6e82b16..c7b53f5 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -9,15 +9,227 @@ #include <asm/pnp_def.h> #include <netdev.h> #include <smsc_lpc47m.h> +#include <asm/arch/gpio.h> #define SERIAL_DEV PNP_DEV(0x2e, 4) DECLARE_GLOBAL_DATA_PTR; +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * The pads list is in the BWG_VOL2 Rev1p2: + * Note that Pad # is not the same as GPIO# + * 37 GPIO Handling: + * Table 37-1. SCORE Pads List + * Table 37-2. SSUSORE Pads List + */ + +/* NCORE GPIOs */ +static const struct byt_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */ + GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */ + GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */ + GPIO_NC, /* GPIO_S0_NC[03] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[04] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[05] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[06] - No Connect */ + GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */ + GPIO_NC, /* GPIO_S0_NC[08] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[09] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[10] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[11] - No Connect */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */ + GPIO_NC, /* GPIO_S0_NC[13] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[14] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[15] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[16] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[17] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[18] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[19] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[20] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[21] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[22] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[23] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[24] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[25] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[26] - No Connect */ + GPIO_END +}; + +/* SCORE GPIOs (GPIO_S0_SC_XX)*/ +static const struct byt_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */ + GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */ + GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */ + GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */ + GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */ + GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */ + GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */ + GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */ + GPIO_NC, /* GPIO_S0_SC[008] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[009] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[010] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[011] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[012] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[013] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[014] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[015] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[016] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[017] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[018] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[019] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[020] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[021] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[022] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[023] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[024] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[025] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[026] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[027] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[028] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[029] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[030] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[031] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[032] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */ + GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */ + GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */ + GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */ + GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */ + GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */ + GPIO_FUNC1, /* GPIO_S0_SC[040] - TP12 (SD3_1P8EN) */ + GPIO_FUNC1, /* GPIO_S0_SC[041] - TP11 (/SD3_PWREN) */ + GPIO_NC, /* GPIO_S0_SC[042] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[043] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[044] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[045] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[046] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[047] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[048] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[049] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[050] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */ + GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */ + /* GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55) */ + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */ + GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */ + /* GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58) */ + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC0, /* GPIO_S0_SC[059] - HDMI_DCDC_ENB */ + GPIO_FUNC0, /* GPIO_S0_SC[060] - HDMI_LDSW_ENB */ + GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */ + GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */ + GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */ + GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */ + GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */ + GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */ + GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */ + GPIO_FUNC1, /* GPIO_S0_SC[072] - SIO_UART1_RTSB */ + GPIO_FUNC1, /* GPIO_S0_SC[073] - SIO_UART1_CTSB */ + GPIO_FUNC1, /* GPIO_S0_SC[074] - SIO_UART2_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[075] - SIO_UART2_TXD */ + GPIO_NC, /* GPIO_S0_SC[076] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[077] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[078] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[079] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA) */ + GPIO_FUNC1, /* GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL) */ + GPIO_NC, /* GPIO_S0_SC[082] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[083] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[084] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[085] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[086] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[087] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[088] - LSS_I2C_SDA */ + GPIO_FUNC1, /* GPIO_S0_SC[089] - LSS_I2C_SCL */ + GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */ + GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */ + GPIO_FUNC(1, PULL_UP, 20K), /* GPIO_S0_SC[092] - TP13 */ + GPIO_FUNC(1, PULL_UP, 20K), /* GPIO_S0_SC[093] - TP16 */ + GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */ + GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */ + GPIO_NC, /* GPIO_S0_SC[096] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[097] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[098] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[099] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[100] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[101] - No Connect */ + GPIO_END +}; + +/* SSUS GPIOs (GPIO_S5) */ +static const struct byt_gpio_map gpssus_gpio_map[] = { + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[00] - SOC_GPIO_S5_0 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[01] - SOC_GPIO_S5_1 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[02] - SOC_GPIO_S5_2 */ + GPIO_FUNC6, /* GPIO_S5[03] - mPCIE_WAKEB */ + GPIO_NC, /* GPIO_S5[04] - No Connect */ + GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 */ + GPIO_INPUT, /* GPIO_S5[06] - BOM_OP2 */ + GPIO_INPUT, /* GPIO_S5[07] - BOM_OP3 */ + GPIO_OUT_HIGH, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */ + GPIO_OUT_HIGH, /* GPIO_S5[09] - SOC_USB_HOST_EN1 */ + GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ + GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK (TP14) */ + GPIO_FUNC0, /* GPIO_S5[12] - PMC_SUSCLK0 */ + GPIO_FUNC1, /* GPIO_S5[13] - PMC_SLP_S0IX (TP10) */ + GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */ + GPIO_FUNC0, /* GPIO_S5[15] - PMC_PCIE_WAKE_R */ + GPIO_FUNC0, /* GPIO_S5[16] - PMC_PWRBTN */ + GPIO_NC1, /* GPIO_S5[17] - No Connect */ + GPIO_FUNC1, /* GPIO_S5[18] - LPCPD_L (TP7) */ + GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */ + GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */ + GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */ + GPIO_NC, /* GPIO_S5[22] - No Connect */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[23] - XDP_H_OBSDATA_A0 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[24] - XDP_H_OBSDATA_A1 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[25] - XDP_H_OBSDATA_A2 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[26] - XDP_H_OBSDATA_A3 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[27] - EXP_GPIO1 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[28] - EXP_GPIO2 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[29] - EXP_GPIO3 */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[30] - EXP_GPIO4 */ + GPIO_NC, /* GPIO_S5[31] - No Connect */ + GPIO_NC, /* GPIO_S5[32] - No Connect */ + GPIO_NC, /* GPIO_S5[33] - No Connect */ + GPIO_NC, /* GPIO_S5[34] - No Connect */ + GPIO_NC, /* GPIO_S5[35] - No Connect */ + GPIO_NC, /* GPIO_S5[36] - No Connect */ + GPIO_NC, /* GPIO_S5[37] - No Connect */ + GPIO_NC, /* GPIO_S5[38] - No Connect */ + GPIO_NC, /* GPIO_S5[39] - No Connect */ + GPIO_NC, /* GPIO_S5[40] - No Connect */ + GPIO_NC, /* GPIO_S5[41] - No Connect */ + GPIO_NC, /* GPIO_S5[42] - No Connect */ + GPIO_NC, /* GPIO_S5[43] - No Connect */ + GPIO_END +}; + +static struct byt_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, +}; + int board_early_init_f(void) { lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); + setup_soc_gpios(&gpio_config); + return 0; } diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + #endif /* __CONFIG_H */ -- 2.1.4

5 20

[U-Boot] [PATCH] omap3: pandora: use common configuration
by Grazvydas Ignotas 09 Apr '15

09 Apr '15

From: notaz <notasas(a)gmail.com> This allows to clean up the config a good deal and also converts pandora to Generic Board. Signed-off-by: Grazvydas Ignotas <notasas(a)gmail.com> --- include/configs/omap3_pandora.h | 177 ++++++++-------------------------------- 1 file changed, 36 insertions(+), 141 deletions(-) diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 11d7b86..8d3531c 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -10,22 +10,13 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define CONFIG_NAND -#define CONFIG_SDRC /* The chip has SDRC controller */ +/* override base for compatibility with MLO the device ships with */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> +#include <configs/ti_omap3_common.h> /* * Display CPU and Board information @@ -33,79 +24,42 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* * Hardware drivers */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SYS_DEVICE_NULLDEV 1 +/* I2C Support */ +#define CONFIG_SYS_I2C_OMAP34XX -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 +/* TWL4030 LED */ +#define CONFIG_TWL4030_LED -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 +/* Initialize GPIOs by default */ +#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */ /* * NS16550 Configuration */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 +#undef CONFIG_OMAP_SERIAL #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SERIAL3 3 -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - /* commands to include */ #include <config_cmd_default.h> -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ - -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_CACHE /* Cache control */ - #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ @@ -113,53 +67,36 @@ #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 -#define CONFIG_TWL4030_LED 1 - /* * Board NAND Info. */ -#define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand */ - /* at CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ - -#ifdef CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_RBTREE -#define CONFIG_LZO - -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:512k(xloader),"\ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 + +#ifdef CONFIG_NAND +#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */ +#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */ + +#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */ +#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */ + +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ + +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(xloader),"\ "1920k(uboot),128k(uboot-env),"\ "10m(boot),-(rootfs)" #else #define MTDPARTS_DEFAULT #endif -/* Environment information */ -#define CONFIG_BOOTDELAY 1 - #define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ "usbtty=cdc_acm\0" \ - "loadaddr=0x82000000\0" \ "bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \ "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ @@ -172,60 +109,18 @@ "ubi part boot && ubifsmount ubi:boot && " \ "ubifsload ${loadaddr} uImage && bootm ${loadaddr}" -#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#undef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "Pandora # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command */ - /* args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -#define CONFIG_SYS_TEXT_BASE 0x80008000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_CMD_NAND) +#if defined(CONFIG_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE #endif -- 1.9.1

1 0

[U-Boot] [PATCH v3 1/3] usb: usb_new_device return codes consistency
by Paul Kocialkowski 08 Apr '15

08 Apr '15

This makes use of errno return codes for representing error codes in a unified way. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- common/usb.c | 58 +++++++++++++++++++++++++++++----------------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/common/usb.c b/common/usb.c index 32e15cd..1288ca0 100644 --- a/common/usb.c +++ b/common/usb.c @@ -116,7 +116,7 @@ int usb_init(void) if (controllers_initialized == 0) puts("USB error: all controllers failed lowlevel init\n"); - return usb_started ? 0 : -1; + return usb_started ? 0 : -ENODEV; } /****************************************************************************** @@ -186,7 +186,7 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, if ((timeout == 0) && (!asynch_allowed)) { /* request for a asynch control pipe is not allowed */ - return -1; + return -EINVAL; } /* set setup command */ @@ -201,7 +201,7 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, dev->status = USB_ST_NOT_PROC; /*not yet processed */ if (submit_control_msg(dev, pipe, data, size, setup_packet) < 0) - return -1; + return -EIO; if (timeout == 0) return (int)size; @@ -224,17 +224,17 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, /*------------------------------------------------------------------- * submits bulk message, and waits for completion. returns 0 if Ok or - * -1 if Error. + * negative if Error. * synchronous behavior */ int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout) { if (len < 0) - return -1; + return -EINVAL; dev->status = USB_ST_NOT_PROC; /*not yet processed */ if (submit_bulk_msg(dev, pipe, data, len) < 0) - return -1; + return -EIO; while (timeout--) { if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC)) break; @@ -244,7 +244,7 @@ int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, if (dev->status == 0) return 0; else - return -1; + return -EIO; } @@ -350,11 +350,11 @@ static int usb_parse_config(struct usb_device *dev, if (head->bDescriptorType != USB_DT_CONFIG) { printf(" ERROR: NOT USB_CONFIG_DESC %x\n", head->bDescriptorType); - return -1; + return -EINVAL; } if (head->bLength != USB_DT_CONFIG_SIZE) { printf("ERROR: Invalid USB CFG length (%d)\n", head->bLength); - return -1; + return -EINVAL; } memcpy(&dev->config, head, USB_DT_CONFIG_SIZE); dev->config.no_of_if = 0; @@ -383,7 +383,7 @@ static int usb_parse_config(struct usb_device *dev, if (ifno >= USB_MAXINTERFACES) { puts("Too many USB interfaces!\n"); /* try to go on with what we have */ - return 1; + return -EINVAL; } if_desc = &dev->config.if_desc[ifno]; dev->config.no_of_if++; @@ -421,7 +421,7 @@ static int usb_parse_config(struct usb_device *dev, if (epno > USB_MAXENDPOINTS) { printf("Interface %d has too many endpoints!\n", if_desc->desc.bInterfaceNumber); - return 1; + return -EINVAL; } /* found an endpoint */ if_desc->no_of_ep++; @@ -459,7 +459,7 @@ static int usb_parse_config(struct usb_device *dev, break; default: if (head->bLength == 0) - return 1; + return -EINVAL; debug("unknown Description Type : %x\n", head->bDescriptorType); @@ -479,7 +479,7 @@ static int usb_parse_config(struct usb_device *dev, index += head->bLength; head = (struct usb_descriptor_header *)&buffer[index]; } - return 1; + return 0; } /*********************************************************************** @@ -546,14 +546,14 @@ int usb_get_configuration_no(struct usb_device *dev, else printf("config descriptor too short " \ "(expected %i, got %i)\n", 9, result); - return -1; + return -EIO; } length = le16_to_cpu(config->wTotalLength); if (length > USB_BUFSIZ) { printf("%s: failed to get descriptor - too long: %d\n", __func__, length); - return -1; + return -EIO; } result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, length); @@ -595,7 +595,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate) } if (!if_face) { printf("selecting invalid interface %d", interface); - return -1; + return -EINVAL; } /* * We should return now for devices with only one alternate setting. @@ -634,7 +634,7 @@ static int usb_set_configuration(struct usb_device *dev, int configuration) dev->toggle[1] = 0; return 0; } else - return -1; + return -EIO; } /******************************************************************** @@ -748,7 +748,7 @@ static int usb_string_sub(struct usb_device *dev, unsigned int langid, } if (rc < 2) - rc = -1; + rc = -EINVAL; return rc; } @@ -767,7 +767,7 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size) unsigned int u, idx; if (size <= 0 || !buf || !index) - return -1; + return -EINVAL; buf[0] = 0; tbuf = &mybuf[0]; @@ -777,10 +777,10 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size) if (err < 0) { debug("error getting string descriptor 0 " \ "(error=%lx)\n", dev->status); - return -1; + return -EIO; } else if (tbuf[0] < 4) { debug("string descriptor 0 too short\n"); - return -1; + return -EIO; } else { dev->have_langid = -1; dev->string_langid = tbuf[2] | (tbuf[3] << 8); @@ -893,7 +893,7 @@ int usb_new_device(struct usb_device *dev) */ if (usb_alloc_device(dev)) { printf("Cannot allocate device context to get SLOT_ID\n"); - return -1; + return -EINVAL; } /* We still haven't set the Address yet */ @@ -915,7 +915,7 @@ int usb_new_device(struct usb_device *dev) if (err < 8) { printf("\n USB device not responding, " \ "giving up (status=%lX)\n", dev->status); - return 1; + return -EIO; } memcpy(&dev->descriptor, tmpbuf, 8); #else @@ -952,7 +952,7 @@ int usb_new_device(struct usb_device *dev) err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64); if (err < 0) { debug("usb_new_device: usb_get_descriptor() failed\n"); - return 1; + return -EIO; } dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0; @@ -968,7 +968,7 @@ int usb_new_device(struct usb_device *dev) err = hub_port_reset(dev->parent, dev->portnr - 1, &portstatus); if (err < 0) { printf("\n Couldn't reset port %i\n", dev->portnr); - return 1; + return -EIO; } } else { usb_reset_root_port(); @@ -998,7 +998,7 @@ int usb_new_device(struct usb_device *dev) if (err < 0) { printf("\n USB device not accepting new address " \ "(error=%lX)\n", dev->status); - return 1; + return -EIO; } mdelay(10); /* Let the SET_ADDRESS settle */ @@ -1014,7 +1014,7 @@ int usb_new_device(struct usb_device *dev) else printf("USB device descriptor short read " \ "(expected %i, got %i)\n", tmp, err); - return 1; + return -EIO; } memcpy(&dev->descriptor, tmpbuf, sizeof(dev->descriptor)); /* correct le values */ @@ -1028,7 +1028,7 @@ int usb_new_device(struct usb_device *dev) printf("usb_new_device: Cannot read configuration, " \ "skipping device %04x:%04x\n", dev->descriptor.idVendor, dev->descriptor.idProduct); - return -1; + return -EIO; } usb_parse_config(dev, tmpbuf, 0); usb_set_maxpacket(dev); @@ -1036,7 +1036,7 @@ int usb_new_device(struct usb_device *dev) if (usb_set_configuration(dev, dev->config.desc.bConfigurationValue)) { printf("failed to set default configuration " \ "len %d, status %lX\n", dev->act_len, dev->status); - return -1; + return -EIO; } debug("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n", dev->descriptor.iManufacturer, dev->descriptor.iProduct, -- 1.9.1

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[U-Boot] [PATCH 0/23] net: cosmetic: Fix naming and other checkpatch.pl issues in net/
by Joe Hershberger 08 Apr '15

08 Apr '15

3 102

[U-Boot] please pull u-boot-samsung master
by Minkyu Kang 08 Apr '15

08 Apr '15

Dear Tom, The following changes since commit d68df028099235c5316eec1ed5f586f3744a8707: Merge git://git.denx.de/u-boot-arc (2015-04-03 09:14:44 -0400) are available in the git repository at: http://git.denx.de/u-boot-samsung for you to fetch changes up to 1018b0a56a4719a64fb6867337a72d6a9343008b: config: exynos: trats2: Enable support for Image.itb at trats2 device (2015-04-06 15:23:59 +0900) ---------------------------------------------------------------- Ajay Kumar (8): arm: exynos: add display clocks for Exynos5800 Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels video: exynos_fb: configure backlight GPIOs if specified in DT video: parade: configure SLP and RST GPIOs if specified in DT dts: exynos54xx: Add samsung, pwm-out-gpio property to FIMD node dts: peach_pit: Add SLP and RST GPIO properties in parade DT node dts: peach_pi: Add DT properties needed for display smdk5420: Remove GPIO enums Guillaume GARDET (1): Exynos: Clock: Fix exynos5_get_periph_rate for I2C. Inha Song (1): exynos5: add trace feature #ifdef in exynos5-common.h Sjoerd Simons (1): config: peach: Correct memory layout environment settings Łukasz Majewski (3): config: exynos: common: Provide env variables to support Image.itb config: exynos: trats: Enable support for Image.itb at trats device config: exynos: trats2: Enable support for Image.itb at trats2 device arch/arm/cpu/armv7/exynos/clock.c | 69 ++++++++++++++++++++++-- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 4 +- arch/arm/dts/exynos5420-peach-pit.dts | 2 + arch/arm/dts/exynos54xx.dtsi | 1 + arch/arm/dts/exynos5800-peach-pi.dts | 3 ++ arch/arm/include/asm/arch-exynos/clk.h | 3 ++ board/samsung/smdk5420/smdk5420.c | 15 ------ doc/device-tree-bindings/video/exynos-fb.txt | 2 + drivers/video/exynos_fb.c | 21 ++++++++ drivers/video/parade.c | 11 ++++ include/configs/exynos4-common.h | 54 +++++++++++++++++++ include/configs/exynos5-common.h | 4 +- include/configs/peach-pi.h | 8 +++ include/configs/peach-pit.h | 8 +++ include/configs/trats.h | 8 ++- include/configs/trats2.h | 8 ++- 16 files changed, 193 insertions(+), 28 deletions(-) -- Thanks, Minkyu Kang.

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[U-Boot] How to reduce SDcard speed in u-boot
by Marco Cavallini 08 Apr '15

08 Apr '15

Hello, I am probably working on a 'buggy hardware' based on i.MX6 that isn't able to manage a SDcard speed properly. I mean, u-boot starts, but as soon as I try to perform a fatload if the uImage the command won't work properly. I had the possibility to test the SoM on another carrier with a different layout and a different microSD connector and it works at every boot. The quick and dirty hack I found is to modify sd_switch() in drivers/mmc/mmc.c in this way /* * Reduce SD/MMC speed * u-boot> mmc info * before : Tran Speed: 50000000 * after : Tran Speed: 25000000 */ printf("*** Skip support SD_HIGHSPEED in sd_change_freq\n") ; return 0; just before /* If high-speed isn't supported, we return */ if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) return 0; the problem is that on 80% of the carrier boards the problem is still present. My questions are: 1. is this hack the best solution in this case or can you suggest me another better way to proceed? 2. would be possible to reduce the speed more than this and how? thank you in advance -- Marco

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[U-Boot] socfpga: missing DECLARE_GLOBAL_DATA_PTR in timer.c
by Pavel Machek 08 Apr '15

08 Apr '15

for A in `find . -name "*.c"`; do if grep DECLARE_GLOBAL_DATA_PTR $A; then echo -n; else echo $A; fi; done reveals a few files that probably should have DECLARE_GLOBAL_DATA_PTR. This fixes it for arch/arm/cpu/armv7/socfpga/timer.c . Signed-off-by: Pavel Machek <pavel(a)denx.de> index 253cde3..2dd8376 100644 --- a/arch/arm/cpu/armv7/socfpga/timer.c +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -8,6 +8,8 @@ #include <asm/io.h> #include <asm/arch/timer.h> +DECLARE_GLOBAL_DATA_PTR; + #define TIMER_LOAD_VAL 0xFFFFFFFF static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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