March 2015 - U-Boot

[U-Boot] [PATCH] common/board_f: implement type casting for gd structure
by Alexey Brodkin 06 Mar '15

06 Mar '15

In case of global data structure defined as "register volatile" compiler throws an warning about incorrect type used: --->8--- common/board_f.c: In function "board_init_f_r": common/board_f.c:1073:2: warning: passing argument 1 of "&board_init_r +(sizetype)gd->reloc_off" discards "volatile" qualifier from pointer target type [enabled by default] (board_init_r + gd->reloc_off)(gd, gd->relocaddr); ^ common/board_f.c:1073:2: note: expected "struct gd_t *" but argument is of type "volatile struct gd_t *" --->8--- An obvious fix is manual casting to "gd_t *". Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)ti.com> --- common/board_f.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/board_f.c b/common/board_f.c index a1dcc5f..96a23ae 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -1070,7 +1070,7 @@ void board_init_f_r(void) * Transfer execution from Flash to RAM by calculating the address * of the in-RAM copy of board_init_r() and calling it */ - (board_init_r + gd->reloc_off)(gd, gd->relocaddr); + (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); /* NOTREACHED - board_init_r() does not return */ hang(); -- 2.1.0

3 2

[U-Boot] [PATCH] lib/asm-offsets - make GD_RELOCADDR, GD_RELOC_OFF & GD_START_ADDR_SP available for all architectures
by Alexey Brodkin 06 Mar '15

06 Mar '15

GD_RELOCADDR, GD_RELOC_OFF & GD_START_ADDR_SP are generic members of global data structure so why don't we allow architectures other than ARM to use it. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)ti.com> --- lib/asm-offsets.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c index 129bc3e..221ebbf 100644 --- a/lib/asm-offsets.c +++ b/lib/asm-offsets.c @@ -32,15 +32,11 @@ int main(void) DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base)); #endif -#if defined(CONFIG_ARM) - DEFINE(GD_RELOCADDR, offsetof(struct global_data, relocaddr)); DEFINE(GD_RELOC_OFF, offsetof(struct global_data, reloc_off)); DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp)); -#endif - return 0; } -- 2.1.0

3 2

[U-Boot] [PATCH] spl: fix calling "spl export .." more than once
by Heiko Schocher 06 Mar '15

06 Mar '15

running "spl export ..." more than once fails with: Trying to execute a command out of order Trying to execute a command out of order Trying to execute a command out of order Trying to execute a command out of order Trying to execute a command out of order Trying to execute a command out of order ERROR prep subcommand failed! Subcommand failed reason is commmit: 35fc84fa1f: Refactor the bootm command to reduce code duplication It used "state != BOOTM_STATE_START" but state is a bitfield, so check if the bit BOOTM_STATE_START is not set. With this fix, "spl export ..." can called more than once ... Signed-off-by: Heiko Schocher <hs(a)denx.de> --- common/cmd_bootm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 48199bf..4f77f22 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -78,7 +78,8 @@ static int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_USAGE; } - if (state != BOOTM_STATE_START && images.state >= state) { + if (((state & BOOTM_STATE_START) != BOOTM_STATE_START) && + images.state >= state) { printf("Trying to execute a command out of order\n"); return CMD_RET_USAGE; } -- 2.1.0

3 2

[U-Boot] [PATCH 1/2] vexpress64: juno: add NOR flash detection
by Linus Walleij 06 Mar '15

06 Mar '15

This enables the vexpress64 to detect its NOR flash so that we can load kernel etc from it. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- include/configs/vexpress_aemv8a.h | 41 ++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 5ffc84dc5ecd..bcfcb63d81d8 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -29,8 +29,6 @@ /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ -#define CONFIG_SYS_NO_FLASH - #define CONFIG_SUPPORT_RAW_INITRD /* Cache Definitions */ @@ -56,14 +54,6 @@ /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT -/* CS register bases for the original memory map. */ -#define V2M_PA_CS0 0x00000000 -#define V2M_PA_CS1 0x14000000 -#define V2M_PA_CS2 0x18000000 -#define V2M_PA_CS3 0x1c000000 -#define V2M_PA_CS4 0x0c000000 -#define V2M_PA_CS5 0x10000000 - #define V2M_PERIPH_OFFSET(x) (x << 16) #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) @@ -71,13 +61,6 @@ #define V2M_BASE 0x80000000 -/* - * Physical addresses, offset from V2M_PA_CS0-3 - */ -#define V2M_NOR0 (V2M_PA_CS0) -#define V2M_NOR1 (V2M_PA_CS4) -#define V2M_SRAM (V2M_PA_CS1) - /* Common peripherals relative to CS7. */ #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) @@ -175,7 +158,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PXE #define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_LOADB #define CONFIG_CMD_MEMORY @@ -258,4 +240,27 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_MAXARGS 64 /* max command args */ +/* Flash memory is available on the Juno board only */ +#ifndef CONFIG_TARGET_VEXPRESS64_JUNO +#define CONFIG_SYS_NO_FLASH +#else +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +/* Timeout values in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ + +/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ +#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ +#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ + +#endif + #endif /* __VEXPRESS_AEMV8A_H */ -- 1.9.3

2 1

[U-Boot] omap_gpmc: Do not default to HAM1 when SW ECC is selected
by Adam YH Lee 06 Mar '15

06 Mar '15

The ECC scheme selection algorithm in OMAP GPMC appears to be left untested when BCH8 handling code was added. Running 'nandecc sw' defaults to HAM1 even if the board is using another scheme (ex. OMAP_ECC_BCH8_CODE_HW_DETECTION_SW on OMAP3). This results in unrecoverable ECC errors when reading data. This commit fixes the behavior by checking for CONFIG_BCH and using the scheme defined by CONFIG_NAND_OMAP_ECCSCHEME in the board configuration file. This has been tested on Gumstix Overo (OMAP3). Signed-off-by: Adam YH Lee <adam.yh.lee(a)gmail.com> --- drivers/mtd/nand/omap_gpmc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index fc64f48..5daf932 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -901,8 +901,13 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) return -EINVAL; } } else { + #ifdef CONFIG_BCH + err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, + mtd->writesize, mtd->oobsize); + #else err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, mtd->writesize, mtd->oobsize); + #endif } /* Update NAND handling after ECC mode switch */ -- 1.9.1

5 5

[U-Boot] [PATCH v2] mtd: nand: omap_gpmc: Make ready/busy pins configurable
by sojkam1＠fel.cvut.cz 06 Mar '15

06 Mar '15

From: Michal Sojka <sojka(a)merica.cz> Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of WAIT0 pin for determining whether the NAND is ready or not. This only works if all NAND chips are connected to WAIT0. If some chips are connected to the other available pin WAIT1, nand_wait() does not really wait and prints a WARN_ON message. This patch allows the board to provide configuration of which chip is connected to which WAITx signal. For example, one can define in include/configs/foo.h: #define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1 This would mean that chips using to CS0 and 1 are connected to WAIT0 and chips with CS2 and 3 are connected to WAIT1. Signed-off-by: Michal Sojka <sojka(a)merica.cz> Acked-by: Stefan Roese <sr(a)denx.de> Tested-by: Michal Vokáč <michal.vokac(a)comap.cz> Cc: Tom Rini <trini(a)ti.com> --- drivers/mtd/nand/omap_gpmc.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index fc64f48..8ba6550 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -30,13 +30,22 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, static uint8_t cs_next; static __maybe_unused struct nand_ecclayout omap_ecclayout; +#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG) +static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] = + { CONFIG_NAND_OMAP_GPMC_WSCFG }; +#else +/* wscfg is preset to zero since its a static variable */ +static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE]; +#endif + /* * Driver configurations */ struct omap_nand_info { struct bch_control *control; enum omap_ecc ecc_scheme; - int cs; + uint8_t cs; + uint8_t ws; /* wait status pin (0,1) */ }; /* We are wasting a bit of memory but al least we are safe */ @@ -76,7 +85,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, /* Check wait pin as dev ready indicator */ static int omap_dev_ready(struct mtd_info *mtd) { - return gpmc_cfg->status & (1 << 8); + register struct nand_chip *this = mtd->priv; + struct omap_nand_info *info = this->priv; + return gpmc_cfg->status & (1 << (8 + info->ws)); } /* @@ -962,6 +973,7 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; omap_nand_info[cs].control = NULL; omap_nand_info[cs].cs = cs; + omap_nand_info[cs].ws = wscfg[cs]; nand->priv = &omap_nand_info[cs]; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; -- 2.1.4

2 1

[U-Boot] [PATCH] fs: ext4 write: return file len on success
by Przemyslaw Marczak 06 Mar '15

06 Mar '15

After rework of the file system API, the size of ext4 write was missed. This causes printing unreliable write size at the end of the file system write operation. Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> Cc: Sjoerd Simons <sjoerd.simons(a)collabora.co.uk> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Simon Glass <sjg(a)chromium.org> --- fs/ext4/ext4_write.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index f7c52cc..fbc4c4b 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -1000,10 +1000,13 @@ int ext4_write_file(const char *filename, void *buf, loff_t offset, } ext4fs_close(); + *actwrite = len; + return 0; fail: ext4fs_close(); + *actwrite = 0; return -1; } -- 1.9.1

3 3

[U-Boot] [PATCH] vexpress64: juno: support SMC9118 ethernet
by Linus Walleij 06 Mar '15

06 Mar '15

This configures the Juno board to enable ethernet using the SMSC9118 ethernet controller found in the board. Tested by TFTP-booting a kernel over ethernet. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- board/armltd/vexpress64/vexpress64.c | 3 +++ include/configs/vexpress_aemv8a.h | 12 ++++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 7ab000cca77b..de6286435d97 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -137,5 +137,8 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif return rc; } diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index e276fff7e442..5ffc84dc5ecd 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -138,9 +138,17 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) -/* SMSC91C111 Ethernet Configuration */ +/* Ethernet Configuration */ +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +/* The real hardware Versatile express uses SMSC9118 */ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT 1 +#define CONFIG_SMC911X_BASE (0x018000000) +#else +/* The Vexpress64 simulators use SMSC91C111 */ #define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE (0x01A000000) +#endif /* PL011 Serial Configuration */ #define CONFIG_PL011_SERIAL @@ -229,7 +237,7 @@ "fdt_addr_r=0x83000000\0" \ "fdt_high=0xa0000000\0" -#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0" #define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \ "$initrd_addr_r:$initrd_size $fdt_addr_r" #define CONFIG_BOOTDELAY -1 -- 1.9.3

2 1

[U-Boot] [PATCH 2/3] m68k: add mcf5307 cpu support
by Angelo Dureghello 06 Mar '15

06 Mar '15

Add Freescale MCF5307 cpu support. Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- arch/m68k/cpu/mcf530x/Makefile | 9 ++ arch/m68k/cpu/mcf530x/config.mk | 12 ++ arch/m68k/cpu/mcf530x/cpu.c | 36 ++++++ arch/m68k/cpu/mcf530x/cpu_init.c | 160 +++++++++++++++++++++++ arch/m68k/cpu/mcf530x/interrupts.c | 29 +++++ arch/m68k/cpu/mcf530x/speed.c | 23 ++++ arch/m68k/cpu/mcf530x/start.S | 257 +++++++++++++++++++++++++++++++++++++ arch/m68k/include/asm/cache.h | 3 +- arch/m68k/include/asm/immap.h | 24 ++++ arch/m68k/include/asm/immap_5307.h | 118 +++++++++++++++++ arch/m68k/include/asm/m5307.h | 70 ++++++++++ arch/m68k/include/asm/timer.h | 3 +- 12 files changed, 742 insertions(+), 2 deletions(-) create mode 100644 arch/m68k/cpu/mcf530x/Makefile create mode 100644 arch/m68k/cpu/mcf530x/config.mk create mode 100644 arch/m68k/cpu/mcf530x/cpu.c create mode 100644 arch/m68k/cpu/mcf530x/cpu_init.c create mode 100644 arch/m68k/cpu/mcf530x/interrupts.c create mode 100644 arch/m68k/cpu/mcf530x/speed.c create mode 100644 arch/m68k/cpu/mcf530x/start.S create mode 100644 arch/m68k/include/asm/immap_5307.h create mode 100644 arch/m68k/include/asm/m5307.h diff --git a/arch/m68k/cpu/mcf530x/Makefile b/arch/m68k/cpu/mcf530x/Makefile new file mode 100644 index 0000000..9492bde --- /dev/null +++ b/arch/m68k/cpu/mcf530x/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y = start.o +obj-y = interrupts.o cpu.o speed.o cpu_init.o + diff --git a/arch/m68k/cpu/mcf530x/config.mk b/arch/m68k/cpu/mcf530x/config.mk new file mode 100644 index 0000000..aef72d7 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/config.mk @@ -0,0 +1,12 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h +is5307:=$(shell grep CONFIG_M5307 $(cfg)) + +ifneq (,$(findstring CONFIG_M5307,$(is5307))) +PLATFORM_CPPFLAGS += -mcpu=5307 +endif diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c new file mode 100644 index 0000000..78f4385 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <asm/immap.h> +#include <asm/io.h> + +#ifdef CONFIG_M5307 +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + sim_t *sim = (sim_t *)(MMAP_SIM); + + /* enable watchdog/reset, set timeout to 0 and wait */ + out_8(&sim->sypcr, SYPCR_SWE | SYPCR_SWRI); + + /* wait for watchdog reset */ + for (;;) + ; + + /* we don't return! */ + return 0; +} + +int checkcpu(void) +{ + char buf[32]; + + printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n", + strmhz(buf, CONFIG_SYS_CPU_CLK)); + return 0; +} +#endif diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c new file mode 100644 index 0000000..80dc239 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/immap.h> +#include <asm/io.h> + +#if defined(CONFIG_M5307) +/* + * Simple mcf5307 chip select module init. + * + * Note: this chip has an issue reported in the device "errata": + * MCF5307ER Rev 4.2 reports @ section 35: + * Corrupted Return PC in Exception Stack Frame + * When processing an autovectored interrupt an error can occur that + * causes 0xFFFFFFFF to be written as the return PC value in the + * exception stack frame. The problem is caused by a conflict between + * an internal autovector access and a chip select mapped to the IACK + * address space (0xFFFFXXXX). + * Workaround: + * Set the C/I bit in the chip select mask register (CSMR) for the + * chip select that is mapped to 0xFFFFXXXX. + * This will prevent the chip select from asserting for IACK accesses. + */ + +#define MCF5307_SP_ERR_FIX(cs_base, mask) \ + do { \ + if (((cs_base<<16)+(in_be32(&mask)&0xffff0000)) >= \ + 0xffff0000) \ + setbits_be32(&mask, CSMR_CI); \ + } while (0) + +void init_csm(void) +{ + csm_t *csm = (csm_t *)(MMAP_CSM); + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \ + defined(CONFIG_SYS_CS0_CTRL)) + out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK); + out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0); +#else +#warning "Chip Select 0 are not initialized/used" +#endif +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \ + defined(CONFIG_SYS_CS1_CTRL)) + out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK); + out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1); +#endif +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \ + defined(CONFIG_SYS_CS2_CTRL)) + out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK); + out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2); +#endif +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \ + defined(CONFIG_SYS_CS3_CTRL)) + out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK); + out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3); +#endif +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \ + defined(CONFIG_SYS_CS4_CTRL)) + out_be16(&csm->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&csm->csmr4, CONFIG_SYS_CS4_MASK); + out_be16(&csm->cscr4, CONFIG_SYS_CS4_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE, csm->csmr4); +#endif +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && \ + defined(CONFIG_SYS_CS5_CTRL)) + out_be16(&csm->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&csm->csmr5, CONFIG_SYS_CS5_MASK); + out_be16(&csm->cscr5, CONFIG_SYS_CS5_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE, csm->csmr5); +#endif +#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && \ + defined(CONFIG_SYS_CS6_CTRL)) + out_be16(&csm->csar6, CONFIG_SYS_CS6_BASE); + out_be32(&csm->csmr6, CONFIG_SYS_CS6_MASK); + out_be16(&csm->cscr6, CONFIG_SYS_CS6_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE, csm->csmr6); +#endif +#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && \ + defined(CONFIG_SYS_CS7_CTRL)) + out_be16(&csm->csar7, CONFIG_SYS_CS7_BASE); + out_be32(&csm->csmr7, CONFIG_SYS_CS7_MASK); + out_be16(&csm->cscr7, CONFIG_SYS_CS7_CTRL); + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE, csm->csmr7); +#endif +} + +/* + * Set up the memory map and initialize registers + */ +void cpu_init_f(void) +{ + sim_t *sim = (sim_t *)(MMAP_SIM); + + out_8(&sim->sypcr, 0x00); + out_8(&sim->swivr, 0x0f); + out_8(&sim->swsr, 0x00); + out_8(&sim->mpark, 0x00); + + intctrl_t *icr = (intctrl_t *)(MMAP_INTC); + + /* timer 2 not masked */ + out_be32(&icr->imr, 0xfffffbff); + + out_8(&icr->icr0, 0x00); /* sw watchdog */ + out_8(&icr->icr1, 0x00); /* timer 1 */ + out_8(&icr->icr2, 0x88); /* timer 2 */ + out_8(&icr->icr3, 0x00); /* i2c */ + out_8(&icr->icr4, 0x00); /* uart 0 */ + out_8(&icr->icr5, 0x00); /* uart 1 */ + out_8(&icr->icr6, 0x00); /* dma 0 */ + out_8(&icr->icr7, 0x00); /* dma 1 */ + out_8(&icr->icr8, 0x00); /* dma 2 */ + out_8(&icr->icr9, 0x00); /* dma 3 */ + + /* Chipselect Init */ + init_csm(); + + /* enable data/instruction cache now */ + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return 0; +} + +void uart_port_conf(void) +{ +} + +void arch_preboot_os(void) +{ + /* + * OS can change interrupt offsets and are about to boot the OS so + * we need to make sure we disable all async interrupts. + */ + intctrl_t *icr = (intctrl_t *)(MMAP_INTC); + + out_8(&icr->icr1, 0x00); /* timer 1 */ + out_8(&icr->icr2, 0x00); /* timer 2 */ +} +#endif diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c new file mode 100644 index 0000000..bf4038d --- /dev/null +++ b/arch/m68k/cpu/mcf530x/interrupts.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <asm/immap.h> +#include <asm/io.h> + +#ifdef CONFIG_M5307 +int interrupt_init(void) +{ + enable_interrupts(); + + return 0; +} + +void dtimer_intr_setup(void) +{ + intctrl_t *icr = (intctrl_t *)(MMAP_INTC); + + /* clearing TIMER2 mask, so enabling the related interrupt */ + out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400); + /* set TIMER2 interrupt priority */ + out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI); +} +#endif diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c new file mode 100644 index 0000000..3cf1986 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ +int get_clocks(void) +{ +#if defined(CONFIG_M5307) + gd->bus_clk = CONFIG_SYS_CLK; + gd->cpu_clk = CONFIG_SYS_CPU_CLK; +#endif + + return 0; +} diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S new file mode 100644 index 0000000..097958a --- /dev/null +++ b/arch/m68k/cpu/mcf530x/start.S @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2015 Angelo Dureghello <angelo(a)sysam.it> + * Based on code from Bernhard Kuhn <bkuhn(a)metrowerks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include "version.h" +#include <asm/cache.h> + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + + +.macro SAVE_ALL + move.w #0x2700,%sr; /* disable intrs */ + subl #60,%sp; /* space for 15 regs */ + moveml %d0-%d7/%a0-%a6,%sp@ +.endm + +.macro RESTORE_ALL + moveml %sp@,%d0-%d7/%a0-%a6; + addl #60,%sp; /* space for 15 regs */ + rte +.endm + +/* If we come from a pre-loader we don't need an initial exception + * table. + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +/* Flash offset is 0 until we setup CS0 */ +.long 0x00000000 +#if defined(CONFIG_M5307) && \ + (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +.long _start - CONFIG_SYS_TEXT_BASE +#else +.long _START +#endif + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +#endif + + .text + .globl _start +_start: + nop + nop + move.w #0x2700,%sr + + /* set MBAR address + valid flag */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.c %d0, %MBAR + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.c %d0, %RAMBAR + + /* DS 4.8.2 (Cache Organization) invalidate and disable cache */ + move.l #CF_CACR_CINVA, %d0 + movec %d0, %CACR + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* + * if we come from a pre-loader we have no exception table and + * therefore no VBR to set + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + move.l #CONFIG_SYS_FLASH_BASE, %d0 + movec %d0, %VBR +#endif + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* + * set stackpointer to internal sram end - 80 + * (global data struct size + some bytes) + * get some stackspace for the first c-code, + */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + /* put relocation table address to a5 */ + move.l #__got_start, %a5 + + /* run low-level CPU init code (from flash) */ + bsr cpu_init_f + + /* run low-level board init code (from flash) */ + bsr board_init_f + + /* board_init_f() does not return */ + +/*--------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE), %a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE), %d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE), %a1 + /* * fix got pointer register a5 */ + move.l %a1,%a5 + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE), %a2 + +7: + move.l (%a1),%d1 + sub.l #_start, %d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ +#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \ + defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) + halt +#endif + jsr (%a1) + +/*--------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + bra _fault + + .globl _exc_handler +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*--------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 59fa33b..812f25c 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -15,7 +15,8 @@ #define CONFIG_CF_V2 #endif -#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) +#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \ + defined(CONFIG_MCF5301x) #define CONFIG_CF_V3 #endif diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index f0a76f4..aca5f3a 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -240,6 +240,30 @@ #endif #endif /* CONFIG_M5282 */ +#ifdef CONFIG_M5307 +#include <asm/immap_5307.h> +#include <asm/m5307.h> + +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC) +#define CONFIG_SYS_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \ + (CONFIG_SYS_INTR_BASE))->ipr) +#define CONFIG_SYS_TMRINTR_NO (31) +#define CONFIG_SYS_TMRINTR_MASK (0x00000400) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \ + MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif +#endif /* CONFIG_M5307 */ + #if defined(CONFIG_MCF5301x) #include <asm/immap_5301x.h> #include <asm/m5301x.h> diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h new file mode 100644 index 0000000..c839f46 --- /dev/null +++ b/arch/m68k/include/asm/immap_5307.h @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __IMMAP_5307__ +#define __IMMAP_5307__ + +#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244) + +typedef struct sim { + u8 rsr; + u8 sypcr; + u8 swivr; + u8 swsr; + u16 par; + u8 irqpar; + u8 res1; + u8 pllcr; + u8 res2; + u16 res3; + u8 mpark; + u8 res4; + u16 res5; + u32 res6; +} sim_t; + +typedef struct intctrl { + u32 ipr; + u32 imr; + u16 res7; + u8 res8; + u8 avr; + u8 icr0; + u8 icr1; + u8 icr2; + u8 icr3; + u8 icr4; + u8 icr5; + u8 icr6; + u8 icr7; + u8 icr8; + u8 icr9; + u16 res9; +} intctrl_t; + +typedef struct csm { + u16 csar0; /* Chip-select Address */ + u16 res1; + u32 csmr0; /* Chip-select Mask */ + u16 res2; + u16 cscr0; /* Chip-select Control */ + u16 csar1; + u16 res3; + u32 csmr1; + u16 res4; + u16 cscr1; + u16 csar2; + u16 res5; + u32 csmr2; + u16 res6; + u16 cscr2; + u16 csar3; + u16 res7; + u32 csmr3; + u16 res8; + u16 cscr3; + u16 csar4; + u16 res9; + u32 csmr4; + u16 res10; + u16 cscr4; + u16 csar5; + u16 res11; + u32 csmr5; + u16 res12; + u16 cscr5; + u16 csar6; + u16 res13; + u32 csmr6; + u16 res14; + u16 cscr6; + u16 csar7; + u16 res15; + u32 csmr7; + u16 res16; + u16 cscr7; +} csm_t; + +typedef struct sdramctrl { + u16 dcr; + u16 res1; + u32 res2; + u32 dacr0; + u32 dmr0; + u32 dacr1; + u32 dmr1; +} sdramctrl_t; + +typedef struct gpio { + u16 paddr; + u16 res1; + u16 padat; + u16 res2; +} gpio_t; + +#endif /* __IMMAP_5307__ */ + diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h new file mode 100644 index 0000000..8192c46 --- /dev/null +++ b/arch/m68k/include/asm/m5307.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef mcf5307_h +#define mcf5307_h + +/* + * Size of internal RAM (RAMBAR) + */ +#define INT_RAM_SIZE 4096 + +/* Bit definitions and macros for SYPCR */ +#define SYPCR_SWTAVAL 0x02 +#define SYPCR_SWTA 0x04 +#define SYPCR_SWT(x) ((x&0x3)<<3) +#define SYPCR_SWP 0x20 +#define SYPCR_SWRI 0x40 +#define SYPCR_SWE 0x80 + +/* Bit definitions and macros for CSMR */ +#define CSMR_V 0x01 +#define CSMR_UD 0x02 +#define CSMR_UC 0x04 +#define CSMR_SD 0x08 +#define CSMR_SC 0x10 +#define CSMR_CI 0x20 +#define CSMR_AM 0x40 +#define CSMR_WP 0x100 + +/* Bit definitions and macros for DACR (SDRAM) */ +#define DACR_PM_CONTINUOUS 0x04 +#define DACR_IP_PRECHG_ALL 0x08 +#define DACR_PORT_SZ_32 0 +#define DACR_PORT_SZ_8 (1<<4) +#define DACR_PORT_SZ_16 (2<<4) +#define DACR_IMRS_INIT_CMD (1<<6) +#define DACR_CMD_PIN(x) ((x&7)<<8) +#define DACR_CASL(x) ((x&3)<<12) +#define DACR_RE (1<<15) + +/* Bit definitions and macros for CSCR */ +#define CSCR_BSTW 0x08 +#define CSCR_BSTR 0x10 +#define CSCR_BEM 0x20 +#define CSCR_PS(x) ((x&0x3)<<6) +#define CSCR_AA 0x100 +#define CSCR_WS ((x&0xf)<<10) + +/* Bit definitions for the ICR family of registers */ +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ + +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ + +#endif /* mcf5307_h */ + diff --git a/arch/m68k/include/asm/timer.h b/arch/m68k/include/asm/timer.h index 2bdaddc..8fb3216 100644 --- a/arch/m68k/include/asm/timer.h +++ b/arch/m68k/include/asm/timer.h @@ -17,7 +17,8 @@ /****************************************************************************/ /* DMA Timer module registers */ typedef struct dtimer_ctrl { -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272) +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ + defined(CONFIG_M5272) || defined(CONFIG_M5307) u16 tmr; /* 0x00 Mode register */ u16 res1; /* 0x02 */ u16 trr; /* 0x04 Reference register */ -- 2.1.4

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by Tom Rini 06 Mar '15

06 Mar '15

1 0