March 2015 - U-Boot

[U-Boot] [PATCH v4 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
by Albert ARIBAUD (3ADEV) 12 Mar '15

12 Mar '15

This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: A - I2C driver remains non-DM During v2 review, it was suggested to move to DM for I2C. However, this caused issues with the 'date', 'dtt' and 'eeprom' commands which are configured in this board. Therefore the I2C move to DM was not done. B - Some checkpatch diagnostics are not fixed The following warnings checkpatch warnings and checks were not fixed: 1. "warning: arch/arm/Kconfig,135: please write a paragraph that describes the config symbol fully" Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. "check: include/configs/work_92105.h,185: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v4: - remove two debugging statements - add __iomem to regs struct - remove useless 'else return;' - take BB marker out of free OOB area - replace magic numbers in OOB reads/writes - add timeouts in NAND loops - use DIV_ROUND_UP where applicable - fix erroneous comment - skip bad blocks in SPL chainload loop Changes in v3: - move DM dependency constraint into Kconfig - move regs pointer and function cache into private struct - discourage readers from using functions implementation as an example - move regs and functions in private struct - remove script/Makefile.spl change - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 Makefile | 20 + arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile | 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h | 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h | 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h | 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig | 15 + board/work-microwave/work_92105/MAINTAINERS | 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 +++ board/work-microwave/work_92105/work_92105.c | 62 ++ .../work-microwave/work_92105/work_92105_display.c | 349 +++++++++++ .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 ++ common/image.c | 1 + configs/work_92105_defconfig | 5 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c | 293 ++++++++++ drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 +++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 ++++++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c | 644 +++++++++++++++++++++ drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 636 ++++++++++++++++++++ drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 144 +++++ include/configs/work_92105.h | 266 +++++++++ include/dtt.h | 15 +- include/image.h | 1 + include/netdev.h | 1 + tools/Makefile | 1 + tools/lpc32xximage.c | 178 ++++++ 43 files changed, 3417 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 board/work-microwave/work_92105/work_92105_spl.c create mode 100644 configs/work_92105_defconfig create mode 100644 drivers/gpio/lpc32xx_gpio.c create mode 100644 drivers/hwmon/ds620.c create mode 100644 drivers/i2c/lpc32xx_i2c.c create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c create mode 100644 drivers/net/lpc32xx_eth.c create mode 100644 drivers/spi/lpc32xx_ssp.c create mode 100644 include/configs/work_92105.h create mode 100644 tools/lpc32xximage.c -- 2.1.0

2 9

[U-Boot] [PATCH] powerpc/t1023rdb: add ddr support for t1023rdb
by Shengzhou Liu 12 Mar '15

12 Mar '15

Tested on the discrete DDR4 MT40A512M8HX with raw timing on T1023RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- board/freescale/t102xrdb/ddr.c | 78 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index a2a8f4c..adf9fd5 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -135,8 +135,83 @@ found: /* for DDR bus 32bit test on T1024 */ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; #endif + +#ifdef CONFIG_T1023RDB + popts->wrlvl_ctl_2 = 0x07070606; + popts->half_strength_driver_enable = 1; +#endif } +#ifdef CONFIG_SYS_DDR_RAW_TIMING +/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 0x80000000, + .capacity = 0x80000000, + .primary_sdram_width = 32, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .bank_addr_bits = 2, + .bank_group_bits = 2, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 938, + .tckmax_ps = 1500, + .caslat_x = 0x000DFA00, + .taa_ps = 13500, + .trcd_ps = 13500, + .trp_ps = 13500, + .tras_ps = 33000, + .trc_ps = 46500, + .trfc1_ps = 260000, + .trfc2_ps = 160000, + .trfc4_ps = 110000, + .tfaw_ps = 25000, + .trrds_ps = 3700, + .trrdl_ps = 5300, + .tccdl_ps = 5355, + .refresh_rate_ps = 7800000, + .dq_mapping[0] = 0x0, + .dq_mapping[1] = 0x0, + .dq_mapping[2] = 0x0, + .dq_mapping[3] = 0x0, + .dq_mapping[4] = 0x0, + .dq_mapping[5] = 0x0, + .dq_mapping[6] = 0x0, + .dq_mapping[7] = 0x0, + .dq_mapping[8] = 0x0, + .dq_mapping[9] = 0x0, + .dq_mapping[10] = 0x0, + .dq_mapping[11] = 0x0, + .dq_mapping[12] = 0x0, + .dq_mapping[13] = 0x0, + .dq_mapping[14] = 0x0, + .dq_mapping[15] = 0x0, + .dq_mapping[16] = 0x0, + .dq_mapping[17] = 0x0, + .dq_mapping_ors = 1, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR4 on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif + #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void) { @@ -155,8 +230,9 @@ phys_size_t initdram(int board_type) phys_size_t dram_size; #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) +#ifndef CONFIG_SYS_DDR_RAW_TIMING puts("Initializing....using SPD\n"); - +#endif dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; -- 2.1.0.27.g96db324

2 1

[U-Boot] 4K padding of ARM DT blob
by Yehuda Yitschak 12 Mar '15

12 Mar '15

Hello I was wondering why the default ARM device tree blob is padded by 4K bytes Is this required to align to some storage medium ? Is there a configuration that allows to eliminate this padding to save space ? Thanks ________________________________ Yehuda Yitschak Marvell Israel - SW Engineer 6 Hamada Street Mordot HaCarmel Industrial Park Yokneam, 20692, Israel Email: yehuday(a)marvell.com<mailto:yehuday@marvell.com> Office: +972.4.9091717 Fax: +972.4.9091501 Web site: http://www.marvell.com<http://www.marvell.com/> This message may contain confidential, proprietary or legally privileged information. The information is intended only for the use of the individual or entity named above. If the reader of this message is not the intended recipient, you are hereby notified that any dissemination, distribution or copying of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by telephone or by e-mail and delete the message from your computer. ________________________________

4 11

Re: [U-Boot] "Writing to MMC(%d)... failed"
by Przemyslaw Marczak 12 Mar '15

12 Mar '15

Hello Nathan, On 03/10/2015 12:30 PM, Nathan wrote: > I hope my last message didn't get lost during that outage last month. > > In the mean time, I had to finagle the HardKernel code to work with > GCC 5.0 which ended up being only 1 line change which I may end up > encountering in mainline if I ever get far enough. > After transferring the "CONFIG_MMC_TRACE" to the HardKernel mmc.c, I > have a comparable output for the U2 with the "Samsung" mainline. > > So the output comparison can be made more readable, I created a Google > Drive Sheet, lining up the output when there were repeats, > highlighting the differing output sections and changing the text color > for the different values: > https://docs.google.com/spreadsheets/d/1Gu10bG8wGJClorJjKoIMiAt4HR0nS22ugrL… > Now, I don't have too much time for this, but the only one you need is the documentation and a time to analyze the responds for commands. Please check this site: https://www.sdcard.org/downloads/pls/simplified_specs/index.html you can also check some example spec from Jedec: http://www.jedec.org/standards-documents/results/jesd84-a441 You will solve this problem with this. By the way, did you tried another SD-Card? Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marczak(a)samsung.com

2 3

[U-Boot] [PATCH v2] autoboot.c: Add feature to stop autobooting via SHA256 encrypted password
by Stefan Roese 12 Mar '15

12 Mar '15

This patch adds the feature to only stop the autobooting, and therefor boot into the U-Boot prompt, when the input string / password matches a values that is encypted via a SHA256 hash and saved in the environment. This feature is enabled by defined these config options: CONFIG_AUTOBOOT_KEYED CONFIG_AUTOBOOT_STOP_STR_SHA256 Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- v2: - Extracted the passwd checking functions (sha256 and non-sha256) into passwd_abort(). Resulting in an easier to read code with less #ifdef's. common/autoboot.c | 90 +++++++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 74 insertions(+), 16 deletions(-) diff --git a/common/autoboot.c b/common/autoboot.c index c27cc2c..def1612 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -12,6 +12,7 @@ #include <fdtdec.h> #include <menu.h> #include <post.h> +#include <u-boot/sha256.h> DECLARE_GLOBAL_DATA_PTR; @@ -26,15 +27,58 @@ DECLARE_GLOBAL_DATA_PTR; /* Stored value of bootdelay, used by autoboot_command() */ static int stored_bootdelay; -/*************************************************************************** - * Watch for 'delay' seconds for autoboot stop or autoboot delay string. - * returns: 0 - no key string, allow autoboot 1 - got key string, abort - */ -# if defined(CONFIG_AUTOBOOT_KEYED) -static int abortboot_keyed(int bootdelay) +#if defined(CONFIG_AUTOBOOT_KEYED) +#if defined(CONFIG_AUTOBOOT_STOP_STR_SHA256) +static int passwd_abort(uint64_t etime) +{ + const char *sha_env_str = getenv("bootstopkeysha256"); + u8 sha_env[SHA256_SUM_LEN]; + u8 sha[SHA256_SUM_LEN]; + char presskey[MAX_DELAY_STOP_STR]; + u_int presskey_len = 0; + int i; + int abort = 0; + + if (sha_env_str == NULL) + sha_env_str = CONFIG_AUTOBOOT_STOP_STR_SHA256; + + /* + * Generate the binary value from the environment hash value + * so that we can compare this value with the computed hash + * from the user input + */ + for (i = 0; i < SHA256_SUM_LEN; i++) { + char chr[3]; + + strncpy(chr, &sha_env_str[i * 2], 2); + sha_env[i] = simple_strtoul(chr, NULL, 16); + } + + /* + * We don't know how long the stop-string is, so we need to + * generate the sha256 hash upon each input character and + * compare the value with the one saved in the environment + */ + do { + if (tstc()) { + presskey[presskey_len++] = getc(); + + /* Calculate sha256 upon each new char */ + sha256_csum_wd((unsigned char *)presskey, presskey_len, + sha, CHUNKSZ_SHA256); + + /* And check if sha matches saved value in env */ + if (memcmp(sha, sha_env, SHA256_SUM_LEN) == 0) + abort = 1; + } + } while (!abort && get_ticks() <= etime); + + return abort; +} +#else +static int passwd_abort(uint64_t etime) { int abort = 0; - uint64_t etime = endtick(bootdelay); struct { char *str; u_int len; @@ -52,15 +96,6 @@ static int abortboot_keyed(int bootdelay) u_int presskey_max = 0; u_int i; -#ifndef CONFIG_ZERO_BOOTDELAY_CHECK - if (bootdelay == 0) - return 0; -#endif - -# ifdef CONFIG_AUTOBOOT_PROMPT - printf(CONFIG_AUTOBOOT_PROMPT); -# endif - # ifdef CONFIG_AUTOBOOT_DELAY_STR if (delaykey[0].str == NULL) delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR; @@ -125,6 +160,29 @@ static int abortboot_keyed(int bootdelay) } } while (!abort && get_ticks() <= etime); + return abort; +} +#endif + +/*************************************************************************** + * Watch for 'delay' seconds for autoboot stop or autoboot delay string. + * returns: 0 - no key string, allow autoboot 1 - got key string, abort + */ +static int abortboot_keyed(int bootdelay) +{ + int abort; + uint64_t etime = endtick(bootdelay); + +#ifndef CONFIG_ZERO_BOOTDELAY_CHECK + if (bootdelay == 0) + return 0; +#endif + +# ifdef CONFIG_AUTOBOOT_PROMPT + printf(CONFIG_AUTOBOOT_PROMPT); +# endif + + abort = passwd_abort(etime); if (!abort) debug_bootkeys("key timeout\n"); -- 2.3.2

1 0

[U-Boot] [RFC PATCH] PMIC: add act8865 series support
by Bo Shen 12 Mar '15

12 Mar '15

Add Active-Semi act8865 series PMU support. Signed-off-by: Bo Shen <voice.shen(a)atmel.com> --- drivers/power/Makefile | 1 + drivers/power/act8865.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++++ include/act8865.h | 54 +++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/power/act8865.c create mode 100644 include/act8865.h diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 2145652..0c2a8cf 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_ACT8865_POWER) += act8865.o obj-$(CONFIG_AS3722_POWER) += as3722.o obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o diff --git a/drivers/power/act8865.c b/drivers/power/act8865.c new file mode 100644 index 0000000..c36f7bd --- /dev/null +++ b/drivers/power/act8865.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Bo Shen <voice.shen(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <act8865.h> + +static int act8865_read(u32 reg, uchar *val) +{ + return i2c_read(ACT8865_I2C_ADDR, reg, 1, val, 1); +} + +static int act8865_write(u32 reg, uchar val) +{ + return i2c_write(ACT8865_I2C_ADDR, reg, 1, &val, 1); +} + +int act8865_disable_i2c_interface(void) +{ + uchar val; + + /* Check the I2C interface is disabled or not */ + if (act8865_read(ACT8865_SYS_CONTROL0, &val)) { + debug("ACT8865: i2c interface has been disabled\n"); + return 0; + } + + /* + * As the ACT8865 don't have ID register, so we try one by one + * to disable the exist chips (303, 304, 305) in this series. + */ + + /* Try to disable ACT8865QI303 */ + act8865_write(0x0B, 0xE9); + act8865_write(0x02, 0x07); + if (act8865_write(0x03, 0x01)) { + debug("ACT8865: subtype 303 has been disabled\n"); + return 0; + } + + /* Try to disable ACT8865QI304 */ + act8865_write(0x0B, 0xEE); + act8865_write(0x02, 0x07); + if (act8865_write(0x03, 0x01)) { + debug("ACT8865: subtype 304 has been disabled\n"); + return 0; + } + + /* Try to disable ACT8865QI305 */ + act8865_write(0x0B, 0xEE); + act8865_write(0x02, 0x07); + if (act8865_write(0x03, 0x01)) { + debug("ACT8865: subtype 305 has been disabled\n"); + return 0; + } + + debug("ACT8865: the chip can not be disabled\n"); + + return 0; +} + +int act8865_enable_ldo_output(enum act8865_ldo ldo, enum act8865_volt volt) +{ + u32 conf_reg, ctrl_reg; + uchar val; + + switch (ldo) { + case ACT8865_LDO_REG4: + conf_reg = ACT8865_REG4_CONFIG0; + ctrl_reg = ACT8865_REG4_CONTROL; + break; + + case ACT8865_LDO_REG5: + conf_reg = ACT8865_REG5_CONFIG0; + ctrl_reg = ACT8865_REG5_CONTROL; + break; + + case ACT8865_LDO_REG6: + conf_reg = ACT8865_REG6_CONFIG0; + ctrl_reg = ACT8865_REG6_CONTROL; + break; + + case ACT8865_LDO_REG7: + conf_reg = ACT8865_REG7_CONFIG0; + ctrl_reg = ACT8865_REG7_CONTROL; + break; + default: + error("ACT8865: unsupported LDO\n"); + return -1; + } + + /* Set the LDO output voltage */ + act8865_write(conf_reg, 0x18); + /* Enable the LDO */ + act8865_read(ctrl_reg, &val); + val |= ACT8865_OUTPUT_ENABLE; + act8865_write(ctrl_reg, val); + + return 0; +} diff --git a/include/act8865.h b/include/act8865.h new file mode 100644 index 0000000..f6053ac --- /dev/null +++ b/include/act8865.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Bo Shen <voice.shen(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define ACT8865_SYS_CONTROL0 0x00 +#define ACT8865_SYS_CONTROL1 0x01 + +#define ACT8865_REG1_CONFIG0 0x20 +#define ACT8865_REG1_CONFIG1 0x21 +#define ACT8865_REG1_CONTROL 0x22 + +#define ACT8865_REG2_CONFIG0 0x30 +#define ACT8865_REG2_CONFIG1 0x31 +#define ACT8865_REG2_CONTROL 0x32 + +#define ACT8865_REG3_CONFIG0 0x40 +#define ACT8865_REG3_CONFIG1 0x41 +#define ACT8865_REG3_CONTROL 0x42 + +#define ACT8865_REG4_CONFIG0 0x50 +#define ACT8865_REG4_CONTROL 0x51 + +#define ACT8865_REG5_CONFIG0 0x54 +#define ACT8865_REG5_CONTROL 0x55 + +#define ACT8865_REG6_CONFIG0 0x60 +#define ACT8865_REG6_CONTROL 0x61 + +#define ACT8865_REG7_CONFIG0 0x64 +#define ACT8865_REG7_CONTROL 0x65 + +#define ACT8865_OUTPUT_ENABLE (0x01 << 7) + +#define ACT8865_I2C_ADDR 0x5B + +enum act8865_ldo { + ACT8865_LDO_REG4 = 4, + ACT8865_LDO_REG5, + ACT8865_LDO_REG6, + ACT8865_LDO_REG7, +}; + +enum act8865_volt { + ACT8865_1V2_VOLT, + ACT8865_1V8_VOLT, + ACT8865_2V5_VOLT, + ACT8865_3V3_VOLT, +}; + +int act8865_enable_ldo_output(enum act8865_ldo ldo, enum act8865_volt volt); +int act8865_disable_i2c_interface(void); -- 2.3.0

1 0

[U-Boot] [PATCH] powerpc/t1023rdb: Add T1023 RDB board support
by Shengzhou Liu 12 Mar '15

12 Mar '15

T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. T1023RDB board Overview ----------------------- - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 without ECC - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - one 1G RGMII port on-board(RTL8211F PHY) - one 1G SGMII port on-board(RTL8211F PHY) - one 2.5G SGMII port on-board(AQR105 PHY) - PCIe: Two Mini-PCIe connectors on-board. - SerDes: 4 lanes up to 10.3125GHz - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. - USB: one Type-A USB 2.0 port with internal PHY - eSDHC: support SD/MMC and eMMC card - 256Kbit M24256 I2C EEPROM - RTC: Real-time clock DS1339 on I2C bus - UART: one serial port on-board with RJ45 connector - Debugging: JTAG/COP for T1023 debugging As well updated T1024RDB to add T1023RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- board/freescale/t102xrdb/Makefile | 2 +- board/freescale/t102xrdb/README | 89 +++++++++++++++++++++++++----- board/freescale/t102xrdb/eth_t102xrdb.c | 23 +++++++- board/freescale/t102xrdb/t1023_rcw.cfg | 8 +++ board/freescale/t102xrdb/t102xrdb.c | 98 +++++++++++++++++++++++++++++++-- board/freescale/t102xrdb/t102xrdb.h | 4 +- include/configs/T102xRDB.h | 73 ++++++++++++++++++++---- 7 files changed, 263 insertions(+), 34 deletions(-) create mode 100644 board/freescale/t102xrdb/t1023_rcw.cfg diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile index a0cf8f6..0520066 100644 --- a/board/freescale/t102xrdb/Makefile +++ b/board/freescale/t102xrdb/Makefile @@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += t102xrdb.o -obj-y += cpld.o +obj-$(CONFIG_T1024RDB) += cpld.o obj-y += eth_t102xrdb.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index 2b17f50..775de06 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -98,6 +98,29 @@ T1024RDB board Overview - Four I2C ports +T1023RDB board Overview +----------------------- +- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz +- CoreNet fabric supporting coherent and noncoherent transactions with + prioritization and bandwidth allocation +- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC +- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC +- Ethernet interfaces: + - one 1G RGMII port on-board(RTL8211FS PHY) + - one 1G SGMII port on-board(RTL8211FS PHY) + - one 2.5G SGMII port on-board(AQR105 PHY) +- PCIe: Two Mini-PCIe connectors on-board. +- SerDes: 4 lanes up to 10.3125GHz +- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash +- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash +- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. +- USB: one Type-A USB 2.0 port with internal PHY +- eSDHC: support SD/MMC and eMMC card +- 256Kbit M24256 I2C EEPROM +- RTC: Real-time clock DS1339U on I2C bus +- UART: one serial port on-board with RJ45 connector +- Debugging: JTAG/COP for T1023 debugging + Memory map on T1024RDB ---------------------- Start Address End Address Description Size @@ -124,22 +147,32 @@ Start Address End Address Definition Max size 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB -0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB +0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB +0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB +0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB +0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB -0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB +0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB -0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB +0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB +0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB +0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB +0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB -0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB 0xE8000000 0xE801FFFF RCW (current bank) 128KB -T1024 Clock frequency ---------------------- +T1024/T1023 Clock frequency +--------------------------- BIN Core DDR Platform FMan Bin1: 1400MHz 1600MT/s 400MHz 700MHz Bin2: 1200MHz 1600MT/s 400MHz 600MHz @@ -155,16 +188,27 @@ Software configurations and board settings b. program u-boot.bin image to NOR flash => tftp 1000000 u-boot.bin => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + on T1024RDB: + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + on T1023RDB: + set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot Switching between default bank0 and alternate bank4 on NOR flash To change boot source to vbank4: - via software: run command 'cpld reset altbank' in u-boot. - via DIP-switch: set SW3[5:7] = '100' + on T1024RDB: + via software: run command 'cpld reset altbank' in u-boot. + via DIP-switch: set SW3[5:7] = '100' + on T1023RDB: + via software: run command 'gpio vbank4' in u-boot. + via DIP-switch: set SW3[5:7] = '100' To change boot source to vbank0: - via software: run command 'cpld reset' in u-boot. - via DIP-Switch: set SW3[5:7] = '000' + on T1024RDB: + via software: run command 'cpld reset' in u-boot. + via DIP-Switch: set SW3[5:7] = '000' + on T1023RDB: + via software: run command 'gpio vbank0' in u-boot. + via DIP-switch: set SW3[5:7] = '000' 2. NAND Boot: a. build PBL image for NAND boot @@ -183,8 +227,11 @@ Software configurations and board settings b. program u-boot-with-spl-pbl.bin to SPI flash => tftp 1000000 u-boot-with-spl-pbl.bin => sf probe 0 - => sf erase 0 f0000 + => sf erase 0 100000 => sf write 1000000 0 $filesize + => tftp 1000000 fsl_fman_ucode_t1024_xx.bin + => sf erase 100000 100000 + => sf write 1000000 110000 20000 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 4. SD Boot: @@ -236,6 +283,15 @@ Start End Definition Size 0x200000 0x27FFFF QE Firmware 512KB(1 block) +NAND Flash memory Map on T1023RDB +------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x100000 0x15FFFF u-boot env 8KB +0x160000 0x17FFFF FMAN Ucode 128KB +0x180000 0x19FFFF QE Firmware 128KB + + SD Card memory Map on T1024RDB ---------------------------------------------------- Block #blocks Definition Size @@ -245,14 +301,17 @@ Block #blocks Definition Size 0x920 0256 QE Firmware 128KB -SPI Flash memory Map on T1024RDB +64MB SPI Flash memory Map on T1024RDB/T1023RDB ---------------------------------------------------- Start End Definition Size 0x000000 0x0FFFFF u-boot img 1MB 0x100000 0x101FFF u-boot env 8KB 0x110000 0x12FFFF FMAN Ucode 128KB 0x130000 0x14FFFF QE Firmware 128KB +0x300000 0x3FFFFF device tree 128KB +0x400000 0x9FFFFF Linux kernel 6MB +0xa00000 0x3FFFFFF rootfs 54MB -For more details, please refer to T1024RDB Reference Manual and access -website www.freescale.com and Freescale QorIQ SDK Infocenter document. +For more details, please refer to T1024RDB Reference Manual +and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index f611ff0..f091d75 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -56,6 +56,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); switch (srds_s1) { +#ifdef CONFIG_T1024RDB case 0x95: /* set the on-board RGMII2 PHY */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); @@ -63,10 +64,17 @@ int board_eth_init(bd_t *bis) /* set 10G XFI with Aquantia AQR105 PHY */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); break; +#endif + case 0x6a: + case 0x6b: case 0x77: case 0x135: /* set the on-board 2.5G SGMII AQR105 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); +#ifdef CONFIG_T1023RDB + /* set the on-board 1G SGMII RTL8211F PHY */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); +#endif break; default: printf("SerDes protocol 0x%x is not supported on T102xRDB\n", @@ -81,6 +89,14 @@ int board_eth_init(bd_t *bis) dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; + case PHY_INTERFACE_MODE_SGMII: +#if defined(CONFIG_T1023RDB) + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); +#elif defined(CONFIG_T1024RDB) + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); +#endif + fm_info_set_mdio(i, dev); + break; case PHY_INTERFACE_MODE_SGMII_2500: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(i, dev); @@ -110,8 +126,9 @@ int board_eth_init(bd_t *bis) void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { - if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) && - (port == FM1_DTSEC3)) { + if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || + (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && + (port == FM1_DTSEC3)) { fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); fdt_setprop(fdt, offset, "phy-connection-type", "sgmii-2500", 10); diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_rcw.cfg new file mode 100644 index 0000000..fa781d6 --- /dev/null +++ b/board/freescale/t102xrdb/t1023_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1023RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x77 +#Core/DDR: 1400Mhz/1600MT/s with single source clock +0810000e 00000000 00000000 00000000 +3b800003 00000012 e8104000 21000000 +00000000 00000000 00000000 00020800 +00000130 04020200 00000000 00000006 diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index e196f12..1841dea 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -18,11 +18,25 @@ #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t102xrdb.h" +#ifdef CONFIG_T1024RDB #include "cpld.h" +#endif #include "../common/sleep.h" DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_T1023RDB +enum { + GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */ + GPIO1_EMMC_SEL, + GPIO1_VBANK0, + GPIO1_VBANK4 = 0x00008000, /* GPIO1_16/20/22, 100:vBank4 */ + GPIO1_VBANK_MASK = 0x00008a00, + GPIO1_DIR_OUTPUT = 0x00028a00, + GPIO1_GET_VAL, +}; +#endif + int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; @@ -34,14 +48,17 @@ int checkboard(void) srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; printf("Board: %sRDB, ", cpu->name); - printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", +#ifdef CONFIG_T1024RDB + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", CPLD_READ(hw_ver), CPLD_READ(sw_ver)); +#endif + printf("boot from "); #ifdef CONFIG_SDCARD puts("SD/MMC\n"); #elif CONFIG_SPIFLASH puts("SPI\n"); -#else +#elif defined(CONFIG_T1024RDB) u8 reg; reg = CPLD_READ(flash_csr); @@ -52,17 +69,28 @@ int checkboard(void) reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); printf("NOR vBank%d\n", reg); } +#elif defined(CONFIG_T1023RDB) +#ifdef CONFIG_NAND + puts("NAND\n"); +#else + printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) & + GPIO1_VBANK4) >> 15 ? 4 : 0); +#endif #endif puts("SERDES Reference Clocks:\n"); +#if defined(CONFIG_T1024RDB) if (srds_s1 == 0x95) printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); else - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]); - + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[1], freq[0]); +#elif defined(CONFIG_T1023RDB) + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]); +#endif return 0; } +#ifdef CONFIG_T1024RDB static void board_mux_lane(void) { ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -82,6 +110,7 @@ static void board_mux_lane(void) } CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); } +#endif int board_early_init_f(void) { @@ -124,7 +153,9 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif +#ifdef CONFIG_T1024RDB board_mux_lane(); +#endif return 0; } @@ -170,3 +201,62 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + + +#ifdef CONFIG_T1023RDB +static u32 t1023rdb_gpio_ctrl(u32 ctrl_type) +{ + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + u32 gpioval; + + setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT); + gpioval = in_be32(&pgpio->gpdat); + + switch (ctrl_type) { + case GPIO1_SD_SEL: + gpioval |= GPIO1_SD_SEL; + break; + case GPIO1_EMMC_SEL: + gpioval &= ~GPIO1_SD_SEL; + break; + case GPIO1_VBANK0: + gpioval &= ~GPIO1_VBANK_MASK; + break; + case GPIO1_VBANK4: + gpioval &= ~GPIO1_VBANK_MASK; + gpioval |= GPIO1_VBANK4; + break; + case GPIO1_GET_VAL: + return gpioval; + default: + break; + } + out_be32(&pgpio->gpdat, gpioval); + + return 0; +} + +static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + if (!strcmp(argv[1], "vbank0")) + t1023rdb_gpio_ctrl(GPIO1_VBANK0); + else if (!strcmp(argv[1], "vbank4")) + t1023rdb_gpio_ctrl(GPIO1_VBANK4); + else if (!strcmp(argv[1], "sd")) + t1023rdb_gpio_ctrl(GPIO1_SD_SEL); + else if (!strcmp(argv[1], "EMMC")) + t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL); + else + return CMD_RET_USAGE; + return 0; +} + +U_BOOT_CMD( + gpio, 2, 0, gpio_cmd, + "for vbank0/vbank4/SD/eMMC switch control in runtime", + "command (e.g. gpio vbank4)" +); +#endif diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h index 2f23579..3f5d85a 100644 --- a/board/freescale/t102xrdb/t102xrdb.h +++ b/board/freescale/t102xrdb/t102xrdb.h @@ -9,5 +9,7 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); - +#ifdef CONFIG_T1023RDB +static u32 t1023rdb_gpio_ctrl(u32 ctrl_type); +#endif #endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index bd40d6a..af10163 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -11,6 +11,13 @@ #ifndef __T1024RDB_H #define __T1024RDB_H +#if defined(CONFIG_PPC_T1024) +#define CONFIG_T1024RDB +#elif defined(CONFIG_PPC_T1023) +#define CONFIG_T1023RDB +#define CONFIG_SYS_NO_FLASH +#endif + /* High Level Configuration Options */ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO @@ -35,7 +42,9 @@ #define CONFIG_ENV_OVERWRITE /* support deep sleep */ +#ifdef CONFIG_PPC_T1024 #define CONFIG_DEEP_SLEEP +#endif #if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE #define CONFIG_BOARD_EARLY_INIT_F @@ -43,7 +52,11 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg +#if defined(CONFIG_PPC_T1024) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg +#elif defined(CONFIG_PPC_T1023) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT @@ -177,7 +190,11 @@ #define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#if defined(CONFIG_T1024RDB) #define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_T1023RDB) +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC @@ -188,7 +205,11 @@ #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 +#if defined(CONFIG_T1024RDB) #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_T1023RDB) +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -209,7 +230,7 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 66660000 +#define CONFIG_DDR_CLK_FREQ 100000000 /* * These can be toggled for performance analysis, otherwise use default. @@ -224,6 +245,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif +#define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_ALT_MEMTEST @@ -265,13 +287,18 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_FSL_DDR_INTERACTIVE +#if defined(CONFIG_T1024RDB) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 - #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_SDRAM_SIZE 2048 +#endif /* * IFC Definitions @@ -291,7 +318,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) +#endif #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) @@ -315,6 +347,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#ifdef CONFIG_T1024RDB /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) @@ -336,6 +369,7 @@ unsigned long get_board_ddr_clk(void); FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 +#endif /* NAND Flash on IFC */ #define CONFIG_NAND_FSL_IFC @@ -352,6 +386,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -359,9 +394,17 @@ unsigned long get_board_ddr_clk(void); | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ + | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif #define CONFIG_SYS_NAND_ONFI_DETECTION - /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ @@ -382,8 +425,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) - #if defined(CONFIG_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -538,6 +579,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 10000000 @@ -737,8 +779,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -763,10 +810,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHYLIB_10G #define CONFIG_PHY_REALTEK #define CONFIG_PHY_AQUANTIA +#if defined(CONFIG_T1024RDB) #define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY2_ADDR 0x6 -#define SGMII_PHY1_ADDR 0x2 +#define SGMII_AQR_PHY_ADDR 0x2 #define FM1_10GEC1_PHY_ADDR 0x1 +#elif defined(CONFIG_T1023RDB) +#define RGMII_PHY1_ADDR 0x1 +#define SGMII_RTK_PHY_ADDR 0x3 +#define SGMII_AQR_PHY_ADDR 0x2 +#endif #endif #ifdef CONFIG_FMAN_ENET @@ -856,16 +909,16 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi #ifdef CONFIG_PPC_T1024 -#define CONFIG_BOARDNAME "t1024rdb" +#define CONFIG_BOARDNAME t1024rdb #else -#define CONFIG_BOARDNAME "t1023rdb" +#define CONFIG_BOARDNAME t1023rdb #endif #define CONFIG_EXTRA_ENV_SETTINGS \ -- 2.1.0.27.g96db324

1 0

[U-Boot] [PATCH v1 1/1] fastboot: Add support for flashing zImage
by Dileep Katta 12 Mar '15

12 Mar '15

This patch adds support to flash zImage to the boot partition on eMMC. Usage: fastboot flash zImage <path_to_zImage> Signed-off-by: Angela Stegmaier <angelabaker(a)ti.com> Signed-off-by: Dileep Katta <dileep.katta(a)linaro.org> --- drivers/usb/gadget/f_fastboot.c | 152 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 310175a..d3d16c0 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -23,6 +23,7 @@ #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV #include <fb_mmc.h> #endif +#include <android_image.h> #define FASTBOOT_VERSION "0.4" @@ -492,6 +493,152 @@ static void cb_continue(struct usb_ep *ep, struct usb_request *req) } #ifdef CONFIG_FASTBOOT_FLASH +static int fastboot_update_zimage(void); + +static u32 fastboot_get_boot_ptn(struct andr_img_hdr *hdr, char *response, + block_dev_desc_t *dev_desc) +{ + u32 hdr_sectors = 0; + u32 sector_size; + int status = 0; + strcpy(response, "OKAY"); + disk_partition_t info; + + status = get_partition_info_efi_by_name(dev_desc, "boot", &info); + if (status) { + strcpy(response, "FAILCannot find boot partition"); + goto out; + } + + /* Read the boot image header */ + sector_size = info.blksz; + hdr_sectors = (sizeof(struct andr_img_hdr)/sector_size) + 1; + status = dev_desc->block_read(dev_desc->dev, info.start, + hdr_sectors, (void *)hdr); + + if (status < 0) { + strcpy(response, "FAILCannot read hdr from boot partition"); + goto out; + } + if (android_image_check_header(hdr) != 0) { + printf("bad boot image magic\n"); + strcpy(response, "FAILBoot partition not initialized"); + goto out; + } + + return hdr_sectors; + +out: + strcpy(response, "INFO"); + fastboot_tx_write_str(response); + + return -1; +} + +#define CEIL(a, b) (((a) / (b)) + ((a % b) > 0 ? 1 : 0)) + +static int fastboot_update_zimage(void) +{ + struct andr_img_hdr *hdr = NULL; + u8 *ramdisk_buffer; + u32 ramdisk_sector_start, ramdisk_sectors; + u32 kernel_sector_start, kernel_sectors; + u32 hdr_sectors = 0; + u32 sectors_per_page = 0; + int ret = 0; + block_dev_desc_t *dev_desc; + disk_partition_t info; + char response[RESPONSE_LEN]; + u32 addr = CONFIG_USB_FASTBOOT_BUF_ADDR; + + strcpy(response, "OKAY"); + printf("Flashing zImage...%d bytes\n", download_bytes); + + dev_desc = get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + sprintf(response + strlen(response), + "FAILInvalid mmc device"); + ret = -1; + goto out; + } + + addr += CEIL(download_bytes, 0x1000) * 0x1000; + hdr = (struct andr_img_hdr *)addr; + + hdr_sectors = fastboot_get_boot_ptn(hdr, response, dev_desc); + if (hdr_sectors <= 0) { + sprintf(response + strlen(response), + "FAILInvalid number of boot sectors %d", hdr_sectors); + ret = -1; + goto out; + } + ret = get_partition_info_efi_by_name(dev_desc, "boot", &info); + if (ret) { + strcpy(response, "FAILCannot find boot partition"); + ret = -1; + goto out; + } + + /* Extract ramdisk location and read it into local buffer */ + sectors_per_page = hdr->page_size / info.blksz; + ramdisk_sector_start = info.start + sectors_per_page; + ramdisk_sector_start += CEIL(hdr->kernel_size, hdr->page_size)* + sectors_per_page; + ramdisk_sectors = CEIL(hdr->ramdisk_size, hdr->page_size)* + sectors_per_page; + + ramdisk_buffer = (u8 *)hdr; + ramdisk_buffer += (hdr_sectors * info.blksz); + ret = dev_desc->block_read(dev_desc->dev, ramdisk_sector_start, + ramdisk_sectors, ramdisk_buffer); + if (ret < 0) { + sprintf(response, "FAILCannot read ramdisk from 'boot'"); + ret = -1; + goto out; + } + + /* Change the boot img hdr */ + hdr->kernel_size = download_bytes; + ret = dev_desc->block_write(dev_desc->dev, info.start, + hdr_sectors, (void *)hdr); + if (ret < 0) { + sprintf(response, "FAILCannot writeback boot img hdr"); + ret = -1; + goto out; + } + + /* Write the new downloaded kernel*/ + kernel_sector_start = info.start + sectors_per_page; + kernel_sectors = CEIL(hdr->kernel_size, hdr->page_size)* + sectors_per_page; + ret = dev_desc->block_write(dev_desc->dev, kernel_sector_start, + kernel_sectors, + (const void *)CONFIG_USB_FASTBOOT_BUF_ADDR); + if (ret < 0) { + sprintf(response, "FAILCannot write new kernel"); + ret = -1; + goto out; + } + + /* Write the saved Ramdisk back */ + ramdisk_sector_start = info.start + sectors_per_page; + ramdisk_sector_start += CEIL(hdr->kernel_size, hdr->page_size)* + sectors_per_page; + ret = dev_desc->block_write(dev_desc->dev, ramdisk_sector_start, + ramdisk_sectors, ramdisk_buffer); + if (ret < 0) { + sprintf(response, "FAILCannot write back original ramdisk"); + ret = -1; + goto out; + } + fastboot_tx_write_str(response); + return 0; + +out: + fastboot_tx_write_str(response); + return ret; +} + static void cb_flash(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; @@ -505,6 +652,11 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req) } strcpy(response, "FAILno flash device defined"); + + if (!strcmp(cmd, "zImage") || !strcmp(cmd, "zimage")) { + fastboot_update_zimage(); + return; + } #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV fb_mmc_flash_write(cmd, (void *)CONFIG_USB_FASTBOOT_BUF_ADDR, download_bytes, response); -- 1.8.3.2

4 5

[U-Boot] [PATCH v2] mmc: fsl_esdhc: Add support for DDR mode
by Volodymyr Riazantsev 12 Mar '15

12 Mar '15

Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Change-Id: Ie27a945c9fe79d044cc886e269b60747f1744116 Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev(a)globallogic.com> --- drivers/mmc/fsl_esdhc.c | 8 ++++++-- include/configs/mx6_common.h | 2 ++ include/fsl_esdhc.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c55eb28..f5d2ccb 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -319,7 +319,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) esdhc_write32(&regs->cmdarg, cmd->cmdarg); #if defined(CONFIG_FSL_USDHC) esdhc_write32(&regs->mixctrl, - (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); + (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) + | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000); #else esdhc_write32(&regs->xfertyp, xfertyp); @@ -442,7 +443,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) if ((sdhc_clk / (div * pre_div)) <= clock) break; - pre_div >>= 1; + pre_div >>= mmc->ddr_mode ? 2 : 1; div -= 1; clk = (pre_div << 8) | (div << 4); @@ -601,6 +602,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) } cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; +#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; +#endif if (cfg->max_bus_width > 0) { if (cfg->max_bus_width < 8) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e0528ce..29b72b2 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif +#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + #define CONFIG_MP #define CONFIG_MXC_GPT_HCLK diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index c1b6648..313fa1e 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -108,6 +108,7 @@ #define XFERTYP_RSPTYP_48_BUSY 0x00030000 #define XFERTYP_MSBSEL 0x00000020 #define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_DDREN 0x00000008 #define XFERTYP_AC12EN 0x00000004 #define XFERTYP_BCEN 0x00000002 #define XFERTYP_DMAEN 0x00000001 -- 2.2.0

4 8

[U-Boot] [PATCH 1/2] pci/layerscape: move pcie_layerscape.h out of arm include
by Minghuan Lian 12 Mar '15

12 Mar '15

The patch moves pcie_layerscape.h out of arm include to top level include folder so that it can be shared on other Socs. Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- arch/arm/include/asm/pcie_layerscape.h | 13 ------------- board/freescale/ls1021atwr/ls1021atwr.c | 3 ++- drivers/pci/pcie_layerscape.c | 2 +- include/pcie_layerscape.h | 13 +++++++++++++ 4 files changed, 16 insertions(+), 15 deletions(-) delete mode 100644 arch/arm/include/asm/pcie_layerscape.h create mode 100644 include/pcie_layerscape.h diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h deleted file mode 100644 index fb08578..0000000 --- a/arch/arm/include/asm/pcie_layerscape.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PCIE_LAYERSCAPE_H_ -#define __PCIE_LAYERSCAPE_H_ - -void pci_init_board(void); -void ft_pcie_setup(void *blob, bd_t *bd); - -#endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index fb8525f..2d5c29c 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,7 +12,6 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> -#include <asm/pcie_layerscape.h> #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> @@ -21,6 +20,8 @@ #include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <pcie_layerscape.h> + #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" #endif diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index bcad8f2..15e3546 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -11,7 +11,7 @@ #include <asm/io.h> #include <errno.h> #include <malloc.h> -#include <asm/pcie_layerscape.h> +#include <pcie_layerscape.h> #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE diff --git a/include/pcie_layerscape.h b/include/pcie_layerscape.h new file mode 100644 index 0000000..fb08578 --- /dev/null +++ b/include/pcie_layerscape.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PCIE_LAYERSCAPE_H_ +#define __PCIE_LAYERSCAPE_H_ + +void pci_init_board(void); +void ft_pcie_setup(void *blob, bd_t *bd); + +#endif -- 1.9.1

3 3