February 2015 - U-Boot

[U-Boot] [PATCH 0/7] ARM: UniPhier: code refactoring and I2C pin fix
by Masahiro Yamada 06 Feb '15

06 Feb '15

Masahiro Yamada (7): ARM: UniPhier: move pin_init() to board_early_init_f() ARM: UniPhier: move SPL init functions to spl_board_init() ARM: UniPhier: revive support card info ARM: UniPhier: remove unused checkboard() functions ARM: UniPhier: do not compile unnecessary objects ARM: UniPhier: consolidate MEMCONF setting code ARM: UniPhier: enable I2C input pins for PH1-sLD8 arch/arm/cpu/armv7/uniphier/Kconfig | 11 +- arch/arm/cpu/armv7/uniphier/Makefile | 28 ++-- arch/arm/cpu/armv7/uniphier/board_early_init_f.c | 22 ++++ arch/arm/cpu/armv7/uniphier/board_postclk_init.c | 47 ------- arch/arm/cpu/armv7/uniphier/dram_init.c | 23 +--- arch/arm/cpu/armv7/uniphier/memconf.c | 141 +++++++++++++++++++++ arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 14 +- arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c | 11 +- arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 13 +- arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c | 16 --- arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c | 11 +- arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 14 +- arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c | 16 --- arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c | 9 ++ .../{ph1-ld4/board_info.c => print_misc_info.c} | 7 +- arch/arm/cpu/armv7/uniphier/spl.c | 57 ++++++++- arch/arm/include/asm/arch-uniphier/sg-regs.h | 119 +---------------- include/configs/uniphier.h | 4 +- 18 files changed, 276 insertions(+), 287 deletions(-) create mode 100644 arch/arm/cpu/armv7/uniphier/board_early_init_f.c delete mode 100644 arch/arm/cpu/armv7/uniphier/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/memconf.c delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c rename arch/arm/cpu/armv7/uniphier/{ph1-ld4/board_info.c => print_misc_info.c} (57%) -- 1.9.1

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[U-Boot] [PATCH v2 0/6] ARM: UniPhier: add doc, improve I2C EEPROM access
by Masahiro Yamada 06 Feb '15

06 Feb '15

Masahiro Yamada (6): ARM: UniPhier: use "&&" instead of ";" in commands ARM: UniPhier: add environment variable to update images in NAND ARM: UniPhier: add a simple README file for UniPhier platform MAINTAINERS: claim maintainership of files with "uniphier" pattern ARM: UniPhier: move EEPROM device node into a separate DTS ARM: UniPhier: set I2C offset length of on-board EEPROM in DTS MAINTAINERS | 2 +- arch/arm/dts/uniphier-ph1-ld4-ref.dts | 7 +-- arch/arm/dts/uniphier-ph1-pro4-ref.dts | 7 +-- arch/arm/dts/uniphier-ph1-sld3-ref.dts | 7 +-- arch/arm/dts/uniphier-ph1-sld8-ref.dts | 7 +-- arch/arm/dts/uniphier-ref-daughter.dtsi | 16 +++++++ doc/README.uniphier | 85 +++++++++++++++++++++++++++++++++ include/configs/uniphier.h | 15 ++++-- 8 files changed, 120 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/uniphier-ref-daughter.dtsi create mode 100644 doc/README.uniphier -- 1.9.1

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[U-Boot] [PATCH] ARM: UniPhier: remove dummy gpio.h
by Masahiro Yamada 06 Feb '15

06 Feb '15

This dummy header was introduced by commit 630bf80ebb34 (ARM: UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROL). Thanks to commit a08d643dbd85 (dm: Drop gpio.h header from fdtdec.c), such an ugly workaround is no longer needed. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/arm/include/asm/arch-uniphier/gpio.h | 6 ------ 1 file changed, 6 deletions(-) delete mode 100644 arch/arm/include/asm/arch-uniphier/gpio.h diff --git a/arch/arm/include/asm/arch-uniphier/gpio.h b/arch/arm/include/asm/arch-uniphier/gpio.h deleted file mode 100644 index 1fc4e19..0000000 --- a/arch/arm/include/asm/arch-uniphier/gpio.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Dummy header file to enable CONFIG_OF_CONTROL. - * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. - * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable - * OF_CONTROL must have arch/gpio.h even if GPIO is not supported. - */ -- 1.9.1

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[U-Boot] [PATCH v3 0/4] dm:gpio:mxc add DT support
by Peng Fan 06 Feb '15

06 Feb '15

This patch set is to add DT support for mxc_gpio driver. patch 1/4 and 2/4, a new dev_get_addr interface is abstracted to improve driver who want to get device address. patch 3/4, add a new bank_index entry in platdata to avoid `plat - mxc_plat` pointer subtract usage. patch 4/4, add compatible ids and implement bind function. Also commented out U_BOOT_DEVICES and mxc_plat, since they are not needed if using DT. Changes v3: 1. split bank_index patch 2. abstract dev_get_addr for driver Changes v2: 1. remove uneccessary #ifdef 2. add more stuff in commit log 3. include a new function mxc_get_gpio_addr to get register base. This function is different for DT and not DT, by `#ifdef`. If using one implementation for DT and not DT, final image will be big. 4. include a new entry in platdata, named bank_index. it can simplify DT support. To no DT, bank_index is static initilized; to DT, bank_index is get from device's req_seq. Peng Fan (4): dm: introduce dev_get_addr interface dm: add dev_get_addr prototype dm:gpio:mxc add a bank_index entry in platdata dm:gpio:mxc add DT support drivers/core/device.c | 19 +++++++++++++ drivers/gpio/mxc_gpio.c | 72 ++++++++++++++++++++++++++++++++++++------------- include/dm/device.h | 9 +++++++ 3 files changed, 82 insertions(+), 18 deletions(-) -- 1.8.4

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[U-Boot] [PATCH][v3] crypto/fsl - Add progressive hashing support using hardware acceleration.
by Gaurav Rana 06 Feb '15

06 Feb '15

Currently only normal hashing is supported using hardware acceleration. Added support for progressinve hashing using h/w. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana(a)freescale.com> CC: Simon Glass <sjg(a)chromium.org> --- Changes in v3: Remove duplication of code and create function gen_hash_type. Modify MAX_SG to MAX_SG_32 Changes in v2: Merge to common functions for SHA1 and SHA256. Replace malloc and memset with calloc. Remove cast conversions for void* pointers. Replace hardcoded errors with Macros. Corrected comments. README | 4 ++ common/hash.c | 10 +++ drivers/crypto/fsl/fsl_hash.c | 137 +++++++++++++++++++++++++++++++++++++++++- drivers/crypto/fsl/fsl_hash.h | 34 +++++++++++ include/fsl_sec.h | 26 ++++++++ include/hw_sha.h | 39 ++++++++++++ 6 files changed, 249 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/fsl/fsl_hash.h diff --git a/README b/README index cac7978..4c72baa 100644 --- a/README +++ b/README @@ -3151,6 +3151,10 @@ CBFS (Coreboot Filesystem) support CONFIG_SHA1 - support SHA1 hashing CONFIG_SHA256 - support SHA256 hashing + CONFIG_SHA_HW_ACCEL - support SHA1 and SHA256 hashing using + hardware acceleration + CONFIG_SHA_PROG_HW_ACCEL - support SHA1 and SHA256 progressive + hashing using hw acceleration Note: There is also a sha1sum command, which should perhaps be deprecated in favour of 'hash sha1'. diff --git a/common/hash.c b/common/hash.c index d154d02..9e9f84b 100644 --- a/common/hash.c +++ b/common/hash.c @@ -127,11 +127,21 @@ static struct hash_algo hash_algo[] = { SHA1_SUM_LEN, hw_sha1, CHUNKSZ_SHA1, +#ifdef CONFIG_SHA_PROG_HW_ACCEL + hw_sha_init, + hw_sha_update, + hw_sha_finish, +#endif }, { "sha256", SHA256_SUM_LEN, hw_sha256, CHUNKSZ_SHA256, +#ifdef CONFIG_SHA_PROG_HW_ACCEL + hw_sha_init, + hw_sha_update, + hw_sha_finish, +#endif }, #endif #ifdef CONFIG_SHA1 diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index d77f257..40dfe72 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -10,6 +10,8 @@ #include "jobdesc.h" #include "desc.h" #include "jr.h" +#include "fsl_hash.h" +#include <hw_sha.h> #define CRYPTO_MAX_ALG_NAME 80 #define SHA1_DIGEST_SIZE 20 @@ -39,6 +41,122 @@ static struct caam_hash_template driver_hash[] = { }, }; +static enum caam_hash_algos get_hash_type(struct hash_algo *algo) +{ + if (!strcmp(algo->name, driver_hash[SHA1].name)) + return SHA1; + else + return SHA256; +} + +/* Create the context for progressive hashing using h/w acceleration. + * + * @ctxp: Pointer to the pointer of the context for hashing + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -ENOMEM on error + */ +static int caam_hash_init(void **ctxp, enum caam_hash_algos caam_algo) +{ + *ctxp = calloc(1, sizeof(struct sha_ctx)); + if (*ctxp == NULL) { + debug("Cannot allocate memory for context\n"); + return -ENOMEM; + } + return 0; +} + +/* + * Update sg table for progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * We support MAX of 32 SG Entries. + * + * @hash_ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -EINVAL on error + */ +static int caam_hash_update(void *hash_ctx, const void *buf, + unsigned int size, int is_last, + enum caam_hash_algos caam_algo) +{ + uint32_t final = 0; + dma_addr_t addr = virt_to_phys((void *)buf); + struct sha_ctx *ctx = hash_ctx; + + if (ctx->sg_num >= MAX_SG_32) { + free(ctx); + return -EINVAL; + } + +#ifdef CONFIG_PHYS_64BIT + ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32; +#else + ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0; +#endif + ctx->sg_tbl[ctx->sg_num].addr_lo = addr; + + sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, + (size & SG_ENTRY_LENGTH_MASK)); + + ctx->sg_num++; + + if (is_last) { + final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) | + SG_ENTRY_FINAL_BIT; + sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final); + } + + return 0; +} + +/* + * Perform progressive hashing on the given buffer and copy hash at + * destination buffer + * + * The context is freed after completion of hash operation. + * + * @hash_ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -EINVAL on error + */ +static int caam_hash_finish(void *hash_ctx, void *dest_buf, + int size, enum caam_hash_algos caam_algo) +{ + uint32_t len = 0; + struct sha_ctx *ctx = hash_ctx; + int i = 0, ret = 0; + + if (size < driver_hash[caam_algo].digestsize) { + free(ctx); + return -EINVAL; + } + + for (i = 0; i < ctx->sg_num; i++) + len += (sec_in32(&ctx->sg_tbl[i].len_flag) & + SG_ENTRY_LENGTH_MASK); + + inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len, + ctx->hash, + driver_hash[caam_algo].alg_type, + driver_hash[caam_algo].digestsize, + 1); + + ret = run_descriptor_jr(ctx->sha_desc); + + if (ret) + debug("Error %x\n", ret); + else + memcpy(dest_buf, ctx->hash, sizeof(ctx->hash)); + + free(ctx); + return ret; +} + int caam_hash(const unsigned char *pbuf, unsigned int buf_len, unsigned char *pout, enum caam_hash_algos algo) { @@ -48,7 +166,7 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); - return -1; + return -ENOMEM; } inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout, @@ -75,3 +193,20 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, if (caam_hash(pbuf, buf_len, pout, SHA1)) printf("CAAM was not setup properly or it is faulty\n"); } + +int hw_sha_init(struct hash_algo *algo, void **ctxp) +{ + return caam_hash_init(ctxp, get_hash_type(algo)); +} + +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last) +{ + return caam_hash_update(ctx, buf, size, is_last, get_hash_type(algo)); +} + +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size) +{ + return caam_hash_finish(ctx, dest_buf, size, get_hash_type(algo)); +} diff --git a/drivers/crypto/fsl/fsl_hash.h b/drivers/crypto/fsl/fsl_hash.h new file mode 100644 index 0000000..01e0e2a --- /dev/null +++ b/drivers/crypto/fsl/fsl_hash.h @@ -0,0 +1,34 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef _SHA_H +#define _SHA_H + +#include <fsl_sec.h> +#include <hash.h> +#include "jr.h" + +/* We support MAX of 32 SG Entries.*/ +#define MAX_SG_32 32 + +/* + * Hash context contains the following fields + * @sha_desc: Sha Descriptor + * @sg_num: number of entries in sg table + * @len: total length of buffer + * @sg_tbl: sg entry table + * @hash: index to the hash calculated + */ +struct sha_ctx { + uint32_t sha_desc[64]; + uint32_t sg_num; + uint32_t len; + struct sg_entry sg_tbl[MAX_SG_32]; + u8 hash[HASH_MAX_DIGEST_SIZE]; +}; + +#endif diff --git a/include/fsl_sec.h b/include/fsl_sec.h index aa850a3..b6e6f04 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -175,6 +175,32 @@ struct jr_regs { u32 jrcr; }; +/* + * Scatter Gather Entry - Specifies the the Scatter Gather Format + * related information + */ +struct sg_entry { +#ifdef CONFIG_SYS_FSL_SEC_LE + uint32_t addr_lo; /* Memory Address - lo */ + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint16_t reserved_zero; +#else + uint16_t reserved_zero; + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint32_t addr_lo; /* Memory Address - lo */ +#endif + + uint32_t len_flag; /* Length of the data in the frame */ +#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF +#define SG_ENTRY_EXTENSION_BIT 0x80000000 +#define SG_ENTRY_FINAL_BIT 0x40000000 + uint32_t bpid_offset; +#define SG_ENTRY_BPID_MASK 0x00FF0000 +#define SG_ENTRY_BPID_SHIFT 16 +#define SG_ENTRY_OFFSET_MASK 0x00001FFF +#define SG_ENTRY_OFFSET_SHIFT 0 +}; + int sec_init(void); #endif diff --git a/include/hw_sha.h b/include/hw_sha.h index 783350d..3d8213e 100644 --- a/include/hw_sha.h +++ b/include/hw_sha.h @@ -34,4 +34,43 @@ void hw_sha256(const uchar * in_addr, uint buflen, */ void hw_sha1(const uchar * in_addr, uint buflen, uchar * out_addr, uint chunk_size); + +/* + * Create the context for sha progressive hashing using h/w acceleration + * + * @algo: Pointer to the hash_algo struct + * @ctxp: Pointer to the pointer of the context for hashing + * @return 0 if ok, -ve on error + */ +int hw_sha_init(struct hash_algo *algo, void **ctxp); + +/* + * Update buffer for sha progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @return 0 if ok, -ve on error + */ +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last); + +/* + * Copy sha hash result at destination location + * + * The context is freed after completion of hash operation or after an error. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @return 0 if ok, -ve on error + */ +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size); + #endif -- 1.8.1.4

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[U-Boot] [PATCH v2] armv8/vexpress64: make multientry conditional
by Linus Walleij 06 Feb '15

06 Feb '15

While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- ChangeLog v1->v2: - Move configuration of ARMV8_MULTIENTRY over to Kconfig as requested by Tom Rini. This patch applied on top of the other patch series send, ending with [PATCH 4/4] vexpress64: support the Juno Development Platform Please apply it on top of these if the patch seems OK. --- arch/arm/Kconfig | 4 ++++ arch/arm/cpu/armv8/Kconfig | 6 ++++++ arch/arm/cpu/armv8/start.S | 8 ++++---- arch/arm/include/asm/macro.h | 8 ++++++++ board/armltd/vexpress64/vexpress64.c | 6 ------ include/configs/vexpress_aemv8a.h | 8 -------- 6 files changed, 22 insertions(+), 18 deletions(-) create mode 100644 arch/arm/cpu/armv8/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 986b4c5d81db..75dd9bb60d6b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -743,10 +743,12 @@ config TARGET_VEXPRESS64_JUNO config TARGET_LS2085A_EMU bool "Support ls2085a_emu" select ARM64 + select ARMV8_MULTIENTRY config TARGET_LS2085A_SIMU bool "Support ls2085a_simu" select ARM64 + select ARMV8_MULTIENTRY config TARGET_LS1021AQDS bool "Support ls1021aqds" @@ -855,6 +857,8 @@ source "arch/arm/cpu/armv7/zynq/Kconfig" source "arch/arm/cpu/armv7/Kconfig" +source "arch/arm/cpu/armv8/Kconfig" + source "board/aristainetos/Kconfig" source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig new file mode 100644 index 000000000000..4cd84b031114 --- /dev/null +++ b/arch/arm/cpu/armv8/Kconfig @@ -0,0 +1,6 @@ +if ARM64 + +config ARMV8_MULTIENTRY + boolean "Enable multiple CPUs to enter into U-boot" + +endif diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 4b11aa4f2227..9b439f30b779 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -77,6 +77,7 @@ reset: /* Processor specific initialization */ bl lowlevel_init +#ifdef CONFIG_ARMV8_MULTIENTRY branch_if_master x0, x1, master_cpu /* @@ -88,11 +89,10 @@ slave_cpu: ldr x0, [x1] cbz x0, slave_cpu br x0 /* branch to the given address */ - - /* - * Master CPU - */ master_cpu: + /* On the master CPU */ +#endif /* CONFIG_ARMV8_MULTIENTRY */ + bl _main /*-----------------------------------------------------------------------*/ diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 1c8c4251ee0c..3b3146ab2239 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -78,6 +78,8 @@ lr .req x30 * choose processor with all zero affinity value as the master. */ .macro branch_if_slave, xreg, slave_label +#ifdef CONFIG_ARMV8_MULTIENTRY + /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ mrs \xreg, mpidr_el1 tst \xreg, #0xff /* Test Affinity 0 */ b.ne \slave_label @@ -90,6 +92,7 @@ lr .req x30 lsr \xreg, \xreg, #16 tst \xreg, #0xff /* Test Affinity 3 */ b.ne \slave_label +#endif .endm /* @@ -97,12 +100,17 @@ lr .req x30 * choose processor with all zero affinity value as the master. */ .macro branch_if_master, xreg1, xreg2, master_label +#ifdef CONFIG_ARMV8_MULTIENTRY + /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ mrs \xreg1, mpidr_el1 lsr \xreg2, \xreg1, #32 lsl \xreg1, \xreg1, #40 lsr \xreg1, \xreg1, #40 orr \xreg1, \xreg1, \xreg2 cbz \xreg1, \master_label +#else + b \master_label +#endif .endm .macro armv8_switch_to_el2_m, xreg1 diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 58973185ecda..7ab000cca77b 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -22,12 +22,6 @@ int board_init(void) int dram_init(void) { - /* - * Clear spin table so that secondary processors - * observe the correct value after waken up from wfe. - */ - *(unsigned long *)CPU_RELEASE_ADDR = 0; - gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 7fb28a54ba17..e276fff7e442 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -56,14 +56,6 @@ /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT - -/* SMP Spin Table Definitions */ -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) -#else -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#endif - /* CS register bases for the original memory map. */ #define V2M_PA_CS0 0x00000000 #define V2M_PA_CS1 0x14000000 -- 1.9.3

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[U-Boot] [PATCH V3] cmd_i2c: Provide option for bulk 'i2c write' in one transaction
by Lubomir Popov 06 Feb '15

06 Feb '15

I2C chips do exist that require a write of some multi-byte data to occur in a single bus transaction (aka atomic transfer), otherwise either the write does not come into effect at all, or normal operation of internal circuitry cannot be guaranteed. The current implementation of the 'i2c write' command (transfer of multiple bytes from a memory buffer) in fact performs a separate transaction for each byte to be written and thus cannot support such types of I2C slave devices. This patch provides an alternative by allowing 'i2c write' to execute the write transfer of the given number of bytes in a single bus transaction if the '-s' option is specified as a final command argument. Else the current re-addressing method is used. Signed-off-by: Lubomir Popov <l-popov(a)ti.com> --- Changes in V3: Rebased on current master. Changes in V2: The option to use bulk transfer vs re-addressing is implemented as a run-time command argument. V1 used conditional compilation through a board header definition. common/cmd_i2c.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 22db1bb..8d4f5f6 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -344,7 +344,7 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ struct udevice *dev; #endif - if (argc != 5) + if ((argc < 5) || (argc > 6)) return cmd_usage(cmdtp); /* @@ -367,7 +367,7 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ return cmd_usage(cmdtp); /* - * Length is the number of objects, not number of bytes. + * Length is the number of bytes. */ length = simple_strtoul(argv[4], NULL, 16); @@ -379,20 +379,40 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ return i2c_report_err(ret, I2C_ERR_WRITE); #endif - while (length-- > 0) { + if (argc == 6 && !strcmp(argv[5], "-s")) { + /* + * Write all bytes in a single I2C transaction. If the target + * device is an EEPROM, it is your responsibility to not cross + * a page boundary. No write delay upon completion, take this + * into account if linking commands. + */ #ifdef CONFIG_DM_I2C - ret = i2c_write(dev, devaddr++, memaddr++, 1); + ret = i2c_write(dev, devaddr, memaddr, length); #else - ret = i2c_write(chip, devaddr++, alen, memaddr++, 1); + ret = i2c_write(chip, devaddr, alen, memaddr, length); #endif if (ret) return i2c_report_err(ret, I2C_ERR_WRITE); + } else { + /* + * Repeated addressing - perform <length> separate + * write transactions of one byte each + */ + while (length-- > 0) { +#ifdef CONFIG_DM_I2C + ret = i2c_write(dev, devaddr++, memaddr++, 1); +#else + ret = i2c_write(chip, devaddr++, alen, memaddr++, 1); +#endif + if (ret) + return i2c_report_err(ret, I2C_ERR_WRITE); /* * No write delay with FRAM devices. */ #if !defined(CONFIG_SYS_I2C_FRAM) - udelay(11000); + udelay(11000); #endif + } } return 0; } @@ -1823,7 +1843,7 @@ static cmd_tbl_t cmd_i2c_sub[] = { U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""), U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""), U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""), - U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""), + U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""), #ifdef CONFIG_DM_I2C U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""), #endif @@ -1890,7 +1910,8 @@ static char i2c_help_text[] = "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" "i2c probe [address] - test for and show device(s) on the I2C bus\n" "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n" - "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n" + "i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n" + " to I2C; the -s option selects bulk write in a single transaction\n" #ifdef CONFIG_DM_I2C "i2c flags chip [flags] - set or get chip flags\n" #endif @@ -1902,7 +1923,7 @@ static char i2c_help_text[] = #endif U_BOOT_CMD( - i2c, 6, 1, do_i2c, + i2c, 7, 1, do_i2c, "I2C sub-system", i2c_help_text ); -- 1.7.9.5

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[U-Boot] U-Boot with PXE
by Islam Mukambetov 06 Feb '15

06 Feb '15

If there is any u-boot for parallella, with PXE booting? If you have, please, can you send me a link, where i can find sources or u-boot image, and flash it to parallella. -- ______________ Ислам Мукамбетов

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[U-Boot] [PATCH 0/6] imx:mx6 spl support for mx6sxsabresd
by Peng Fan 06 Feb '15

06 Feb '15

This patch set is to make mx6sxsabresd spl boot capable from USDHC. SPL image is burned to sector 2 of SD card. u-boot.img is burned to sector 138. Since i.MX 6SoloX chip only supports one mmdc channel, in order to reuse mx6_dram_cfg, define a new macro MMDC1. To i.MX 6SoloX, MMDC1 does nothing; to others, MMDC1 effects as the original "mmdc1->entry = value". Peng Fan (6): imx:mx6sxsabresd add spl config file imx:mx6sxsabresd select SUPPORT_SPL imx:mx6sxsabresd spl support in header file imx:mx6sx add dram io configure for mx6sx imx:mx6 add mx6sx in imx spl header file imx:mx6sxsabresd board spl support arch/arm/Kconfig | 1 + arch/arm/cpu/armv7/mx6/ddr.c | 96 +++++++++++++--- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 46 ++++++++ board/freescale/mx6sxsabresd/MAINTAINERS | 1 + board/freescale/mx6sxsabresd/mx6sxsabresd.c | 168 ++++++++++++++++++++++++++++ configs/mx6sxsabresd_spl_defconfig | 4 + include/configs/imx6_spl.h | 8 ++ include/configs/mx6sxsabresd.h | 6 + 8 files changed, 316 insertions(+), 14 deletions(-) create mode 100644 configs/mx6sxsabresd_spl_defconfig -- 1.8.4

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[U-Boot] [PATCH] cmd_i2c: quit I2C commands immediately on error
by Masahiro Yamada 06 Feb '15

06 Feb '15

If the i2c driver returns an error status, error out immediately. Continuing the loop just results in printing error messages again and again. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Heiko Schocher <hs(a)denx.de> --- common/cmd_i2c.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 7c3ad00..12ce3f3 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -518,7 +518,7 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] ret = i2c_read(chip, addr, alen, linebuf, linebytes); #endif if (ret) - i2c_report_err(ret, I2C_ERR_READ); + return i2c_report_err(ret, I2C_ERR_READ); else { printf("%04x:", addr); cp = linebuf; @@ -616,7 +616,7 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] ret = i2c_write(chip, addr++, alen, &byte, 1); #endif if (ret) - i2c_report_err(ret, I2C_ERR_WRITE); + return i2c_report_err(ret, I2C_ERR_WRITE); /* * Wait for the write to complete. The write can take * up to 10mSec (we allow a little more time). @@ -798,16 +798,15 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg ret = i2c_read(chip, addr, alen, (uchar *)&data, size); #endif if (ret) - i2c_report_err(ret, I2C_ERR_READ); - else { - data = cpu_to_be32(data); - if (size == 1) - printf(" %02lx", (data >> 24) & 0x000000FF); - else if (size == 2) - printf(" %04lx", (data >> 16) & 0x0000FFFF); - else - printf(" %08lx", data); - } + return i2c_report_err(ret, I2C_ERR_READ); + + data = cpu_to_be32(data); + if (size == 1) + printf(" %02lx", (data >> 24) & 0x000000FF); + else if (size == 2) + printf(" %04lx", (data >> 16) & 0x0000FFFF); + else + printf(" %08lx", data); nbytes = cli_readline(" ? "); if (nbytes == 0) { @@ -848,7 +847,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg (uchar *)&data, size); #endif if (ret) - i2c_report_err(ret, I2C_ERR_WRITE); + return i2c_report_err(ret, + I2C_ERR_WRITE); #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif -- 1.9.1

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