February 2015 - U-Boot

[U-Boot] [PATCH] arm: rmobile: r8a7794: Enable SMP mode of Auxiliary Control Register
by Nobuhiro Iwamatsu 10 Feb '15

10 Feb '15

R8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we need to enable SMP bit of Auxiliary Control Register. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index d47546a..fc839ea 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -40,7 +40,7 @@ do_lowlevel_init: and r1, r1, #0x7F00 lsrs r1, r1, #8 cmp r1, #0x4C /* 0x4C is ID of r8a7794 */ - beq _exit_init_l2_a15 + beq _enable_actlr_smp /* surpress wfe if ca15 */ tst r4, #4 @@ -64,6 +64,14 @@ do_lowlevel_init: orrne r0, r0, #0x20 /* L2CTLR[5] */ #endif mcrne p15, 1, r0, c9, c0, 2 + + b _exit_init_l2_a15 + +_enable_actlr_smp: /* R8A7794 only (CA7) */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + _exit_init_l2_a15: ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) sub sp, r3, #4 -- 2.1.3

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[U-Boot] [PATCH] arm: rmobile: Add SILK board support
by Vladimir Barinov 10 Feb '15

10 Feb '15

SILK is an entry level development board based on R-Car E2 SoC (R8A7794) This commit supports the following peripherals: - SCIF, I2C, Ethernet, QSPI, MMC, USB Host Signed-off-by: Vladimir Barinov <vladimir.barinov(a)cogentembedded.com> --- arch/arm/cpu/armv7/rmobile/Kconfig | 6 +- board/renesas/silk/Kconfig | 12 + board/renesas/silk/MAINTAINERS | 6 + board/renesas/silk/Makefile | 10 + board/renesas/silk/qos.c | 951 +++++++++++++++++++++++++++++++++++++ board/renesas/silk/silk.c | 175 +++++++ configs/silk_defconfig | 3 + include/configs/silk.h | 117 +++++ 8 files changed, 1279 insertions(+), 1 deletion(-) create mode 100644 board/renesas/silk/Kconfig create mode 100644 board/renesas/silk/MAINTAINERS create mode 100644 board/renesas/silk/Makefile create mode 100644 board/renesas/silk/qos.c create mode 100644 board/renesas/silk/silk.c create mode 100644 configs/silk_defconfig create mode 100644 include/configs/silk.h diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index 6d94199..3586650 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -21,6 +21,9 @@ config TARGET_KZM9G config TARGET_ALT bool "Alt board" +config TARGET_SILK + bool "Silk board" + endchoice config SYS_SOC @@ -28,7 +31,7 @@ config SYS_SOC config RMOBILE_EXTRAM_BOOT bool "Enable boot from RAM" - depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK default n source "board/atmark-techno/armadillo-800eva/Kconfig" @@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig" source "board/renesas/lager/Kconfig" source "board/kmc/kzm9g/Kconfig" source "board/renesas/alt/Kconfig" +source "board/renesas/silk/Kconfig" endif diff --git a/board/renesas/silk/Kconfig b/board/renesas/silk/Kconfig new file mode 100644 index 0000000..07aee0e --- /dev/null +++ b/board/renesas/silk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SILK + +config SYS_BOARD + default "silk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "silk" + +endif diff --git a/board/renesas/silk/MAINTAINERS b/board/renesas/silk/MAINTAINERS new file mode 100644 index 0000000..b566ccf --- /dev/null +++ b/board/renesas/silk/MAINTAINERS @@ -0,0 +1,6 @@ +SILK BOARD +M: Cogent Embedded, Inc. <source(a)cogentembedded.com> +S: Maintained +F: board/renesas/silk/ +F: include/configs/silk.h +F: configs/silk_defconfig diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile new file mode 100644 index 0000000..e6eea61 --- /dev/null +++ b/board/renesas/silk/Makefile @@ -0,0 +1,10 @@ +# +# board/renesas/silk/Makefile +# +# Copyright (C) 2015 Renesas Electronics Corporation +# Copyright (C) 2015 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := silk.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/silk/qos.c b/board/renesas/silk/qos.c new file mode 100644 index 0000000..4f6e46c --- /dev/null +++ b/board/renesas/silk/qos.c @@ -0,0 +1,951 @@ +/* + * board/renesas/silk/qos.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/arch/rmobile.h> + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +/* QoS version 0.11 */ + +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x1F0D0B0A, &s3c->s3crorr); + writel(0x1F0D0B09, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x80928092, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x0000202A, &qos_addr->dbtmval2); + writel(0x00001FBD, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002019, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x00002043, &qos_addr->dbtmval2); + writel(0x00002030, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002031, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20000800, CCI_400_MAXOT_1); + writel(0x20000800, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000E, &mxi_qos->du0); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c new file mode 100644 index 0000000..8818211 --- /dev/null +++ b/board/renesas/silk/silk.c @@ -0,0 +1,175 @@ +/* + * board/renesas/silk/silk.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/mmc.h> +#include <netdev.h> +#include <miiphy.h> +#include <i2c.h> +#include <div64.h> +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* QoS */ + qos_init(); + +#ifndef CONFIG_DCACHE_OFF + /* + * The caches are disabled when ACTLR.SMP is set to 0 + * regardless of the value of the SCTLR.C (cache enable bit) + * on Cortex-A7 MPCore + */ + asm volatile( + "mrc 15, 0, r0, c1, c0, 1\n" /* read ACTLR */ + "orr r0, r0, #(1 << 6)\n" /* set ACTLR.SMP bit */ + "mcr p15, 0, r0, c1, c0, 1\n"); /* write ACTLR */ +#endif +} + +#define TMU0_MSTP125 (1 << 25) +#define SCIF2_MSTP719 (1 << 19) +#define ETHER_MSTP813 (1 << 13) +#define IIC1_MSTP323 (1 << 23) +#define MMC0_MSTP315 (1 << 15) + +int board_early_init_f(void) +{ + /* TMU */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF2 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + /* IIC1 / sh-i2c ch1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); + +#ifdef CONFIG_SH_MMCIF + /* MMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); +#endif + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7794_pinmux_init(); + + /* Ether Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_MAGIC, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ8, NULL); + + /* PHY reset */ + gpio_request(GPIO_GP_1_24, NULL); + gpio_direction_output(GPIO_GP_1_24, 0); + mdelay(20); + gpio_set_value(GPIO_GP_1_24, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else + return 0; +#endif +} + +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_SH_MMCIF + /* MMC0 */ + gpio_request(GPIO_GP_4_31, NULL); + gpio_set_value(GPIO_GP_4_31, 1); + + ret = mmcif_mmc_init(); +#endif + return ret; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(1); /* PowerIC connected to ch1 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/configs/silk_defconfig b/configs/silk_defconfig new file mode 100644 index 0000000..515ee33 --- /dev/null +++ b/configs/silk_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_SILK=y diff --git a/include/configs/silk.h b/include/configs/silk.h new file mode 100644 index 0000000..a4235e9 --- /dev/null +++ b/include/configs/silk.h @@ -0,0 +1,117 @@ +/* + * include/configs/silk.h + * This file is silk board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __SILK_H +#define __SILK_H + +#undef DEBUG +#define CONFIG_R8A7794 +#define CONFIG_RMOBILE_BOARD_STRING "Silk" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#endif +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF2 +#define CONFIG_SCIF_USE_EXT_CLK + +/* FLASH */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* MMCIF */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SH_MMCIF +#define CONFIG_SH_MMCIF_ADDR 0xee200000 +#define CONFIG_SH_MMCIF_CLK 48000000 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF2 */ +#define CONFIG_SMSTP7_ENA 0x00080000 + +#endif /* __SILK_H */ -- 1.9.1

3 6

[U-Boot] [PATCH] arm: rmobile: r8a7794: Enable SMP mode of Auxiliary Control Register
by Nobuhiro Iwamatsu 10 Feb '15

10 Feb '15

R8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we need to enable SMP bit of Auxiliary Control Register. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index d47546a..fc839ea 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -40,7 +40,7 @@ do_lowlevel_init: and r1, r1, #0x7F00 lsrs r1, r1, #8 cmp r1, #0x4C /* 0x4C is ID of r8a7794 */ - beq _exit_init_l2_a15 + beq _enable_actlr_smp /* surpress wfe if ca15 */ tst r4, #4 @@ -64,6 +64,14 @@ do_lowlevel_init: orrne r0, r0, #0x20 /* L2CTLR[5] */ #endif mcrne p15, 1, r0, c9, c0, 2 + + b _exit_init_l2_a15 + +_enable_actlr_smp: /* R8A7794 only (CA7) */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + _exit_init_l2_a15: ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) sub sp, r3, #4 -- 2.1.3

1 0

[U-Boot] [PATCH 0/11] ARM: remove non-generic boards
by Masahiro Yamada 10 Feb '15

10 Feb '15

Based on Tom's announce mail (http://lists.denx.de/pipermail/u-boot/2015-February/203606.html), let's start removing non-generic ARM boards. No conversion patches have been posted for these boards. Masahiro Yamada (11): ARM: remove mx31ads board support ARM: mx31: remove imx31_phycore board ARM: remove jadecpu board support ARM: remove zmx25 board support ARM: remove devkit3250 board support ARM: remove dkb board support ARM: remove cm4008 and cm41xx board support ARM: remove a320evb board support ARM: armada100: remove aspenite and gplugd board support ARM: remove tnetv107x board support ARM: davinci: remove hawkboard support arch/arm/Kconfig | 60 -- arch/arm/cpu/arm1176/Makefile | 1 - arch/arm/cpu/arm1176/start.S | 22 - arch/arm/cpu/arm1176/tnetv107x/Makefile | 6 - arch/arm/cpu/arm1176/tnetv107x/aemif.c | 78 --- arch/arm/cpu/arm1176/tnetv107x/clock.c | 432 ------------ arch/arm/cpu/arm1176/tnetv107x/init.c | 22 - arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 10 - arch/arm/cpu/arm1176/tnetv107x/mux.c | 319 --------- arch/arm/cpu/arm1176/tnetv107x/timer.c | 93 --- arch/arm/cpu/arm920t/Makefile | 2 - arch/arm/cpu/arm920t/a320/Makefile | 9 - arch/arm/cpu/arm920t/a320/reset.S | 10 - arch/arm/cpu/arm920t/a320/timer.c | 118 ---- arch/arm/cpu/arm920t/ks8695/Makefile | 9 - arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 189 ------ arch/arm/cpu/arm920t/ks8695/timer.c | 77 --- arch/arm/cpu/arm926ejs/Makefile | 4 - arch/arm/cpu/arm926ejs/armada100/Makefile | 9 - arch/arm/cpu/arm926ejs/armada100/cpu.c | 92 --- arch/arm/cpu/arm926ejs/armada100/dram.c | 116 ---- arch/arm/cpu/arm926ejs/armada100/timer.c | 194 ------ arch/arm/cpu/arm926ejs/davinci/Kconfig | 4 - arch/arm/cpu/arm926ejs/lpc32xx/Makefile | 8 - arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 104 --- arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 57 -- arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 39 -- arch/arm/cpu/arm926ejs/lpc32xx/timer.c | 82 --- arch/arm/cpu/arm926ejs/mb86r0x/Makefile | 8 - arch/arm/cpu/arm926ejs/mb86r0x/clock.c | 27 - arch/arm/cpu/arm926ejs/mb86r0x/reset.c | 24 - arch/arm/cpu/arm926ejs/mb86r0x/timer.c | 115 ---- arch/arm/cpu/arm926ejs/pantheon/Makefile | 9 - arch/arm/cpu/arm926ejs/pantheon/cpu.c | 85 --- arch/arm/cpu/arm926ejs/pantheon/dram.c | 117 ---- arch/arm/cpu/arm926ejs/pantheon/timer.c | 201 ------ arch/arm/include/asm/arch-a320/a320.h | 22 - arch/arm/include/asm/arch-armada100/armada100.h | 60 -- arch/arm/include/asm/arch-armada100/config.h | 42 -- arch/arm/include/asm/arch-armada100/cpu.h | 162 ----- arch/arm/include/asm/arch-armada100/gpio.h | 32 - arch/arm/include/asm/arch-armada100/mfp.h | 80 --- arch/arm/include/asm/arch-armada100/spi.h | 79 --- .../include/asm/arch-armada100/utmi-armada100.h | 63 -- arch/arm/include/asm/arch-ks8695/platform.h | 294 --------- arch/arm/include/asm/arch-lpc32xx/clk.h | 157 ----- arch/arm/include/asm/arch-lpc32xx/config.h | 59 -- arch/arm/include/asm/arch-lpc32xx/cpu.h | 51 -- arch/arm/include/asm/arch-lpc32xx/emc.h | 79 --- arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 12 - arch/arm/include/asm/arch-lpc32xx/timer.h | 61 -- arch/arm/include/asm/arch-lpc32xx/uart.h | 101 --- arch/arm/include/asm/arch-lpc32xx/wdt.h | 38 -- arch/arm/include/asm/arch-mb86r0x/hardware.h | 15 - arch/arm/include/asm/arch-mb86r0x/mb86r0x.h | 599 ----------------- arch/arm/include/asm/arch-pantheon/config.h | 53 -- arch/arm/include/asm/arch-pantheon/cpu.h | 77 --- arch/arm/include/asm/arch-pantheon/gpio.h | 0 arch/arm/include/asm/arch-pantheon/mfp.h | 39 -- arch/arm/include/asm/arch-pantheon/pantheon.h | 38 -- arch/arm/include/asm/arch-tnetv107x/clock.h | 53 -- arch/arm/include/asm/arch-tnetv107x/hardware.h | 160 ----- arch/arm/include/asm/arch-tnetv107x/mux.h | 291 --------- arch/arm/lib/asm-offsets.c | 46 -- board/Marvell/aspenite/Kconfig | 15 - board/Marvell/aspenite/MAINTAINERS | 6 - board/Marvell/aspenite/Makefile | 10 - board/Marvell/aspenite/aspenite.c | 43 -- board/Marvell/dkb/Kconfig | 15 - board/Marvell/dkb/MAINTAINERS | 6 - board/Marvell/dkb/Makefile | 9 - board/Marvell/dkb/dkb.c | 85 --- board/Marvell/gplugd/Kconfig | 15 - board/Marvell/gplugd/MAINTAINERS | 6 - board/Marvell/gplugd/Makefile | 15 - board/Marvell/gplugd/gplugd.c | 130 ---- board/cm4008/Kconfig | 12 - board/cm4008/MAINTAINERS | 6 - board/cm4008/Makefile | 8 - board/cm4008/cm4008.c | 88 --- board/cm4008/config.mk | 1 - board/cm4008/flash.c | 395 ----------- board/cm41xx/Kconfig | 12 - board/cm41xx/MAINTAINERS | 6 - board/cm41xx/Makefile | 8 - board/cm41xx/cm41xx.c | 88 --- board/cm41xx/config.mk | 1 - board/cm41xx/flash.c | 395 ----------- board/davinci/da8xxevm/Kconfig | 13 - board/davinci/da8xxevm/MAINTAINERS | 8 - board/davinci/da8xxevm/Makefile | 1 - board/davinci/da8xxevm/README.hawkboard | 92 --- board/davinci/da8xxevm/hawkboard-ais-nand.cfg | 4 - board/davinci/da8xxevm/hawkboard.c | 120 ---- board/davinci/da8xxevm/u-boot-spl-hawk.lds | 69 -- board/faraday/a320evb/Kconfig | 15 - board/faraday/a320evb/MAINTAINERS | 6 - board/faraday/a320evb/Makefile | 9 - board/faraday/a320evb/a320evb.c | 59 -- board/faraday/a320evb/lowlevel_init.S | 106 --- board/freescale/mx31ads/Kconfig | 15 - board/freescale/mx31ads/MAINTAINERS | 6 - board/freescale/mx31ads/Makefile | 8 - board/freescale/mx31ads/lowlevel_init.S | 268 -------- board/freescale/mx31ads/mx31ads.c | 114 ---- board/freescale/mx31ads/u-boot.lds | 110 ---- board/imx31_phycore/Kconfig | 12 - board/imx31_phycore/MAINTAINERS | 11 - board/imx31_phycore/Makefile | 9 - board/imx31_phycore/imx31_phycore.c | 153 ----- board/imx31_phycore/lowlevel_init.S | 88 --- board/syteco/jadecpu/Kconfig | 15 - board/syteco/jadecpu/MAINTAINERS | 6 - board/syteco/jadecpu/Makefile | 13 - board/syteco/jadecpu/jadecpu.c | 160 ----- board/syteco/jadecpu/lowlevel_init.S | 249 ------- board/syteco/zmx25/Kconfig | 15 - board/syteco/zmx25/MAINTAINERS | 6 - board/syteco/zmx25/Makefile | 9 - board/syteco/zmx25/lowlevel_init.S | 97 --- board/syteco/zmx25/zmx25.c | 174 ----- board/ti/tnetv107xevm/Kconfig | 15 - board/ti/tnetv107xevm/MAINTAINERS | 6 - board/ti/tnetv107xevm/Makefile | 5 - board/ti/tnetv107xevm/config.mk | 5 - board/ti/tnetv107xevm/sdb_board.c | 134 ---- board/timll/devkit3250/Kconfig | 15 - board/timll/devkit3250/MAINTAINERS | 6 - board/timll/devkit3250/Makefile | 8 - board/timll/devkit3250/devkit3250.c | 52 -- configs/a320evb_defconfig | 2 - configs/aspenite_defconfig | 2 - configs/cm4008_defconfig | 2 - configs/cm41xx_defconfig | 2 - configs/devkit3250_defconfig | 2 - configs/dkb_defconfig | 2 - configs/gplugd_defconfig | 2 - configs/hawkboard_defconfig | 4 - configs/hawkboard_uart_defconfig | 5 - configs/imx31_phycore_defconfig | 2 - configs/imx31_phycore_eet_defconfig | 3 - configs/jadecpu_defconfig | 2 - configs/mx31ads_defconfig | 2 - configs/tnetv107x_evm_defconfig | 2 - configs/zmx25_defconfig | 2 - doc/README.scrapyard | 47 +- drivers/net/Makefile | 2 - drivers/net/armada100_fec.c | 726 --------------------- drivers/net/armada100_fec.h | 209 ------ drivers/net/ks8695eth.c | 229 ------- drivers/serial/Makefile | 2 - drivers/serial/lpc32xx_hsuart.c | 89 --- drivers/serial/serial.c | 4 - drivers/serial/serial_ks8695.c | 121 ---- drivers/spi/Makefile | 1 - drivers/spi/armada100_spi.c | 203 ------ drivers/usb/host/Makefile | 1 - drivers/usb/host/ehci-armada100.c | 48 -- drivers/usb/host/utmi-armada100.c | 80 --- drivers/video/Makefile | 1 - drivers/video/mb86r0xgdc.c | 168 ----- drivers/watchdog/Makefile | 1 - drivers/watchdog/tnetv107x_wdt.c | 165 ----- include/configs/a320evb.h | 211 ------ include/configs/aspenite.h | 55 -- include/configs/cm4008.h | 104 --- include/configs/cm41xx.h | 104 --- include/configs/devkit3250.h | 101 --- include/configs/dkb.h | 51 -- include/configs/gplugd.h | 134 ---- include/configs/hawkboard.h | 220 ------- include/configs/imx31_phycore.h | 202 ------ include/configs/jadecpu.h | 273 -------- include/configs/mx31ads.h | 188 ------ include/configs/tnetv107x_evm.h | 139 ---- include/configs/zmx25.h | 162 ----- include/netdev.h | 2 - include/serial.h | 4 +- 178 files changed, 31 insertions(+), 13228 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/Makefile delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/aemif.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/clock.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/init.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/mux.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/timer.c delete mode 100644 arch/arm/cpu/arm920t/a320/Makefile delete mode 100644 arch/arm/cpu/arm920t/a320/reset.S delete mode 100644 arch/arm/cpu/arm920t/a320/timer.c delete mode 100644 arch/arm/cpu/arm920t/ks8695/Makefile delete mode 100644 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm920t/ks8695/timer.c delete mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile delete mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c delete mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c delete mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c delete mode 100644 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arch/arm/include/asm/arch-pantheon/cpu.h delete mode 100644 arch/arm/include/asm/arch-pantheon/gpio.h delete mode 100644 arch/arm/include/asm/arch-pantheon/mfp.h delete mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/clock.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/hardware.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/mux.h delete mode 100644 board/Marvell/aspenite/Kconfig delete mode 100644 board/Marvell/aspenite/MAINTAINERS delete mode 100644 board/Marvell/aspenite/Makefile delete mode 100644 board/Marvell/aspenite/aspenite.c delete mode 100644 board/Marvell/dkb/Kconfig delete mode 100644 board/Marvell/dkb/MAINTAINERS delete mode 100644 board/Marvell/dkb/Makefile delete mode 100644 board/Marvell/dkb/dkb.c delete mode 100644 board/Marvell/gplugd/Kconfig delete mode 100644 board/Marvell/gplugd/MAINTAINERS delete mode 100644 board/Marvell/gplugd/Makefile delete mode 100644 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mode 100644 include/configs/devkit3250.h delete mode 100644 include/configs/dkb.h delete mode 100644 include/configs/gplugd.h delete mode 100644 include/configs/hawkboard.h delete mode 100644 include/configs/imx31_phycore.h delete mode 100644 include/configs/jadecpu.h delete mode 100644 include/configs/mx31ads.h delete mode 100644 include/configs/tnetv107x_evm.h delete mode 100644 include/configs/zmx25.h -- 1.9.1

3 14

[U-Boot] [PATCH] mtd: atmel_nand: according to pmecc version to perform 0xff page correction
by Josh Wu 10 Feb '15

10 Feb '15

As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip can generate 0xff pmecc ECC value for all 0xff sector. According to this, add PMECC version check, if it's SAMA5D4 then we always let PMECC hardware to correct it. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- drivers/mtd/nand/atmel_nand.c | 9 +++++++++ drivers/mtd/nand/atmel_nand_ecc.h | 20 ++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 620b6e8..b16e3aa 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -44,6 +44,7 @@ struct atmel_nand_host { u8 pmecc_corr_cap; u16 pmecc_sector_size; u32 pmecc_index_table_offset; + u32 pmecc_version; int pmecc_bytes_per_sector; int pmecc_sector_number; @@ -486,6 +487,10 @@ static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf, int i, err_nbr, eccbytes; uint8_t *buf_pos; + /* SAMA5D4 PMECC IP can correct errors for all 0xff page */ + if (host->pmecc_version >= PMECC_VERSION_SAMA5D4) + goto normal_check; + eccbytes = nand_chip->ecc.bytes; for (i = 0; i < eccbytes; i++) if (ecc[i] != 0xff) @@ -961,6 +966,10 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, nand->ecc.write_page = atmel_nand_pmecc_write_page; nand->ecc.strength = cap; + /* Check the PMECC ip version */ + host->pmecc_version = pmecc_readl(host->pmerrloc, version); + dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version); + atmel_pmecc_core_init(mtd); return 0; diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h index eac860d..b2d2682 100644 --- a/drivers/mtd/nand/atmel_nand_ecc.h +++ b/drivers/mtd/nand/atmel_nand_ecc.h @@ -123,6 +123,20 @@ struct pmecc_errloc_regs { u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */ u32 el[24]; /* 0x8C-0xE8 Error Location Registers */ u32 reserved1[5]; /* 0xEC-0xFC Reserved */ + + /* + * 0x100-0x1F8: + * Reserved for AT91SAM9X5, AT91SAM9N12. + * HSMC registers for SAMA5D3, SAMA5D4. + */ + u32 reserved2[63]; + + /* + * 0x1FC: + * PMECC version for AT91SAM9X5, AT91SAM9N12. + * HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version. + */ + u32 version; }; /* For Error Location Configuration Register */ @@ -137,6 +151,12 @@ struct pmecc_errloc_regs { #define PMERRLOC_ERR_NUM_MASK (0x1f << 8) #define PMERRLOC_CALC_DONE (1 << 0) +/* PMECC IP version */ +#define PMECC_VERSION_SAMA5D4 0x113 +#define PMECC_VERSION_SAMA5D3 0x112 +#define PMECC_VERSION_AT91SAM9N12 0x102 +#define PMECC_VERSION_AT91SAM9X5 0x101 + /* Galois field dimension */ #define PMECC_GF_DIMENSION_13 13 #define PMECC_GF_DIMENSION_14 14 -- 1.9.1

4 9

[U-Boot] [PATCH v2] imx6: Added DEK blob generator command
by Ulises.Cardenas＠freescale.com 09 Feb '15

09 Feb '15

From: Raul Cardenas <Ulises.Cardenas(a)freescale.com> Freescale's SEC block has built-in Data Encryption Key(DEK) Blob Protocol which provides a method for protecting a DEK for non-secure memory storage. SEC block protects data in a data structure called a Secret Key Blob, which provides both confidentiality and integrity protection. Every time the blob encapsulation is executed, a SHA-256 key is randomly generated to encrypt the DEK. This key is itself encrypted with the OTP Secret key from SoC. The ending blob consists of the encrypted SHA-256 key, the encrypted DEK, and a 16-bit MAC. During decapsulation, the reverse process is performed to get back the original DEK. A caveat to the blob decapsulation process, is that the DEK is decrypted in secure-memory and can only be read by FSL SEC HW. The DEK is used to decrypt data during encrypted boot. Commands added -------------- dek_blob - encapsulating DEK as a cryptgraphic blob Commands Syntax --------------- dek_blob src dst len Encapsulate and create blob of a len-bits DEK at address src and store the result at address dst. Signed-off-by: Raul Cardenas <Ulises.Cardenas(a)freescale.com> Signed-off-by: Nitin Garg <nitin.garg(a)freescale.com> --- Changes in v2: -Remove weak symbol as recommended by Ruchika arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/cmd_dek.c | 89 +++++++++++++++++++ arch/arm/imx-common/timer.c | 17 ++++ arch/arm/include/asm/arch-mx6/imx-regs.h | 4 + doc/README.mxc_hab | 48 ++++++++++ drivers/crypto/fsl/Makefile | 2 +- drivers/crypto/fsl/desc.h | 15 ++++ drivers/crypto/fsl/fsl_blob.c | 50 +++++++++++ drivers/crypto/fsl/jobdesc.c | 142 +++++++++++++++++++++++++++++- drivers/crypto/fsl/jobdesc.h | 5 ++ drivers/crypto/fsl/jr.c | 24 ++++- include/fsl_sec.h | 60 +++++++++++++ 12 files changed, 451 insertions(+), 6 deletions(-) create mode 100644 arch/arm/imx-common/cmd_dek.c diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 25a9d4c..606482f 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o endif obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o +obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o quiet_cmd_cpp_cfg = CFGS $@ cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $< diff --git a/arch/arm/imx-common/cmd_dek.c b/arch/arm/imx-common/cmd_dek.c new file mode 100644 index 0000000..1a3a996a --- /dev/null +++ b/arch/arm/imx-common/cmd_dek.c @@ -0,0 +1,89 @@ +/* + * Command for encapsulating DEK blob + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <malloc.h> +#include <asm/byteorder.h> +#include <linux/compiler.h> +#include <fsl_sec.h> +#include <asm/arch/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** +* blob_dek() - Encapsulate the DEK as a blob using CAM's Key +* @src: - Address of data to be encapsulated +* @dst: - Address of data to be encapsulated +* @len: - Size of data to be encapsulated +* +* Returns zero on success,and negative on error. +*/ +static int blob_encap_dek(u8 *src, u8 *dst, u32 len) +{ + int ret = 0; + u32 jr_size = 4; + + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c); + if (out_jr_size != jr_size) { + hab_caam_clock_enable(1); + sec_init(); + } + + if (!((len == 128)|(len == 192)|(len == 256))) { + debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); + return -1; + } + + len /= 8; + ret = blob_dek(src, dst, len); + + return ret; +} + +/** + * do_dek_blob() - Handle the "dek_blob" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_dek_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + uint32_t src_addr, dst_addr, len; + uint8_t *src_ptr, *dst_ptr; + int ret = 0; + + if (argc != 4) + return CMD_RET_USAGE; + + src_addr = simple_strtoul(argv[1], NULL, 16); + dst_addr = simple_strtoul(argv[2], NULL, 16); + len = simple_strtoul(argv[3], NULL, 10); + + src_ptr = (uint8_t *)src_addr; + dst_ptr = (uint8_t *)dst_addr; + + ret = blob_encap_dek(src_ptr, dst_ptr, len); + + return ret; +} + +/***************************************************/ +static char dek_blob_help_text[] = + "src dst len - Encapsulate and create blob of data\n" + " $len bits long at address $src and\n" + " store the result at address $dst.\n"; + +U_BOOT_CMD( + dek_blob, 4, 1, do_dek_blob, + "Data Encryption Key blob encapsulation", + dek_blob_help_text +); diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index 65ef60b..e522990 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -176,3 +176,20 @@ ulong get_tbclk(void) { return gpt_get_clk(); } + +/* + * This function is intended for SHORT delays only. + * It will overflow at around 10 seconds @ 400MHz, + * or 20 seconds @ 200MHz. + */ +unsigned long usec2ticks(unsigned long usec) +{ + ulong ticks; + + if (usec < 1000) + ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000; + else + ticks = ((usec / 10) * (get_tbclk() / 100000)); + + return ticks; +} diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index c968600..8642021 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -215,6 +215,10 @@ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) + +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR) +#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000) + #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab index 43e64a2..46ed0df 100644 --- a/doc/README.mxc_hab +++ b/doc/README.mxc_hab @@ -46,3 +46,51 @@ cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx NOTE: U-Boot_CSF.bin needs to be padded to the value specified in the imximage.cfg file. + +Setup U-Boot Image for Encrypted Boot +------------------------------------- +An authenticated U-boot image is used as starting point for +Encrypted Boot. The image is encrypted by Freescale's Code +Signing Tool (CST). The CST replaces only the image data of +u-boot.imx with the encrypted data. The Initial Vector Table, +DCD, and Boot data, remains in plaintext. + +The image data is encrypted with a Encryption Key (DEK). +Therefore, this key is needed to decrypt the data during the +booting process. The DEK is protected by wrapping it in a Blob, +which needs to be appended to the U-boot image and specified in +the CSF file. + +The DEK blob is generated by an authenticated U-boot image with +the dek_blob cmd enabled. The image used for DEK blob generation +needs to have the following configurations enabled: + +CONFIG_SECURE_BOOT +CONFIG_SYS_FSL_SEC_COMPAT 4 /* HAB version */ +CONFIG_FSL_CAAM +CONFIG_CMD_DEKBLOB + +Note: The encrypted boot feature is only supported by HABv4 or +greater. + +The dek_blob command then can be used to generate the DEK blob of +a DEK previously loaded in memory. The command is used as follows: + +dek_blob <DEK address> <Output Address> <Key Size in Bits> +example: dek_blob 0x10800000 0x10801000 192 + +The resulting DEK blob then is used to construct the encrypted +U-boot image. Note that the blob needs to be transfered back +to the host.Then the following commands are used to construct +the final image. + +objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0x00 \ + U-Boot_CSF.bin U-Boot_CSF_pad.bin +cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx +objcopy -I binary -O binary --pad-to <blob_dst> --gap-fill=0x00 \ + u-boot-signed.imx u-boot-signed-pad.bin +cat u-boot-signed-pad.imx DEK_blob.bin > u-boot-encrypted.imx + + NOTE: u-boot-signed.bin needs to be padded to the value + equivalent to the address in which the DEK blob is specified + in the CSF. diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index c0cf642..4aa91e4 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -8,5 +8,5 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o -obj-$(CONFIG_CMD_BLOB) += fsl_blob.o +obj-$(CONFIG_CMD_BLOB)$(CONFIG_CMD_DEKBLOB) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 504f2b0..bb82734 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -12,11 +12,18 @@ #ifndef DESC_H #define DESC_H +#define KEY_BLOB_SIZE 32 +#define MAC_SIZE 16 + /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */ #define MAX_CAAM_DESCSIZE 64 +/* Size of DEK Blob descriptor, inclusive of header */ +#define DEK_BLOB_DESCSIZE 9 + /* Block size of any entity covered/uncovered with a KEK/TKEK */ #define KEK_BLOCKSIZE 16 + /* * Supported descriptor command types as they show up * inside a descriptor command word. @@ -273,6 +280,13 @@ #define LDLEN_SET_OFIFO_OFFSET_MASK (3 << LDLEN_SET_OFIFO_OFFSET_SHIFT) /* + * AAD Definitions + */ +#define AES_KEY_SHIFT 8 +#define LD_CCM_MODE (0x66) +#define KEY_AES_SRC (0x55 << AES_KEY_SHIFT) + +/* * FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE * Command Constructs */ @@ -418,6 +432,7 @@ #define OP_PCLID_MASK (0xff << 16) /* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */ +#define OP_PCLID_SECMEM (0x08) #define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT) #define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT) #define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT) diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index bc01075..f9dc85a 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -7,6 +7,7 @@ #include <common.h> #include <malloc.h> +#include <fsl_sec.h> #include "jobdesc.h" #include "desc.h" #include "jr.h" @@ -59,3 +60,52 @@ int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) free(desc); return ret; } + +#ifdef CONFIG_CMD_DEKBLOB +int blob_dek(u8 *src, u8 *dst, u8 len) +{ + int ret, size, i = 0; + u32 *desc; + + int out_sz = WRP_HDR_SIZE + len + KEY_BLOB_SIZE + MAC_SIZE; + + puts("\nEncapsulating provided DEK to form blob\n"); + desc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * DEK_BLOB_DESCSIZE); + if (!desc) { + debug("Not enough memory for descriptor allocation\n"); + return -1; + } + + ret = inline_cnstr_jobdesc_blob_dek(desc, src, dst, len); + if (ret) { + debug("Error in Job Descriptor Construction: %d\n", ret); + } else { + size = roundup(sizeof(uint32_t) * DEK_BLOB_DESCSIZE, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + size); + size = roundup(sizeof(uint8_t) * out_sz, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + + ret = run_descriptor_jr(desc); + } + + if (ret) + debug("Error in Encapsulation %d\n", ret); + + size = roundup(out_sz, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst+size); + + /* Print DEK Blob */ + puts("DEK Blob\n"); + for (i = 0; i < out_sz; i++) + printf("%02X", ((uint8_t *)dst)[i]); + + puts("\n\n"); + + free(desc); + return ret; +} +#endif diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index cc0dced..4dc73ae 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -9,12 +9,150 @@ */ #include <common.h> +#include <fsl_sec.h> #include "desc_constr.h" #include "jobdesc.h" #include "rsa_caam.h" -#define KEY_BLOB_SIZE 32 -#define MAC_SIZE 16 +#ifdef CONFIG_MX6 +/*! + * Secure memory run command. + * + * @param sec_mem_cmd Secure memory command register + * @return cmd_status Secure memory command status register + */ +uint32_t secmem_set_cmd(uint32_t sec_mem_cmd) +{ + uint32_t temp_reg; + + sec_out32(CAAM_SMCJR0, sec_mem_cmd); + + do { + temp_reg = sec_in32(CAAM_SMCSJR0); + } while (temp_reg & CMD_COMPLETE); + + return temp_reg; +} + +/*! + * CAAM page allocation. + * + * @param page Number of the page to allocate. + * @param partition Number of the partition to allocate. + */ +uint32_t caam_page_alloc(uint8_t page_num, uint8_t partition_num) +{ + uint32_t temp_reg; + + /* + * De-Allocate partition_num if already allocated to ARM core + */ + if (sec_in32(CAAM_SMPO_0) & PARTITION_OWNER(partition_num)) { + temp_reg = secmem_set_cmd(PARTITION(partition_num) | + CMD_PART_DEALLOC); + if (temp_reg & SMCSJR_AERR) { + printf("Error: De-allocation status 0x%X\n", temp_reg); + return ERROR_IN_PAGE_ALLOC; + } + } + + /* set the access rights to allow full access */ + sec_out32(CAAM_SMAG1JR0(partition_num), 0xF); + sec_out32(CAAM_SMAG2JR0(partition_num), 0xF); + sec_out32(CAAM_SMAPJR0(partition_num), 0xFF); + + /* Now need to allocate partition_num of secure RAM. */ + /* De-Allocate page_num by starting with a page inquiry command */ + temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY); + + /* if the page is owned, de-allocate it */ + if ((temp_reg & SMCSJR_PO) == PAGE_OWNED) { + temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_PAGE_DEALLOC); + if (temp_reg & SMCSJR_AERR) { + printf("Error: Allocation status 0x%X\n", temp_reg); + return ERROR_IN_PAGE_ALLOC; + } + } + + /* Allocate page_num to partition_num */ + temp_reg = secmem_set_cmd(PAGE(page_num) | PARTITION(partition_num) + | CMD_PAGE_ALLOC); + if (temp_reg & SMCSJR_AERR) { + printf("Error: Allocation status 0x%X\n", temp_reg); + return ERROR_IN_PAGE_ALLOC; + } + /* page inquiry command to ensure that the page was allocated */ + temp_reg = secmem_set_cmd(PAGE(page_num) | CMD_INQUIRY); + + /* if the page is not owned => problem */ + if ((temp_reg & SMCSJR_PO) != PAGE_OWNED) { + printf("Allocation of page %d in partition %d failed 0x%X\n", + temp_reg, page_num, partition_num); + + return ERROR_IN_PAGE_ALLOC; + } + + return 0; +} + +uint32_t inline_cnstr_jobdesc_blob_dek(uint32_t *desc, uint8_t *plain_txt, + uint8_t *dek_blob, uint32_t in_sz) +{ + uint32_t ret = 0; + u32 aad_w1, aad_w2; + /* output blob will have 32 bytes key blob in beginning and + * 16 byte HMAC identifier at end of data blob */ + uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE; + /* Setting HDR for blob */ + uint8_t wrapped_key_hdr[8] = {HDR_TAG, 0x00, WRP_HDR_SIZE + out_sz, + HDR_PAR, HAB_MOD, HAB_ALG, in_sz, HAB_FLG}; + + /* initialize the blob array */ + memset(dek_blob, 0, out_sz + 8); + /* Copy the header into the DEK blob buffer */ + memcpy((uint32_t *)dek_blob, wrapped_key_hdr, sizeof(wrapped_key_hdr)); + + /* allocating secure memory */ + ret = caam_page_alloc(PAGE_1, PARTITION_1); + if (ret) + return ret; + + /* Write DEK to secure memory */ + memcpy((uint32_t *)SEC_MEM_PAGE1, (uint32_t *)plain_txt, in_sz); + + unsigned long start = (unsigned long)SEC_MEM_PAGE1 & + ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + 0x1000, ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + + /* Now configure the access rights of the partition */ + sec_out32(CAAM_SMAG1JR0(PARTITION_1), KS_G1); /* set group 1 */ + sec_out32(CAAM_SMAG2JR0(PARTITION_1), 0); /* clear group 2 */ + sec_out32(CAAM_SMAPJR0(PARTITION_1), PERM); /* set perm & locks */ + + /* construct aad for AES */ + aad_w1 = (in_sz << OP_ALG_ALGSEL_SHIFT) | KEY_AES_SRC | LD_CCM_MODE; + aad_w2 = 0x0; + + init_job_desc(desc, 0); + + append_cmd(desc, CMD_LOAD | CLASS_2 | KEY_IMM | KEY_ENC | + (0x0c << LDST_OFFSET_SHIFT) | 0x08); + + append_u32(desc, aad_w1); + + append_u32(desc, aad_w2); + + append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); + + append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR); + + append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB | + OP_PCLID_SECMEM); + + return ret; +} +#endif void inline_cnstr_jobdesc_hash(uint32_t *desc, const uint8_t *msg, uint32_t msgsz, uint8_t *digest, diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h index 84b3edd..d20c18c 100644 --- a/drivers/crypto/fsl/jobdesc.h +++ b/drivers/crypto/fsl/jobdesc.h @@ -14,6 +14,11 @@ #define KEY_IDNFR_SZ_BYTES 16 +#ifdef CONFIG_CMD_DEKBLOB +uint32_t inline_cnstr_jobdesc_blob_dek(uint32_t *desc, uint8_t *plain_txt, + uint8_t *enc_blob, uint32_t in_sz); +#endif + void inline_cnstr_jobdesc_hash(uint32_t *desc, const uint8_t *msg, uint32_t msgsz, uint8_t *digest, u32 alg_type, uint32_t alg_size, int sg_tbl); diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index f9d4938..8b76c1b 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -90,11 +90,13 @@ static int jr_init(void) jr.liodn = DEFAULT_JR_LIODN; #endif jr.size = JR_SIZE; - jr.input_ring = (dma_addr_t *)malloc(JR_SIZE * sizeof(dma_addr_t)); + jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + JR_SIZE * sizeof(dma_addr_t)); if (!jr.input_ring) return -1; jr.output_ring = - (struct op_ring *)malloc(JR_SIZE * sizeof(struct op_ring)); + (struct op_ring *)memalign(ARCH_DMA_MINALIGN, + JR_SIZE * sizeof(struct op_ring)); if (!jr.output_ring) return -1; @@ -163,13 +165,22 @@ static int jr_enqueue(uint32_t *desc_addr, CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0) return -1; - jr.input_ring[head] = desc_phys_addr; jr.info[head].desc_phys_addr = desc_phys_addr; jr.info[head].desc_addr = (uint32_t)desc_addr; jr.info[head].callback = (void *)callback; jr.info[head].arg = arg; jr.info[head].op_done = 0; + unsigned long start = (unsigned long)jr.info & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + sizeof(struct jr_info) * JR_SIZE , + ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + + jr.input_ring[head] = desc_phys_addr; + start = (unsigned long)jr.input_ring & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN(start + sizeof(dma_addr_t)*JR_SIZE , ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + jr.head = (head + 1) & (jr.size - 1); sec_out32(&regs->irja, 1); @@ -187,6 +198,13 @@ static int jr_dequeue(void) void *arg = NULL; while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { + unsigned long start = (unsigned long)jr.output_ring & + ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + + sizeof(struct op_ring)*JR_SIZE, + ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + found = 0; dma_addr_t op_desc = jr.output_ring[jr.tail].desc; diff --git a/include/fsl_sec.h b/include/fsl_sec.h index aa850a3..95fbb6b 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -11,6 +11,13 @@ #include <common.h> #include <asm/io.h> +#ifdef CONFIG_ARM +#define sec_in32(a) __raw_readl(a) +#define sec_out32(a, v) __raw_writel(v, a) +#define sec_in16(a) __raw_readw(a) +#define sec_clrbits32 clrbits_le32 +#define sec_setbits32 setbits_le32 +#elif CONFIG_PPC #ifdef CONFIG_SYS_FSL_SEC_LE #define sec_in32(a) in_le32(a) #define sec_out32(a, v) out_le32(a, v) @@ -26,6 +33,7 @@ #else #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined #endif +#endif /* ARCHITECURE */ /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 @@ -175,7 +183,59 @@ struct jr_regs { u32 jrcr; }; +#ifdef CONFIG_MX6 + +#define SMCSJR_PO (3 << 6) +#define SMCSJR_AERR (3 << 12) +#define SMCSJR_CERR (3 << 14) +#define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC +#define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4 +#define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc +#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16) +#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16) +#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16) + +#define ERROR_IN_PAGE_ALLOC (1) +#define CMD_PAGE_ALLOC 0x1 +#define CMD_PAGE_DEALLOC 0x2 +#define CMD_PART_DEALLOC 0x3 +#define CMD_INQUIRY 0x5 +#define CMD_COMPLETE (3 << 14) +#define PAGE_AVAILABLE 0 +#define PAGE_OWNED (3 << 6) +#define PAGE(x) (x << 16) +#define PARTITION(x) (x << 8) +#define PARTITION_OWNER(x) (0x3 << (x*2)) + +/* 4kbyte pages */ +#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR +#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000) +#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000) +#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000) + +#define JR_MID 2 /* Matches ROM configuration */ +#define KS_G1 (1 << JR_MID) /* CAAM only */ +#define PERM 0x0000B008 /* Clear on release, lock SMAP + * lock SMAG group 1 Blob */ + +/* HAB WRAPPED KEY header */ +#define WRP_HDR_SIZE 0x08 +#define HDR_TAG 0x81 +#define HDR_PAR 0x41 +/* HAB WRAPPED KEY Data */ +#define HAB_MOD 0x66 +#define HAB_ALG 0x55 +#define HAB_FLG 0x00 + +#define PARTITION_1 1 +#define PAGE_1 1 + +#endif + int sec_init(void); + +int blob_dek(u8 *src, u8 *dst, u8 len); + #endif #endif /* __FSL_SEC_H */ -- 1.7.9.5

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Re: [U-Boot] [GIT PULL] microblaze changes
by Tom Rini 09 Feb '15

09 Feb '15

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 02/09/2015 09:28 AM, Michal Simek wrote: > Hi Tom, > > please consider to add these microblaze changes to your tree. > It is moving Microblaze to use generic board support. > > I have also added one patch from Andreas which is the part avr32 series > because it is also needed for Microblaze. > > The first patch in this series (Move drram_init()) was asked by Simon > and it was also reviewed by him. > > Thanks, > Michal > > The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08: > > Merge branch 'master' of git://git.denx.de/u-boot-ubi (2015-02-04 13:30:00 -0500) > > are available in the git repository at: > > > git://www.denx.de/git/u-boot-microblaze.git microblaze > > for you to fetch changes up to 7f33899221e4235900760add69ffbb5f66f1229d: > > microblaze: spl: Add LISTS to linker script (2015-02-09 15:13:12 +0100) > > ---------------------------------------------------------------- > Andreas Bießmann (1): > common/board_r: manual relocation for cmd table > > Michal Simek (19): > common: Move dram_init() declaration to common location > microblaze: Fix stack usage in interrupt handler > microblaze: Show return address from exception > microblaze: Fix coding style in exception.c > microblaze: Remove DEBUG_INT macro and use debug() instead > microblaze: Fix coding style > microblaze: Add debug message about enabling interrupts > microblaze: Remove unneeded data section adding from DTB > microblaze: Use standard interrupt_init() function > microblaze: Remove unused asm label > microblaze: Fix gd_t address which is placed at the end of BRAM > microblaze: Enable SPL_NOR support when FLASH_BASE is setup > microblaze: Move architecture to use generic board init > microblaze: Speedup code copy > bdinfo: Show information about fdt blob via bdinfo > microblaze: Do not use CONFIG_SYS_GENERIC_GLOBAL_DATA > microblaze: Add support for CONFIG_SYS_MALLOC_F_LEN > microblaze: spl: Do not call mem_malloc_init and use early alloc > microblaze: spl: Add LISTS to linker script > > arch/arm/include/asm/u-boot-arm.h | 1 - > arch/microblaze/config.mk | 5 ++ > arch/microblaze/cpu/exception.c | 35 +++++++------- > arch/microblaze/cpu/interrupts.c | 76 ++++++++++++++--------------- > arch/microblaze/cpu/irq.S | 121 +++++++++++++++++++++++----------------------- > arch/microblaze/cpu/spl.c | 2 - > arch/microblaze/cpu/start.S | 126 +++++++++++++++++++++++++++++++++++++++++++++++- > arch/microblaze/cpu/u-boot-spl.lds | 6 +++ > arch/microblaze/cpu/u-boot.lds | 12 +++-- > arch/microblaze/include/asm/asm.h | 4 ++ > arch/microblaze/include/asm/config.h | 7 +++ > arch/microblaze/include/asm/microblaze_intc.h | 2 - > arch/microblaze/include/asm/u-boot.h | 11 +---- > arch/microblaze/lib/Makefile | 1 - > arch/microblaze/lib/board.c | 201 ----------------------------------------------------------------------------- > arch/nds32/include/asm/u-boot-nds32.h | 1 - > arch/sandbox/include/asm/u-boot-sandbox.h | 1 - > arch/x86/include/asm/u-boot-x86.h | 6 --- > board/xilinx/microblaze-generic/microblaze-generic.c | 46 ++++++++++++++++++ > common/board_f.c | 4 +- > common/board_r.c | 14 +++++- > common/cmd_bdinfo.c | 16 ++++++- > include/common.h | 1 + > include/configs/microblaze-generic.h | 101 ++++++++++----------------------------- > 24 files changed, 371 insertions(+), 429 deletions(-) > delete mode 100644 arch/microblaze/lib/board.c > > > > > [u-boot]$ ./tools/buildman/buildman -b microblaze microblaze -sSed > boards.cfg is up to date. Nothing to do. > Summary of 21 commits for 1 boards (1 thread, 8 jobs per thread) > 01: Merge branch 'master' of git://git.denx.de/u-boot-ubi > microblaze: + microblaze-generic > w+../common/spl/spl_nor.c: In function 'spl_nor_load_image': > w+../common/spl/spl_nor.c:26:10: warning: assignment discards 'const' qualifier from pointer target type [enabled by default] > 02: common: Move dram_init() declaration to common location > 03: common/board_r: manual relocation for cmd table > 04: microblaze: Fix stack usage in interrupt handler > 05: microblaze: Show return address from exception > microblaze: (for 1/1 boards) all +44.0 bss -16.0 rodata +36.0 text +24.0 > microblaze-generic: all +44 bss -16 rodata +36 text +24 > 06: microblaze: Fix coding style in exception.c > 07: microblaze: Remove DEBUG_INT macro and use debug() instead > 08: microblaze: Fix coding style > 09: microblaze: Add debug message about enabling interrupts > 10: microblaze: Remove unneeded data section adding from DTB > 11: microblaze: Use standard interrupt_init() function > 12: microblaze: Remove unused asm label > 13: microblaze: Fix gd_t address which is placed at the end of BRAM > 14: microblaze: Enable SPL_NOR support when FLASH_BASE is setup > 15: microblaze: Move architecture to use generic board init > microblaze: (for 1/1 boards) all +52380.0 bss +32.0 data +11712.0 rodata -2668.0 spl/u-boot-spl:all +36.0 spl/u-boot-spl:data +36.0 text +43304.0 > microblaze-generic: all +52380 bss +32 data +11712 rodata -2668 spl/u-boot-spl:all +36 spl/u-boot-spl:data +36 text +43304 > 16: microblaze: Speedup code copy > microblaze: (for 1/1 boards) all +4.0 text +4.0 > microblaze-generic: all +4 text +4 > 17: bdinfo: Show information about fdt blob via bdinfo > microblaze: (for 1/1 boards) all +116.0 bss -12.0 data +12.0 rodata +32.0 text +84.0 > microblaze-generic: all +116 bss -12 data +12 rodata +32 text +84 > 18: microblaze: Do not use CONFIG_SYS_GENERIC_GLOBAL_DATA > microblaze: (for 1/1 boards) all +136.0 bss +160.0 text -24.0 > microblaze-generic: all +136 bss +160 text -24 > 19: microblaze: Add support for CONFIG_SYS_MALLOC_F_LEN > microblaze: (for 1/1 boards) all +412.0 bss -8.0 data +8.0 rodata +64.0 text +348.0 > microblaze-generic: all +412 bss -8 data +8 rodata +64 text +348 > 20: microblaze: spl: Do not call mem_malloc_init and use early alloc > microblaze: (for 1/1 boards) spl/u-boot-spl:all -64.0 spl/u-boot-spl:bss +132.0 spl/u-boot-spl:text -196.0 > microblaze-generic: spl/u-boot-spl:all -64 spl/u-boot-spl:bss +132 spl/u-boot-spl:text -196 > 21: microblaze: spl: Add LISTS to linker script Applied to u-boot/master, thanks! - -- Tom -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAEBAgAGBQJU2RhMAAoJENk4IS6UOR1WK1kP/RnIOliSgzX6LlNHd7Yh75KW 6zb+YjKQ1OkPUUuWflWBVmF/ItxjTdHg1kKtFxzoPW0PBrfwkln6CsWwkkASFosu nDKea+dxtwFFQcHWiw4DxQ2ykE8vrDLvxH0pwKZodJT7JIuEr0LMUzocuZp/wyAq 7TJDSGIHeyMyOEX2RrJc/7TV0mIBonEEAbEUAIuPDjuJ0664slfwDqwRg8t2CeC/ mnEJ+YJcZ4h9a+10hBAQsyz+GvlhOdgL+daeemn2GiqBXn/O0qxX/1GZ8KGfr423 9IgBGMqthkNQK9y0w04PBbzSt6FuSjyLlhKls5+3TnrOMYJM5dBbwqaDLt0SGW3Z IOw8TTGAJ5roKMyQy6aaCDbM2ElC3KyHnpczx7teTfyUm1CPrq0TCkjuHBWpMa/h bog2GDAB7X8KIDv3F9rbXgnG7xftz0SEw/WNjitporIR6sDbhgZxH1wgyDoSWHq/ 0B/uA7bENujhJxBjkAqx154q38MgL9yugrAHHTj+bz3uI4lETcTaHCN6JDooArjN Lpd7LfzSGAyRefioJL8R0OIPo6sCm4UMlSPZDOPD+qSl4W8aqxn6Vpl0sUoCfPdC 3lLclwIey+NGtSpdsvxGyIKuLHtWgWwxBoyw6tq4VajKi7HMGxVV5g+Y8VfDcZlH k3vtvkn7SBXdDNHEoi97 =8zBx -----END PGP SIGNATURE-----

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[U-Boot] [PATCH] kwbimage: Make the Makefile pass in CONFIG_SYS_SPI_U_BOOT_OFFS
by Tom Rini 09 Feb '15

09 Feb '15

We can't use config.h directly as some platforms include headers that aren't safe to use in normal Linux userland. Signed-off-by: Tom Rini <trini(a)ti.com> --- tools/Makefile | 4 ++++ tools/kwbimage.c | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index 6e1ce79..e4b23eb 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -115,6 +115,10 @@ ifdef CONFIG_FIT_SIGNATURE HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE endif +ifdef CONFIG_SYS_SPI_U_BOOT_OFFS +HOSTCFLAGS_kwbimage.o += -DCONFIG_SYS_SPI_U_BOOT_OFFS=$(CONFIG_SYS_SPI_U_BOOT_OFFS) +endif + # MXSImage needs LibSSL ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),) HOSTLOADLIBES_mkimage += -lssl -lcrypto diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 28ce1e4..de5c808 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -16,7 +16,6 @@ #include <image.h> #include <stdint.h> #include "kwbimage.h" -#include <config.h> #define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1)) -- 1.7.9.5

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[U-Boot] Please pull u-boot-marvell master
by Luka Perkov 09 Feb '15

09 Feb '15

Hi Tom, this series contains the last bits of pending kirkwood/mvebu patches that I'm aware of. The changes from Gerald are minimal and I've merged Stefan's series which have reached v3 on the list. The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08: Merge branch 'master' of git://git.denx.de/u-boot-ubi (2015-02-04 13:30:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-marvell.git for you to fetch changes up to 68102b81e8fb699087ec5757a75676c6c65af3fd: arm: mvebu: maxbcm: Fix compilation warning and add Spansion SPI NOR support (2015-02-06 17:25:08 +0100) ---------------------------------------------------------------- DrEagle (3): kirkwood: sheevaplug: fix style kirkwood: sheevaplug: fix multiple defines kirkwood: sheevaplug: add FDT support Stefan Roese (11): arm: armada-xp: Change built target to include the SPL binary as bin_hdr arm: mvebu: Placeholder bin_hdr file can now be removed arm: maxbcm: Enable SPL to include DDR training code into U-Boot arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot Makefile: Add another kwb build target used on Marvell Armada-XP (AXP) tools: kwbimage: Support u-boot.img padding to CONFIG_SYS_SPI_U_BOOT_OFFS scripts/Makefile.spl: Add MVEBU DDR code to SPL arm: armada-xp: Add SPL support used to include the DDR training code arm: mvebu: Add Serdes PHY config code arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr arm: mvebu: maxbcm: Fix compilation warning and add Spansion SPI NOR support Makefile | 6 + arch/arm/Kconfig | 2 + arch/arm/cpu/armv7/armada-xp/Makefile | 2 + arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S | 62 + arch/arm/cpu/armv7/armada-xp/spl.c | 38 + arch/arm/include/asm/arch-armada-xp/config.h | 4 + arch/arm/include/asm/arch-armada-xp/cpu.h | 16 + arch/arm/mvebu-common/Makefile | 2 + arch/arm/mvebu-common/serdes/Makefile | 6 + arch/arm/mvebu-common/serdes/board_env_spec.h | 262 ++++ arch/arm/mvebu-common/serdes/high_speed_env_lib.c | 1572 +++++++++++++++++++ arch/arm/mvebu-common/serdes/high_speed_env_spec.c | 185 +++ arch/arm/mvebu-common/serdes/high_speed_env_spec.h | 87 ++ arch/arm/mvebu-common/u-boot-spl.lds | 57 + board/Marvell/db-mv784mp-gp/binary.0 | 17 - board/Marvell/db-mv784mp-gp/kwbimage.cfg | 2 +- board/maxbcm/binary.0 | 17 - board/maxbcm/kwbimage.cfg | 2 +- board/maxbcm/maxbcm.c | 85 +- configs/db-mv784mp-gp_defconfig | 5 +- configs/maxbcm_defconfig | 5 +- drivers/ddr/mvebu/Makefile | 14 + drivers/ddr/mvebu/ddr3_axp.h | 510 +++++++ drivers/ddr/mvebu/ddr3_axp_config.h | 146 ++ drivers/ddr/mvebu/ddr3_axp_mc_static.h | 284 ++++ drivers/ddr/mvebu/ddr3_axp_training_static.h | 770 ++++++++++ drivers/ddr/mvebu/ddr3_axp_vars.h | 226 +++ drivers/ddr/mvebu/ddr3_dfs.c | 1552 +++++++++++++++++++ drivers/ddr/mvebu/ddr3_dqs.c | 1374 +++++++++++++++++ drivers/ddr/mvebu/ddr3_hw_training.c | 1115 ++++++++++++++ drivers/ddr/mvebu/ddr3_hw_training.h | 392 +++++ drivers/ddr/mvebu/ddr3_init.c | 1219 +++++++++++++++ drivers/ddr/mvebu/ddr3_init.h | 143 ++ drivers/ddr/mvebu/ddr3_patterns_64bit.h | 924 ++++++++++++ drivers/ddr/mvebu/ddr3_pbs.c | 1592 ++++++++++++++++++++ drivers/ddr/mvebu/ddr3_read_leveling.c | 1214 +++++++++++++++ drivers/ddr/mvebu/ddr3_sdram.c | 669 ++++++++ drivers/ddr/mvebu/ddr3_spd.c | 1300 ++++++++++++++++ drivers/ddr/mvebu/ddr3_write_leveling.c | 1366 +++++++++++++++++ drivers/ddr/mvebu/xor.c | 436 ++++++ drivers/ddr/mvebu/xor.h | 70 + drivers/ddr/mvebu/xor_regs.h | 103 ++ include/configs/db-mv784mp-gp.h | 49 + include/configs/maxbcm.h | 49 + include/configs/sheevaplug.h | 7 +- scripts/Makefile.spl | 1 + tools/kwbimage.c | 11 + 47 files changed, 17925 insertions(+), 45 deletions(-) create mode 100644 arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S create mode 100644 arch/arm/cpu/armv7/armada-xp/spl.c create mode 100644 arch/arm/mvebu-common/serdes/Makefile create mode 100644 arch/arm/mvebu-common/serdes/board_env_spec.h create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_lib.c create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.c create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.h create mode 100644 arch/arm/mvebu-common/u-boot-spl.lds delete mode 100644 board/Marvell/db-mv784mp-gp/binary.0 delete mode 100644 board/maxbcm/binary.0 create mode 100644 drivers/ddr/mvebu/Makefile create mode 100644 drivers/ddr/mvebu/ddr3_axp.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_config.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_mc_static.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_training_static.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_vars.h create mode 100644 drivers/ddr/mvebu/ddr3_dfs.c create mode 100644 drivers/ddr/mvebu/ddr3_dqs.c create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.c create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.h create mode 100644 drivers/ddr/mvebu/ddr3_init.c create mode 100644 drivers/ddr/mvebu/ddr3_init.h create mode 100644 drivers/ddr/mvebu/ddr3_patterns_64bit.h create mode 100644 drivers/ddr/mvebu/ddr3_pbs.c create mode 100644 drivers/ddr/mvebu/ddr3_read_leveling.c create mode 100644 drivers/ddr/mvebu/ddr3_sdram.c create mode 100644 drivers/ddr/mvebu/ddr3_spd.c create mode 100644 drivers/ddr/mvebu/ddr3_write_leveling.c create mode 100644 drivers/ddr/mvebu/xor.c create mode 100644 drivers/ddr/mvebu/xor.h create mode 100644 drivers/ddr/mvebu/xor_regs.h Regards, Luka

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[U-Boot] Pull request: u-boot-uniphier
by Masahiro YAMADA 09 Feb '15

09 Feb '15

Hi Tom, The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08: Merge branch 'master' of git://git.denx.de/u-boot-ubi (2015-02-04 13:30:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to 4e79908044e4ebf186464cf118497458faf0903c: ARM: UniPhier: leave the last element of boot_device_table empty (2015-02-07 00:15:03 +0900) ---------------------------------------------------------------- Masahiro Yamada (15): ARM: UniPhier: remove dummy gpio.h ARM: UniPhier: use "&&" instead of "; " in commands ARM: UniPhier: add environment variable to update images in NAND ARM: UniPhier: add a simple README file for UniPhier platform MAINTAINERS: claim maintainership of files with "uniphier" pattern ARM: UniPhier: move EEPROM device node into a separate DTS ARM: UniPhier: set I2C offset length of on-board EEPROM in DTS ARM: UniPhier: move pin_init() to board_early_init_f() ARM: UniPhier: move SPL init functions to spl_board_init() ARM: UniPhier: revive support card info ARM: UniPhier: remove unused checkboard() functions ARM: UniPhier: do not compile unnecessary objects ARM: UniPhier: enable I2C input pins for PH1-sLD8 ARM: UniPhier: refactor pinmon command ARM: UniPhier: leave the last element of boot_device_table empty MAINTAINERS | 2 +- arch/arm/cpu/armv7/uniphier/Kconfig | 11 +---- arch/arm/cpu/armv7/uniphier/Makefile | 27 +++++++---- arch/arm/cpu/armv7/uniphier/board_early_init_f.c | 22 +++++++++ arch/arm/cpu/armv7/uniphier/board_postclk_init.c | 47 ------------------ arch/arm/cpu/armv7/uniphier/cmd_pinmon.c | 15 +++--- arch/arm/cpu/armv7/uniphier/dram_init.c | 23 +-------- arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 14 +++--- arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 13 +++-- arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c | 16 ------- arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c | 6 +-- arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 14 +++--- arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c | 16 ------- arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c | 9 ++++ .../arm/cpu/armv7/uniphier/{ph1-ld4/board_info.c => print_misc_info.c} | 7 +-- arch/arm/cpu/armv7/uniphier/spl.c | 52 ++++++++++++++++++-- arch/arm/dts/uniphier-ph1-ld4-ref.dts | 7 +-- arch/arm/dts/uniphier-ph1-pro4-ref.dts | 7 +-- arch/arm/dts/uniphier-ph1-sld3-ref.dts | 7 +-- arch/arm/dts/uniphier-ph1-sld8-ref.dts | 7 +-- arch/arm/dts/uniphier-ref-daughter.dtsi | 16 +++++++ arch/arm/include/asm/arch-uniphier/boot-device.h | 2 +- arch/arm/include/asm/arch-uniphier/gpio.h | 6 --- doc/README.uniphier | 85 +++++++++++++++++++++++++++++++++ include/configs/uniphier.h | 19 +++++--- 25 files changed, 256 insertions(+), 194 deletions(-) create mode 100644 arch/arm/cpu/armv7/uniphier/board_early_init_f.c delete mode 100644 arch/arm/cpu/armv7/uniphier/board_postclk_init.c delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c rename arch/arm/cpu/armv7/uniphier/{ph1-ld4/board_info.c => print_misc_info.c} (57%) create mode 100644 arch/arm/dts/uniphier-ref-daughter.dtsi delete mode 100644 arch/arm/include/asm/arch-uniphier/gpio.h create mode 100644 doc/README.uniphier -- Best Regards Masahiro Yamada

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