February 2015 - U-Boot

[U-Boot] please pull u-boot-samsung master
by Minkyu Kang 17 Feb '15

17 Feb '15

Dear Tom, The following changes since commit bd2a4888b123713adec271d6c8040ca9f609aa2f: sunxi: configs/sunxi-common.h: Enable CONFIG_CMD_PART (2015-02-11 19:43:45 -0500) are available in the git repository at: http://git.denx.de/u-boot-samsung for you to fetch changes up to 2e82e9252695a612ab0cbf40fa0c7368515f6506: Exynos: Clock: Cleanup soc_get_periph_rate (2015-02-13 17:23:06 +0900) ---------------------------------------------------------------- Akshay Saraswat (7): Exynos5: Fix compiler warnings due to clock_get_periph_rate Exynos542x: Move exynos5420_get_pll_clk up and rename Exynos542x: Add and enable get_periph_rate support Exynos5: Fix exynos5_get_periph_rate calculations Exynos5: Use clock_get_periph_rate generic API Exynos: clock: change mask bits as per peripheral Exynos: Clock: Cleanup soc_get_periph_rate Jaehoon Chung (1): arm: exynos: fix the div value for set_mmc_clk Joonyoung Shim (5): samsung: board: support eMMC reset using DT Odroid: Add eMMC-reset node on DT Odroid-XU3: Add eMMC-reset node on DT odroid: fix g2d sclk rate EXYNOS5: Add function to enable exynos5420 usbdev phy ctrl arch/arm/cpu/armv7/exynos/clock.c | 621 ++++++++++++------------ arch/arm/cpu/armv7/exynos/power.c | 28 +- arch/arm/dts/exynos4412-odroid.dts | 5 + arch/arm/dts/exynos5422-odroidxu3.dts | 5 + arch/arm/include/asm/arch-exynos/clk.h | 4 + board/samsung/common/board.c | 28 ++ board/samsung/odroid/odroid.c | 12 +- doc/device-tree-bindings/exynos/emmc-reset.txt | 15 + 8 files changed, 383 insertions(+), 335 deletions(-) create mode 100644 doc/device-tree-bindings/exynos/emmc-reset.txt -- Thanks, Minkyu Kang.

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[U-Boot] [PATCH] imx: don't clobber reset cause
by Eric Nelson 17 Feb '15

17 Feb '15

The cause of a reset is generally useful, and shouldn't be blindly cleared in the process of displaying it as a part of the boot announcement. If a particular system wants to clear it out, this should be done later after there's an opportunity for code or boot commands to read the value. Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> --- arch/arm/imx-common/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 28ccd29..3e0a582 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -30,7 +30,6 @@ char *get_reset_cause(void) struct src *src_regs = (struct src *)SRC_BASE_ADDR; cause = readl(&src_regs->srsr); - writel(cause, &src_regs->srsr); switch (cause) { case 0x00001: -- 1.9.1

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[U-Boot] [PATCH 2/2] ot1200: add eeprom command to non-SPL build
by Christian Gmeiner 17 Feb '15

17 Feb '15

Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- include/configs/ot1200.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index c061e93..3c60b4f 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -131,6 +131,16 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC +#ifndef CONFIG_SPL +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_BUS 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#endif + /* Miscellaneous commands */ #define CONFIG_CMD_BMODE #define CONFIG_CMD_SETEXPR -- 2.1.0

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[U-Boot] [PATCH 1/2] cmd_eeprom: make it possible to define the used i2c bus
by Christian Gmeiner 17 Feb '15

17 Feb '15

A SoC like the i.MX6 supports more then one i2c bus. In oder to be able to use the eeprom command add a new define to specify the i2c bus to use. If CONFIG_SYS_I2C_EEPROM_BUS is not defined there is no functional change, else a call to i2c_set_bus_num(..) is done before calling i2c_read(..) and i2c_write(..). Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- README | 3 +++ common/cmd_eeprom.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/README b/README index ba57dc5..f38ab15 100644 --- a/README +++ b/README @@ -4341,6 +4341,9 @@ to save the current settings. If defined, specified the chip address of the EEPROM device. The default address is zero. + - CONFIG_SYS_I2C_EEPROM_BUS: + If defined, specified the i2c bus of the EEPROM device. + - CONFIG_SYS_EEPROM_PAGE_WRITE_BITS: If defined, the number of bits used to address bytes in a single page in the EEPROM device. A 64 byte page, for example diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index 29f0f1f..e9904cd 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -161,6 +161,9 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) spi_read (addr, alen, buffer, len); #else +#if defined(CONFIG_SYS_I2C_EEPROM_BUS) + i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); +#endif if (i2c_read(addr[0], offset, alen - 1, buffer, len)) rcode = 1; #endif @@ -339,6 +342,9 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn /* Write is enabled ... now write eeprom value. */ #endif +#if defined(CONFIG_SYS_I2C_EEPROM_BUS) + i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); +#endif if (i2c_write(addr[0], offset, alen - 1, buffer, len)) rcode = 1; -- 2.1.0

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[U-Boot] [PATCH 1/3] ARM: imx fix register base address for i.MX6SX
by Peng Fan 17 Feb '15

17 Feb '15

Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- arch/arm/include/asm/arch-mx6/imx-regs.h | 50 ++++++++++++++++---------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5314298..44e31c9 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -277,31 +277,31 @@ #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #ifdef CONFIG_MX6SX -#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) -#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) -#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) -#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) -#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) -#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) -#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) -#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) -#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) -#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) -#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) -#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) -#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) -#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) -#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) -#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) -#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) -#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) -#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) -#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#define GIS_BASE_ADDR (AIPS3_BASE_ADDR + 0x04000) +#define DCIC1_BASE_ADDR (AIPS3_BASE_ADDR + 0x0C000) +#define DCIC2_BASE_ADDR (AIPS3_BASE_ADDR + 0x10000) +#define CSI1_BASE_ADDR (AIPS3_BASE_ADDR + 0x14000) +#define PXP_BASE_ADDR (AIPS3_BASE_ADDR + 0x18000) +#define CSI2_BASE_ADDR (AIPS3_BASE_ADDR + 0x1C000) +#define LCDIF1_BASE_ADDR (AIPS3_BASE_ADDR + 0x20000) +#define LCDIF2_BASE_ADDR (AIPS3_BASE_ADDR + 0x24000) +#define VADC_BASE_ADDR (AIPS3_BASE_ADDR + 0x28000) +#define VDEC_BASE_ADDR (AIPS3_BASE_ADDR + 0x2C000) +#define SPBA_BASE_ADDR (AIPS3_BASE_ADDR + 0x3C000) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_BASE_ADDR + 0x7C000) +#define ADC1_BASE_ADDR (AIPS3_BASE_ADDR + 0x80000) +#define ADC2_BASE_ADDR (AIPS3_BASE_ADDR + 0x84000) +#define WDOG3_BASE_ADDR (AIPS3_BASE_ADDR + 0x88000) +#define ECSPI5_BASE_ADDR (AIPS3_BASE_ADDR + 0x8C000) +#define HS_BASE_ADDR (AIPS3_BASE_ADDR + 0x90000) +#define MU_MCU_BASE_ADDR (AIPS3_BASE_ADDR + 0x94000) +#define CANFD_BASE_ADDR (AIPS3_BASE_ADDR + 0x98000) +#define MU_DSP_BASE_ADDR (AIPS3_BASE_ADDR + 0x9C000) +#define UART6_BASE_ADDR (AIPS3_BASE_ADDR + 0xA0000) +#define PWM5_BASE_ADDR (AIPS3_BASE_ADDR + 0xA4000) +#define PWM6_BASE_ADDR (AIPS3_BASE_ADDR + 0xA8000) +#define PWM7_BASE_ADDR (AIPS3_BASE_ADDR + 0xAC000) +#define PWM8_BASE_ADDR (AIPS3_BASE_ADDR + 0xB0000) #endif #define CHIP_REV_1_0 0x10 -- 1.8.4

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[U-Boot] [PATCH v2 0/11] Add full DDR init for Marvell Armada-XP MV78xx0 (AXP)
by Stefan Roese 17 Feb '15

17 Feb '15

This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the AXP boot image. Not linked with the main U-Boot. With this code addition and the also included SERDES / PHY setup code, the Armada-XP support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Hopefully other MVEBU SoC's will follow here. Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and on a custom fixed DDR configuration board (maxbcm with MV78460). Thanks, Stefan Changes in v2: - Patch added to patch series (removal of dummy binary.0 files) - Rebased on current master (2015.01, git ID ab77f241) Stefan Roese (11): arm: mvebu: maxbcm: Fix compilation warning and add Spansion SPI NOR support arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr arm: mvebu: Add Serdes PHY config code arm: armada-xp: Add SPL support used to include the DDR training code scripts/Makefile.spl: Add MVEBU DDR code to SPL tools: kwbimage: Support u-boot.img padding to CONFIG_SYS_SPI_U_BOOT_OFFS Makefile: Add another kwb build target used on Marvell Armada-XP (AXP) arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot arm: maxbcm: Enable SPL to include DDR training code into U-Boot arm: mvebu: Placeholder bin_hdr file can now be removed arm: armada-xp: Change built target to include the SPL binary as bin_hdr Makefile | 6 + arch/arm/Kconfig | 2 + arch/arm/cpu/armv7/armada-xp/Makefile | 2 + arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S | 62 + arch/arm/cpu/armv7/armada-xp/spl.c | 38 + arch/arm/include/asm/arch-armada-xp/config.h | 4 + arch/arm/include/asm/arch-armada-xp/cpu.h | 16 + arch/arm/mvebu-common/Makefile | 2 + arch/arm/mvebu-common/serdes/Makefile | 6 + arch/arm/mvebu-common/serdes/board_env_spec.h | 262 ++++ arch/arm/mvebu-common/serdes/high_speed_env_lib.c | 1572 +++++++++++++++++++ arch/arm/mvebu-common/serdes/high_speed_env_spec.c | 185 +++ arch/arm/mvebu-common/serdes/high_speed_env_spec.h | 87 ++ arch/arm/mvebu-common/u-boot-spl.lds | 57 + board/Marvell/db-mv784mp-gp/binary.0 | 17 - board/Marvell/db-mv784mp-gp/kwbimage.cfg | 2 +- board/maxbcm/binary.0 | 17 - board/maxbcm/kwbimage.cfg | 2 +- board/maxbcm/maxbcm.c | 85 +- configs/db-mv784mp-gp_defconfig | 5 +- configs/maxbcm_defconfig | 5 +- drivers/ddr/mvebu/Makefile | 14 + drivers/ddr/mvebu/ddr3_axp.h | 510 +++++++ drivers/ddr/mvebu/ddr3_axp_config.h | 146 ++ drivers/ddr/mvebu/ddr3_axp_mc_static.h | 284 ++++ drivers/ddr/mvebu/ddr3_axp_training_static.h | 770 ++++++++++ drivers/ddr/mvebu/ddr3_axp_vars.h | 226 +++ drivers/ddr/mvebu/ddr3_dfs.c | 1552 +++++++++++++++++++ drivers/ddr/mvebu/ddr3_dqs.c | 1374 +++++++++++++++++ drivers/ddr/mvebu/ddr3_hw_training.c | 1115 ++++++++++++++ drivers/ddr/mvebu/ddr3_hw_training.h | 392 +++++ drivers/ddr/mvebu/ddr3_init.c | 1219 +++++++++++++++ drivers/ddr/mvebu/ddr3_init.h | 143 ++ drivers/ddr/mvebu/ddr3_patterns_64bit.h | 924 ++++++++++++ drivers/ddr/mvebu/ddr3_pbs.c | 1592 ++++++++++++++++++++ drivers/ddr/mvebu/ddr3_read_leveling.c | 1214 +++++++++++++++ drivers/ddr/mvebu/ddr3_sdram.c | 669 ++++++++ drivers/ddr/mvebu/ddr3_spd.c | 1300 ++++++++++++++++ drivers/ddr/mvebu/ddr3_write_leveling.c | 1366 +++++++++++++++++ drivers/ddr/mvebu/xor.c | 436 ++++++ drivers/ddr/mvebu/xor.h | 70 + drivers/ddr/mvebu/xor_regs.h | 103 ++ include/configs/db-mv784mp-gp.h | 49 + include/configs/maxbcm.h | 49 + scripts/Makefile.spl | 1 + tools/kwbimage.c | 11 + 46 files changed, 17919 insertions(+), 44 deletions(-) create mode 100644 arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S create mode 100644 arch/arm/cpu/armv7/armada-xp/spl.c create mode 100644 arch/arm/mvebu-common/serdes/Makefile create mode 100644 arch/arm/mvebu-common/serdes/board_env_spec.h create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_lib.c create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.c create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.h create mode 100644 arch/arm/mvebu-common/u-boot-spl.lds delete mode 100644 board/Marvell/db-mv784mp-gp/binary.0 delete mode 100644 board/maxbcm/binary.0 create mode 100644 drivers/ddr/mvebu/Makefile create mode 100644 drivers/ddr/mvebu/ddr3_axp.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_config.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_mc_static.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_training_static.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_vars.h create mode 100644 drivers/ddr/mvebu/ddr3_dfs.c create mode 100644 drivers/ddr/mvebu/ddr3_dqs.c create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.c create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.h create mode 100644 drivers/ddr/mvebu/ddr3_init.c create mode 100644 drivers/ddr/mvebu/ddr3_init.h create mode 100644 drivers/ddr/mvebu/ddr3_patterns_64bit.h create mode 100644 drivers/ddr/mvebu/ddr3_pbs.c create mode 100644 drivers/ddr/mvebu/ddr3_read_leveling.c create mode 100644 drivers/ddr/mvebu/ddr3_sdram.c create mode 100644 drivers/ddr/mvebu/ddr3_spd.c create mode 100644 drivers/ddr/mvebu/ddr3_write_leveling.c create mode 100644 drivers/ddr/mvebu/xor.c create mode 100644 drivers/ddr/mvebu/xor.h create mode 100644 drivers/ddr/mvebu/xor_regs.h -- 2.2.2

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[U-Boot] [PATCH] spi: davinci: Remove duplicate code to set bus and cs for slave
by Axel Lin 17 Feb '15

17 Feb '15

It's done in spi_alloc_slave(). Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/spi/davinci_spi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0ec5b9d..bf18362 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -32,9 +32,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!ds) return NULL; - ds->slave.bus = bus; - ds->slave.cs = cs; - switch (bus) { case SPI0_BUS: ds->regs = (struct davinci_spi_regs *)SPI0_BASE; -- 1.9.1

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[U-Boot] [PATCH] spi: cf_qspi: Fixup to_cf_qspi_slave macro
by Axel Lin 17 Feb '15

17 Feb '15

The third parameter of container_of is the name of the member within the struct. Current code only works if the parameter passed to to_cf_qspi_slave named slave. Fix it. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/spi/cf_qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c index 6b85633..834c5bd 100644 --- a/drivers/spi/cf_qspi.c +++ b/drivers/spi/cf_qspi.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define clamp(x, low, high) (min(max(low, x), high)) -#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, s) +#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave) struct cf_qspi_slave { struct spi_slave slave; /* Specific bus:cs ID for each device */ -- 1.9.1

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[U-Boot] spi: ftssp010_spi: Use to_ftssp010_spi() to ensure free correct address
by Axel Lin 17 Feb '15

17 Feb '15

Don't assume slave is always the first member of struct ftssp010_spi. Use to_ftssp010_spi() to ensure free correct address in spi_free_slave(). Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/spi/ftssp010_spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c index 267e4d8..c7d6480 100644 --- a/drivers/spi/ftssp010_spi.c +++ b/drivers/spi/ftssp010_spi.c @@ -431,7 +431,9 @@ free_out: void spi_free_slave(struct spi_slave *slave) { - free(slave); + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + + free(chip); } int spi_claim_bus(struct spi_slave *slave) -- 1.9.1

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[U-Boot] [PATCH] am43xx_evm: Add netboot and related to environment
by Franklin S Cooper Jr 17 Feb '15

17 Feb '15

From: Tom Rini <trini(a)ti.com> Signed-off-by: Tom Rini <trini(a)ti.com> --- include/configs/am43xx_evm.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 7ccbf36..44b6f93 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -168,6 +168,10 @@ "usbroot=/dev/sda2 rw\0" \ "usbrootfstype=ext4 rootwait\0" \ "usbdev=0\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ "ramroot=/dev/ram0 rw\0" \ "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ @@ -178,6 +182,11 @@ "${optargs} " \ "root=${usbroot} " \ "rootfstype=${usbrootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=load ${devtype} ${devnum} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ @@ -229,6 +238,13 @@ "bootz ${loadaddr} - ${fdtaddr}; " \ "fi;" \ "fi\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "findfdt="\ "if test $board_name = AM43EPOS; then " \ "setenv fdtfile am43x-epos-evm.dtb; fi; " \ -- 2.2.2

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