February 2015 - U-Boot

[U-Boot] [PATCH v2] image: Convert to use fdt_for_each_subnode macro
by Axel Lin 17 Feb '15

17 Feb '15

Use fdt_for_each_subnode macro to simplify the code a bit. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- v2: Update commit log common/image-fit.c | 4 +--- common/image-sig.c | 16 ++++------------ 2 files changed, 5 insertions(+), 15 deletions(-) diff --git a/common/image-fit.c b/common/image-fit.c index b47d110..778d2a1 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1010,9 +1010,7 @@ int fit_image_verify(const void *fit, int image_noffset) } /* Process all hash subnodes of the component image node */ - for (noffset = fdt_first_subnode(fit, image_noffset); - noffset >= 0; - noffset = fdt_next_subnode(fit, noffset)) { + fdt_for_each_subnode(fit, noffset, image_noffset) { const char *name = fit_get_name(fit, noffset, NULL); /* diff --git a/common/image-sig.c b/common/image-sig.c index 2c9f0cd..eda5e13 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -212,9 +212,7 @@ static int fit_image_verify_sig(const void *fit, int image_noffset, int ret; /* Process all hash subnodes of the component image node */ - for (noffset = fdt_first_subnode(fit, image_noffset); - noffset >= 0; - noffset = fdt_next_subnode(fit, noffset)) { + fdt_for_each_subnode(fit, noffset, image_noffset) { const char *name = fit_get_name(fit, noffset, NULL); if (!strncmp(name, FIT_SIG_NODENAME, @@ -262,9 +260,7 @@ int fit_image_verify_required_sigs(const void *fit, int image_noffset, return 0; } - for (noffset = fdt_first_subnode(sig_blob, sig_node); - noffset >= 0; - noffset = fdt_next_subnode(sig_blob, noffset)) { + fdt_for_each_subnode(sig_blob, noffset, sig_node) { const char *required; int ret; @@ -397,9 +393,7 @@ static int fit_config_verify_sig(const void *fit, int conf_noffset, int ret; /* Process all hash subnodes of the component conf node */ - for (noffset = fdt_first_subnode(fit, conf_noffset); - noffset >= 0; - noffset = fdt_next_subnode(fit, noffset)) { + fdt_for_each_subnode(fit, noffset, conf_noffset) { const char *name = fit_get_name(fit, noffset, NULL); if (!strncmp(name, FIT_SIG_NODENAME, @@ -444,9 +438,7 @@ int fit_config_verify_required_sigs(const void *fit, int conf_noffset, return 0; } - for (noffset = fdt_first_subnode(sig_blob, sig_node); - noffset >= 0; - noffset = fdt_next_subnode(sig_blob, noffset)) { + fdt_for_each_subnode(sig_blob, noffset, sig_node) { const char *required; int ret; -- 1.9.1

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[U-Boot] [PATCH v2] spl, spl_nor: fix compiler warning
by Heiko Schocher 17 Feb '15

17 Feb '15

executing "tools/buildman/buildman mpc5xx" drops this warning: common/spl/spl_nor.c: In function 'spl_nor_load_image': common/spl/spl_nor.c:26:10: warning: assignment discards 'const' qualifier from pointer target type [enabled by default] fix this. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- Changes in v2: - add comment from Masahiro Yamada: - add const to "struct image_header *header;" - change subject prefix from "powerpc, mpc5xx" to "spl, spl_nor" common/spl/spl_nor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 2c0e8e0..c2fee01 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -17,7 +17,7 @@ void spl_nor_load_image(void) #ifdef CONFIG_SPL_OS_BOOT if (!spl_start_uboot()) { - struct image_header *header; + const struct image_header *header; /* * Load Linux from its location in NOR flash to its defined -- 2.1.0

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[U-Boot] [PATCH] .travis.yml: remove 824x builds
by Heiko Schocher 17 Feb '15

17 Feb '15

remove powerpc 824x build, as this architecture not longer exists. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- .travis.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index 90f0fd7..923c9dd 100644 --- a/.travis.yml +++ b/.travis.yml @@ -107,9 +107,6 @@ matrix: - TEST_CMD="tools/buildman/buildman mpc512x" INSTALL_TOOLCHAIN="ppc" - env: - - TEST_CMD="tools/buildman/buildman mpc824x" - INSTALL_TOOLCHAIN="ppc" - - env: - TEST_CMD="tools/buildman/buildman mpc8260" INSTALL_TOOLCHAIN="ppc" - env: -- 2.1.0

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[U-Boot] [PATCH v2] PCI: add 64-bit prefetchable memory support
by fenghua＠phytium.com.cn 17 Feb '15

17 Feb '15

From: David Feng <fenghua(a)phytium.com.cn> PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors. Changes for v2: - According to Bin Meng's advice, the macro PCI_PREF_RANGE_TYPE_MASK and PCI_PREF_RANGE_TYPE_64 are used. Signed-off-by: David Feng <fenghua(a)phytium.com.cn> --- drivers/pci/pci_auto.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index ed92857..378efbf 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -223,9 +223,12 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, struct pci_region *pci_mem = hose->pci_mem; struct pci_region *pci_prefetch = hose->pci_prefetch; struct pci_region *pci_io = hose->pci_io; - u16 cmdstat; + u16 cmdstat, prefechable_64; pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat); + pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE, + &prefechable_64); + prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; /* Configure bus number registers */ pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, @@ -252,12 +255,26 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, /* Set up memory and I/O filter limits, assume 32-bit I/O space */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, (pci_prefetch->bus_lower & 0xfff00000) >> 16); + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) +#ifdef CONFIG_SYS_PCI_64BIT + pci_hose_write_config_dword(hose, dev, + PCI_PREF_BASE_UPPER32, + pci_prefetch->bus_lower >> 32); +#else + pci_hose_write_config_dword(hose, dev, + PCI_PREF_BASE_UPPER32, + 0x0); +#endif cmdstat |= PCI_COMMAND_MEMORY; } else { /* We don't support prefetchable memory for now, so disable */ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0); + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { + pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0); + pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0); + } } if (pci_io) { @@ -297,11 +314,28 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose, } if (pci_prefetch) { + u16 prefechable_64; + + pci_hose_read_config_word(hose, dev, + PCI_PREF_MEMORY_LIMIT, + &prefechable_64); + prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; + /* Round memory allocator to 1MB boundary */ pciauto_region_align(pci_prefetch, 0x100000); pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, (pci_prefetch->bus_lower - 1) >> 16); + if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) +#ifdef CONFIG_SYS_PCI_64BIT + pci_hose_write_config_dword(hose, dev, + PCI_PREF_LIMIT_UPPER32, + (pci_prefetch->bus_lower - 1) >> 32); +#else + pci_hose_write_config_dword(hose, dev, + PCI_PREF_LIMIT_UPPER32, + 0x0); +#endif } if (pci_io) { -- 1.7.9.5

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[U-Boot] [PATCH 1/4] mmc: fsl_esdhc: Add CMD11 support to switch to 1.8V
by Otavio Salvador 17 Feb '15

17 Feb '15

This adds support to switch to 1.8V in case CMD11 succeeds. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- drivers/mmc/fsl_esdhc.c | 30 +++++++++++++++++++++++------- include/fsl_esdhc.h | 2 ++ include/mmc.h | 1 + 3 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c55eb28..eb0fbf9 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -54,19 +54,21 @@ struct fsl_esdhc { uint fevt; /* Force event register */ uint admaes; /* ADMA error status register */ uint adsaddr; /* ADMA system address register */ - char reserved2[160]; /* reserved */ + char reserved2[100]; /* reserved */ + uint vendorspec; /* Vendor Specific register */ + char reserved3[59]; /* reserved */ uint hostver; /* Host controller version register */ - char reserved3[4]; /* reserved */ - uint dmaerraddr; /* DMA error address register */ char reserved4[4]; /* reserved */ - uint dmaerrattr; /* DMA error attribute register */ + uint dmaerraddr; /* DMA error address register */ char reserved5[4]; /* reserved */ + uint dmaerrattr; /* DMA error attribute register */ + char reserved6[4]; /* reserved */ uint hostcapblt2; /* Host controller capabilities register 2 */ - char reserved6[8]; /* reserved */ + char reserved7[8]; /* reserved */ uint tcr; /* Tuning control register */ - char reserved7[28]; /* reserved */ + char reserved8[28]; /* reserved */ uint sddirctl; /* SD direction control register */ - char reserved8[712]; /* reserved */ + char reserved9[712]; /* reserved */ uint scr; /* eSDHC control register */ }; @@ -341,6 +343,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) goto out; } + /* Switch voltage to 1.8V if CMD11 succeeded */ + if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { + esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); + + printf("Run CMD11 1.8V switch\n"); + /* Sleep for 5 ms - max time for card to switch to 1.8V */ + udelay(5000); + } + /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { int timeout = 2500; @@ -413,6 +424,11 @@ out: while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD)) ; } + + /* If this was CMD11, then notify that power cycle is needed */ + if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) + printf("CMD11 to switch to 1.8V mode failed." + "Card requires power cycle\n"); } esdhc_write32(&regs->irqstat, -1); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index c1b6648..e3d6581 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -154,6 +154,8 @@ #define ESDHC_HOSTCAPBLT_DMAS 0x00400000 #define ESDHC_HOSTCAPBLT_HSS 0x00200000 +#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */ + struct fsl_esdhc_cfg { u32 esdhc_base; u32 sdhc_clk; diff --git a/include/mmc.h b/include/mmc.h index 56d97bb..e4b071e 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -88,6 +88,7 @@ #define SD_CMD_SEND_RELATIVE_ADDR 3 #define SD_CMD_SWITCH_FUNC 6 #define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_SWITCH_UHS18V 11 #define SD_CMD_APP_SET_BUS_WIDTH 6 #define SD_CMD_ERASE_WR_BLK_START 32 -- 2.1.4

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[U-Boot] Question about Arndale Octa board (Exynos 5420) and HYP mode
by Fabio Canigliula 17 Feb '15

17 Feb '15

Hello, I have a Samsung Exynos 5420 Arndale Octa Board and I am trying to run Xen 4.5 on it. I have successfully managed to configure and patch XEN and the kernel for the board. The problem is that XEN doesn't match the correct CPU mode for its boot. -------------XEN early debug----------------- Starting kernel ... - UART enabled - - CPU 00000000 booting - - Xen must be entered in NS Hyp mode - - Boot failed - ------------------------------------------------------- As far as I know, the only currently working U-Boot for the octa board is a signed 2012.07 version which starts the booting CPU in a NS SVC mode. I patched it, adding all the modules needed to bring the CPU to HYP mode, as in: http://lists.denx.de/pipermail/u-boot/2013-September/163019.html However, CPU does not seem to switch properly to HYP mode, as it hangs on an assembly instruction (hvc #0) when calling the function _switch_to_hyp(), just like in: http://markmail.org/thread/dhiknm25xfbsrlo6 I am than asking you if there is something I can do to overcome this problem or if there is someone working on it who can help me out. Any help or suggestion would be greatly appreciated. Regards, F.C.

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[U-Boot] [PATCH] add example for file on VFAT filesystem usage
by Waldemar Brodkorb 17 Feb '15

17 Feb '15

For example on a raspberry pi the u-boot environment can be saved in a file on the first VFAT partition. This example illustrates how to use it with fw_printenv/fw_setenv. Signed-off-by: Waldemar Brodkorb <wbx(a)openadk.org> --- tools/env/fw_env.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config index c9b9f6a..6f216f9 100644 --- a/tools/env/fw_env.config +++ b/tools/env/fw_env.config @@ -20,3 +20,6 @@ # Block device example #/dev/mmcblk0 0xc0000 0x20000 + +# VFAT example +#/boot/uboot.env 0x0000 0x4000 -- 1.9.1

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[U-Boot] [PULL] u-boot-avr32/master -> u-boot/master
by Andreas Bießmann 17 Feb '15

17 Feb '15

Hi Tom, finally generic board support for avr32! The following changes since commit bd2a4888b123713adec271d6c8040ca9f609aa2f: sunxi: configs/sunxi-common.h: Enable CONFIG_CMD_PART (2015-02-11 19:43:45 -0500) are available in the git repository at: git://git.denx.de/u-boot-avr32.git master for you to fetch changes up to 4d3dada78ec402dc51e4198dda316301e0d99f35: atstk1002: enable generic board (2015-02-16 21:21:26 +0100) ---------------------------------------------------------------- Andreas Bießmann (11): avr32: use dlmalloc for DMA buffers avr32: rename cpu_init() -> arch_cpu_init() avr32: factor out cpu_mmc_init() avr32: rename mmu.h definitions avr32: convert to dram_init() avr32: use generic gd->start_addr_sp common/board_f: factor out reserve_stacks common/board_r: allocate bootparams avr32: add generic board support grasshopper: enable generic board atstk1002: enable generic board arch/arm/lib/Makefile | 1 + arch/arm/lib/stack.c | 42 +++++++++++++ arch/avr32/config.mk | 3 + arch/avr32/cpu/Makefile | 1 + arch/avr32/cpu/at32ap700x/mmu.c | 8 +-- arch/avr32/cpu/cpu.c | 2 +- arch/avr32/cpu/exception.c | 6 +- arch/avr32/cpu/mmc.c | 16 +++++ arch/avr32/cpu/u-boot.lds | 2 + arch/avr32/include/asm/arch-at32ap700x/mmu.h | 6 +- arch/avr32/include/asm/config.h | 1 + arch/avr32/include/asm/dma-mapping.h | 7 ++- arch/avr32/include/asm/global_data.h | 1 - arch/avr32/include/asm/u-boot.h | 10 ++++ arch/avr32/lib/Makefile | 3 + arch/avr32/lib/board.c | 83 ++++---------------------- arch/avr32/lib/dram_init.c | 17 ++++++ arch/avr32/lib/interrupts.c | 5 ++ arch/powerpc/lib/Makefile | 1 + arch/powerpc/lib/stack.c | 31 ++++++++++ board/atmel/atngw100/atngw100.c | 32 +++------- board/atmel/atngw100mkii/atngw100mkii.c | 39 ++++-------- board/atmel/atstk1000/atstk1000.c | 33 +++------- board/earthlcd/favr-32-ezkit/favr-32-ezkit.c | 33 +++------- board/in-circuit/grasshopper/grasshopper.c | 32 +++------- board/mimc/mimc200/mimc200.c | 38 ++++-------- board/miromico/hammerhead/hammerhead.c | 32 +++------- common/board_f.c | 46 ++++---------- common/board_r.c | 28 ++++++++- common/cmd_bdinfo.c | 4 +- include/asm-generic/u-boot.h | 4 ++ include/common.h | 18 ++++++ include/configs/atngw100.h | 1 - include/configs/atngw100mkii.h | 1 - include/configs/atstk1002.h | 5 +- include/configs/atstk1006.h | 1 - include/configs/favr-32-ezkit.h | 1 - include/configs/grasshopper.h | 5 +- include/configs/hammerhead.h | 1 - include/configs/mimc200.h | 1 - 40 files changed, 294 insertions(+), 307 deletions(-) create mode 100644 arch/arm/lib/stack.c create mode 100644 arch/avr32/cpu/mmc.c create mode 100644 arch/avr32/lib/dram_init.c create mode 100644 arch/powerpc/lib/stack.c

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[U-Boot] [PATCH] mtd: nand: omap_gpmc: Make ready/busy pins configurable
by Michal Sojka 17 Feb '15

17 Feb '15

Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of WAIT0 pin for determining whether the NAND is ready or not. This only works if all NAND chips are connected to WAIT0. If some chips are connected to the other available pin WAIT1, nand_wait() does not really wait and prints a WARN_ON message. This patch allows the board to provide configuration of which chip is connected to which WAITx signal. For example, one can define in include/configs/foo.h: #define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1 This would mean that chips using to CS0 and 1 are connected to WAIT0 and chips with CS2 and 3 are connected to WAIT1. Signed-off-by: Michal Sojka <sojka(a)merica.cz> Cc: Tom Rini <trini(a)ti.com> Cc: Stefan Roese <sr(a)denx.de> --- drivers/mtd/nand/omap_gpmc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 459904d..57fc7b9 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -36,7 +36,8 @@ static __maybe_unused struct nand_ecclayout omap_ecclayout; struct omap_nand_info { struct bch_control *control; enum omap_ecc ecc_scheme; - int cs; + uint8_t cs; + uint8_t ws; /* wait status pin (0,1) */ }; /* We are wasting a bit of memory but al least we are safe */ @@ -76,7 +77,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, /* Check wait pin as dev ready indicator */ static int omap_dev_ready(struct mtd_info *mtd) { - return gpmc_cfg->status & (1 << 8); + register struct nand_chip *this = mtd->priv; + struct omap_nand_info *info = this->priv; + return gpmc_cfg->status & (1 << (8 + info->ws)); } /* @@ -853,6 +856,12 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; omap_nand_info[cs].control = NULL; omap_nand_info[cs].cs = cs; +#if !defined(CONFIG_NAND_OMAP_GPMC_WSCFG) + omap_nand_info[cs].ws = 0; +#else + int8_t ws[CONFIG_SYS_MAX_NAND_DEVICE] = { CONFIG_NAND_OMAP_GPMC_WSCFG }; + omap_nand_info[cs].ws = ws[cs]; +#endif nand->priv = &omap_nand_info[cs]; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; -- 2.1.4

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[U-Boot] [PATCH v2 00/11] Add support for booting multiple cores
by Akshay Saraswat 17 Feb '15

17 Feb '15

This patch series introduces changes for booting secondary CPUs on Exynos5420 and Exynos5800. Changes since v1: - Added Reviewed-by & Tested-by in the acked patches. - Removed unnecessary CONFIGS and macros. - Changed names of few macros for better understanding in patch 2. - Added MPIDR bit assignment info comment in power_down_core in patch 2. - Changed to SPDX header in sec_boot.S in patch 5. - Fixed compilation error for snow build in patch 11. Akshay Saraswat (10): Exynos542x: Config: Add various configs Exynos542x: CPU: Power down all secondary cores Exynos542x: Add workaround for ARM errata 798870 Exynos542x: Add workaround for ARM errata 799270 Exynos542x: Add workaround for exynos iROM errata Exynos542x: Change ambiguous function name set_l2cache Exynos542x: cache: Disable clean/evict push to external Exynos542x: add L2 control register configuration Exynos542x: Fix secondary core booting for thumb Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset Doug Anderson (1): Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800 arch/arm/cpu/armv7/exynos/Makefile | 2 + arch/arm/cpu/armv7/exynos/common_setup.h | 55 ++++++++++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 3 + arch/arm/cpu/armv7/exynos/lowlevel_init.c | 166 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/exynos/sec_boot.S | 128 +++++++++++++++++++++++ arch/arm/cpu/armv7/exynos/soc.c | 35 ------- arch/arm/include/asm/arch-exynos/cpu.h | 5 + arch/arm/include/asm/arch-exynos/system.h | 88 ++++++++++++++++ include/configs/exynos5420-common.h | 16 +++ 9 files changed, 463 insertions(+), 35 deletions(-) create mode 100644 arch/arm/cpu/armv7/exynos/sec_boot.S -- 1.9.1

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