February 2015 - U-Boot

Re: [U-Boot] [PATCH v3 03/11] Exynos542x: Add workaround for ARM errata 798870
by Akshay Saraswat 18 Feb '15

18 Feb '15

Hello, >On Wed, 18 Feb 2015 15:16:27 +0530 >Akshay Saraswat <akshay.s(a)samsung.com> wrote: > >> This patch adds workaround for ARM errata 798870 which says >> "If back-to-back speculative cache line fills (fill A and fill B) are >> issued from the L1 data cache of a CPU to the L2 cache, the second >> request (fill B) is then cancelled, and the second request would have >> detected a hazard against a recent write or eviction (write B) to the >> same cache line as fill B then the L2 logic might deadlock." >> >> Signed-off-by: Kimoon Kim <kimoon.kim(a)samsung.com> >> Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> >> Reviewed-by: Simon Glass <sjg(a)chromium.org> >> Tested-by: Simon Glass <sjg(a)chromium.org> >> --- >> Changes since v2: >> - No change. >> >> Changes since v1: >> - Added Reviewed-by & Tested-by. >> - Added space before */ on line # 40. >> >> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c >> index e36f2fa..7335a1e 100644 >> --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c >> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c >> @@ -46,6 +46,28 @@ enum { >> >> #ifdef CONFIG_EXYNOS5420 >> /* >> + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been >> + * stalled for 1024 cycles to verify that its hazard condition still exists. >> + */ > >Having the ARM errata number mentioned in the comment here would make >the purpose of this code much more clear to anyone looking at it later >in the future. > >Also isn't this a general purpose Cortex-A15 r2pX workaround, >also potentially useful for the other non-Exynos SoCs too? Yes, you are right. I'll mention errata number and will move it to armv7/cpu.c. > >> +void set_l2cache(void) >> +{ >> + uint32_t val; >> + >> + /* Read MIDR for Primary Part Number */ >> + mrc_midr(val); >> + val = (val >> 4); >> + val &= 0xf; >> + >> + /* L2ACTLR[7]: Enable hazard detect timeout for A15 */ >> + if (val == 0xf) { >> + mrc_l2_aux_ctlr(val); >> + val |= (1 << 7); >> + mcr_l2_aux_ctlr(val); >> + mrc_l2_ctlr(val); >> + } >> +} >> + >> +/* >> * Pointer to this function is stored in iRam which is used >> * for jump and power down of a specific core. >> */ > > > >-- >Best regards, >Siarhei Siamashka Regards, Akshay Saraswat

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Re: [U-Boot] [PATCH v3 02/11] Exynos542x: CPU: Power down all secondary cores
by Akshay Saraswat 18 Feb '15

18 Feb '15

Hi Lukasz, >Hi Akshay, > >> This patch adds code to shutdown secondary cores. >> When U-boot comes up, all secondary cores appear powered on, >> which is undesirable and causes side effects while >> initializing these cores in kernel. >> >> Secondary core power down happens in following steps: >> >> Step-1: After Exynos power-on, primary core starts executing first. >> Step-2: In iROM code every core has to check 2 flags i.e. >> addresses 0x02020028 & 0x02020004. > >Could you provide exact names of those registers? I'm familiar with >Samsung SoCs but I cannot recall which one those are. > As I have written in Step-2, these are addresses (SRAM) and not registers. Our iROM code has a part where it reads 0x02020028 for a specific vlaue FCBA0D10. If CPU finds that value then it extracts jump address from 0x02020004, else it follows normal boot path. >It would provide more readability to this commit message. Please fix it >globally. > >> Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a >> jump address for primary core and 0 for all secondary cores. >> Step-4: Therefore, primary core follows normal iROM execution and >> jumps to BL1 eventually, whereas all secondary cores enter WFE. >> Step-5: When primary core comes into function >> secondary_cores_configure, it puts pointer to function >> power_down_core into 0x02020004 and provides DSB and SEV for all >> cores so that they may come out of WFE and jump to power_down_core >> function. Step-6: And ultimately because of power_down_core all >> secondary cores shut-down. >> >> Signed-off-by: Kimoon Kim <kimoon.kim(a)samsung.com> >> Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> >> --- >> Changes since v2: >> - No change. >> >> Changes since v1: >> - Removed unnecessary macros. >> - Changed names of few macros for better understanding. >> - Added MPIDR bit assignment info comment in power_down_core. >> >> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 3 ++ >> arch/arm/cpu/armv7/exynos/lowlevel_init.c | 69 >> ++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | >> 5 ++ arch/arm/include/asm/arch-exynos/system.h | 87 >> +++++++++++++++++++++++++++++++ 4 files changed, 164 insertions(+) >> >> diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h >> b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 2eea48a..9073f50 >> 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h >> +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h >> @@ -700,6 +700,9 @@ >> #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE >> >> #else >> + >> +#define CPU_CONFIG_STATUS_OFFSET 0x80 >> +#define CPU_RST_FLAG_VAL 0xFCBA0D10 >> #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 >> >> /* APLL_CON1 */ >> diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c >> b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index 83e1dcf..e36f2fa >> 100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c >> +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c >> @@ -31,7 +31,9 @@ >> #include <asm/arch/tzpc.h> >> #include <asm/arch/periph.h> >> #include <asm/arch/pinmux.h> >> +#include <asm/arch/system.h> >> #include "common_setup.h" >> +#include "exynos5_setup.h" >> >> /* These are the things we can do during low-level init */ >> enum { >> @@ -42,6 +44,68 @@ enum { >> DO_POWER = 1 << 4, >> }; >> >> +#ifdef CONFIG_EXYNOS5420 >> +/* >> + * Pointer to this function is stored in iRam which is used >> + * for jump and power down of a specific core. >> + */ >> +static void power_down_core(void) >> +{ >> + uint32_t tmp, core_id, core_config; >> + >> + /* Get the unique core id */ >> + /* >> + * Multiprocessor Affinity Register >> + * [11:8] Cluster ID >> + * [1:0] CPU ID >> + */ >> + mrc_mpafr(core_id); >> + tmp = core_id & 0x3; >> + core_id = (core_id >> 6) & ~3; >> + core_id |= tmp; >> + core_id &= 0x3f; >> + >> + /* Set the status of the core to low */ >> + core_config = (core_id * CPU_CONFIG_STATUS_OFFSET); >> + core_config += EXYNOS5420_CPU_CONFIG_BASE; >> + writel(0x0, core_config); >> + >> + /* Core enter WFI */ >> + wfi(); >> +} >> + >> +/* >> + * Configurations for secondary cores are inapt at this stage. >> + * Reconfigure secondary cores. Shutdown and change the status >> + * of all cores except the primary core. >> + */ >> +static void secondary_cores_configure(void) >> +{ >> + uint32_t core_id; >> + >> + /* Store jump address for power down of secondary cores */ >> + writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + >> 0x4); + >> + /* Need all core power down check */ >> + dsb(); >> + sev(); >> + >> + /* >> + * Power down all cores(secondary) while primary core must >> + * wait for all cores to go down. >> + */ >> + for (core_id = 1; core_id != CONFIG_CORE_COUNT; core_id++) { >> + while ((readl(EXYNOS5420_CPU_STATUS_BASE >> + + (core_id * CPU_CONFIG_STATUS_OFFSET)) >> + & 0xff) != 0x0) { >> + isb(); >> + sev(); >> + } >> + isb(); >> + } >> +} >> +#endif >> + >> int do_lowlevel_init(void) >> { >> uint32_t reset_status; >> @@ -49,6 +113,11 @@ int do_lowlevel_init(void) >> >> arch_cpu_init(); >> >> +#ifdef CONFIG_EXYNOS5420 >> + /* Reconfigure secondary cores */ >> + secondary_cores_configure(); >> +#endif >> + >> reset_status = get_reset_status(); >> >> switch (reset_status) { >> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h >> b/arch/arm/include/asm/arch-exynos/cpu.h index 29674ad..e739520 100644 >> --- a/arch/arm/include/asm/arch-exynos/cpu.h >> +++ b/arch/arm/include/asm/arch-exynos/cpu.h >> @@ -153,6 +153,10 @@ >> #define EXYNOS5420_CLOCK_BASE 0x10010000 >> #define EXYNOS5420_POWER_BASE 0x10040000 >> #define EXYNOS5420_SWRESET 0x10040400 >> +#define EXYNOS5420_INFORM_BASE 0x10040800 >> +#define EXYNOS5420_SPARE_BASE 0x10040900 >> +#define EXYNOS5420_CPU_CONFIG_BASE 0x10042000 >> +#define EXYNOS5420_CPU_STATUS_BASE 0x10042004 >> #define EXYNOS5420_SYSREG_BASE 0x10050000 >> #define EXYNOS5420_TZPC_BASE 0x100E0000 >> #define EXYNOS5420_WATCHDOG_BASE 0x101D0000 >> @@ -186,6 +190,7 @@ >> #define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE >> #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE >> >> + >> #ifndef __ASSEMBLY__ >> #include <asm/io.h> >> /* CPU detection macros */ >> diff --git a/arch/arm/include/asm/arch-exynos/system.h >> b/arch/arm/include/asm/arch-exynos/system.h index 4968d3d..86903c3 >> 100644 --- a/arch/arm/include/asm/arch-exynos/system.h >> +++ b/arch/arm/include/asm/arch-exynos/system.h >> @@ -37,6 +37,93 @@ struct exynos5_sysreg { >> >> #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) >> >> +#ifdef CONFIG_EXYNOS5420 >> +/* >> + * Data Synchronization Barrier acts as a special kind of memory >> barrier. >> + * No instruction in program order after this instruction executes >> until >> + * this instruction completes. This instruction completes when: >> + * - All explicit memory accesses before this instruction complete. >> + * - All Cache, Branch predictor and TLB maintenance operations >> before >> + * this instruction complete. >> + */ >> +#define dsb() __asm__ __volatile__ ("dsb\n\t" : : ); >> + >> +/* >> + * This instruction causes an event to be signaled to all cores >> + * within a multiprocessor system. If SEV is implemented, >> + * WFE must also be implemented. >> + */ >> +#define sev() __asm__ __volatile__ ("sev\n\t" : : ); >> +/* >> + * If the Event Register is not set, WFE suspends execution until >> + * one of the following events occurs: >> + * - an IRQ interrupt, unless masked by the CPSR I-bit >> + * - an FIQ interrupt, unless masked by the CPSR F-bit >> + * - an Imprecise Data abort, unless masked by the CPSR A-bit >> + * - a Debug Entry request, if Debug is enabled >> + * - an Event signaled by another processor using the SEV >> instruction. >> + * If the Event Register is set, WFE clears it and returns >> immediately. >> + * If WFE is implemented, SEV must also be implemented. >> + */ >> +#define wfe() __asm__ __volatile__ ("wfe\n\t" : : ); >> + >> +/* Move 0xd3 value to CPSR register to enable SVC mode */ >> +#define svc32_mode_en() __asm__ >> __volatile__ \ >> + ("@ I&F disable, Mode: 0x13 - >> SVC\n\t" \ >> + "msr cpsr_c, #0x13|0xC0\n\t" : : ) >> + >> +/* Set program counter with the given value */ >> +#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : >> "r"(x)) + >> +/* Read Main Id register */ >> +#define mrc_midr(x) __asm__ __volatile__ \ >> + ("mrc p15, 0, %0, c0, c0, 0\n\t" : >> "=r"(x) : ) + >> +/* Read Multiprocessor Affinity Register */ >> +#define mrc_mpafr(x) __asm__ __volatile__ \ >> + ("mrc p15, 0, %0, c0, c0, 5\n\t" : >> "=r"(x) : ) + >> +/* Read System Control Register */ >> +#define mrc_sctlr(x) __asm__ __volatile__ \ >> + ("mrc p15, 0, %0, c1, c0, 0\n\t" : >> "=r"(x) : ) + >> +/* Read Auxiliary Control Register */ >> +#define mrc_auxr(x) __asm__ __volatile__ \ >> + ("mrc p15, 0, %0, c1, c0, 1\n\t" : >> "=r"(x) : ) + >> +/* Read L2 Control register */ >> +#define mrc_l2_ctlr(x) __asm__ __volatile__ \ >> + ("mrc p15, 1, %0, c9, c0, 2\n\t" : >> "=r"(x) : ) + >> +/* Read L2 Auxilliary Control register */ >> +#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \ >> + ("mrc p15, 1, %0, c15, c0, 0\n\t" : >> "=r"(x) : ) + >> +/* Write System Control Register */ >> +#define mcr_sctlr(x) __asm__ __volatile__ \ >> + ("mcr p15, 0, %0, c1, c0, 0\n\t" : : >> "r"(x)) + >> +/* Write Auxiliary Control Register */ >> +#define mcr_auxr(x) __asm__ __volatile__ \ >> + ("mcr p15, 0, %0, c1, c0, 1\n\t" : : >> "r"(x)) + >> +/* Invalidate all instruction caches to PoU */ >> +#define mcr_icache(x) __asm__ __volatile__ \ >> + ("mcr p15, 0, %0, c7, c5, 0\n\t" : : >> "r"(x)) + >> +/* Invalidate unified TLB */ >> +#define mcr_tlb(x) __asm__ __volatile__ \ >> + ("mcr p15, 0, %0, c8, c7, 0\n\t" : : >> "r"(x)) + >> +/* Write L2 Control register */ >> +#define mcr_l2_ctlr(x) __asm__ __volatile__ \ >> + ("mcr p15, 1, %0, c9, c0, 2\n\t" : : >> "r"(x)) + >> +/* Write L2 Auxilliary Control register */ >> +#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \ >> + ("mcr p15, 1, %0, c15, c0, 0\n\t" : : >> "r"(x)) +#endif >> + >> void set_usbhost_mode(unsigned int mode); >> void set_system_display_ctrl(void); >> int exynos_lcd_early_init(const void *blob); > >-- >Best regards, > >Lukasz Majewski > >Samsung R&D Institute Poland (SRPOL) | Linux Platform Group Regards, Akshay Saraswat

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[U-Boot] [PATCH v3 00/11] Add support for booting multiple cores
by Akshay Saraswat 18 Feb '15

18 Feb '15

This patch series introduces changes for booting secondary CPUs on Exynos5420 and Exynos5800. Changes since v2: - Patch 7 & 8 : Replaced #ifdef and #ifndef -> if(proid_is_soc()). - Patch 11 : Removed #ifdef from enum definition. Changes since v1: - Added Reviewed-by & Tested-by in the acked patches. - Removed unnecessary CONFIGS and macros. - Changed names of few macros for better understanding in patch 2. - Added MPIDR bit assignment info comment in power_down_core in patch 2. - Changed to SPDX header in sec_boot.S in patch 5. - Fixed compilation error for snow build in patch 11. Akshay Saraswat (10): Exynos542x: Config: Add various configs Exynos542x: CPU: Power down all secondary cores Exynos542x: Add workaround for ARM errata 798870 Exynos542x: Add workaround for ARM errata 799270 Exynos542x: Add workaround for exynos iROM errata Exynos542x: Change ambiguous function name set_l2cache Exynos542x: cache: Disable clean/evict push to external Exynos542x: add L2 control register configuration Exynos542x: Fix secondary core booting for thumb Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset Doug Anderson (1): Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800 arch/arm/cpu/armv7/exynos/Makefile | 2 + arch/arm/cpu/armv7/exynos/common_setup.h | 63 ++++++++++++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 3 + arch/arm/cpu/armv7/exynos/lowlevel_init.c | 166 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/exynos/sec_boot.S | 128 +++++++++++++++++++++++ arch/arm/cpu/armv7/exynos/soc.c | 35 ------- arch/arm/include/asm/arch-exynos/cpu.h | 5 + arch/arm/include/asm/arch-exynos/system.h | 88 ++++++++++++++++ include/configs/exynos5420-common.h | 16 +++ 9 files changed, 471 insertions(+), 35 deletions(-) create mode 100644 arch/arm/cpu/armv7/exynos/sec_boot.S -- 1.9.1

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[U-Boot] [PATCH RFC v2 0/6] usb: host: Add driver model support
by Vivek Gautam 18 Feb '15

18 Feb '15

Hi Marek, Simon, This patch-series comes as a update for an earlier posted series[1] "[PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host support" which was posted long back. We had discussion to introduce the driver model instead of the approach used in [1]. The driver model seems pretty straight-forward and easier to implement besides giving a clean approach to use multiple host controller types, viz. EHCI, XHCI or OHCI simultaneously on a platform which has such provision. It's rather bad on my side that it took so long to post the updated version. Got busy with the projects. :-( So here's the RFC-v2 which implements the driver model approach. I have added support on OHCI, EHCI and XHCI and enabled EHCI and XHCI on Exynos5250 machines. Though not tested thoroughly, i can see EHCI and XHCI working together (enumerating the Root hubs). Let me know you comments on what you think of current approach. Thanks Vivek [1] [PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host support http://lists.denx.de/pipermail/u-boot/2014-June/182559.html Vivek Gautam (6): usb: Rename usb_submit_int_msg() API to usb_int_msg() dm: usb: Make necessary changes in framework for driver model dm: usb-host: Add UCLASS driver for USB dm: usb-host: Add support for driver model in o/e/xhci. arm: exynos5: Enable EHCI and XHCI hcds through device tree. configs: smdk5250: Enable using XHCI and EHCI together arch/arm/dts/exynos5.dtsi | 8 +++ common/usb.c | 101 ++++++++++++++++++++++++++++++--- common/usb_hub.c | 2 +- common/usb_kbd.c | 4 +- common/usb_storage.c | 2 +- drivers/usb/host/Kconfig | 9 +++ drivers/usb/host/Makefile | 3 + drivers/usb/host/ehci-hcd.c | 36 +++++++++--- drivers/usb/host/ohci-hcd.c | 35 +++++++++--- drivers/usb/host/usb-uclass.c | 107 +++++++++++++++++++++++++++++++++++ drivers/usb/host/xhci.c | 34 ++++++++--- include/configs/exynos5-common.h | 3 + include/configs/exynos5250-common.h | 3 + include/configs/smdk5250.h | 2 + include/dm/uclass-id.h | 1 + include/usb.h | 62 +++++++++++++++----- 16 files changed, 365 insertions(+), 47 deletions(-) create mode 100644 drivers/usb/host/usb-uclass.c -- 1.7.10.4

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[U-Boot] [ANN] U-Boot v2015.01-rc2 released
by Tom Rini 18 Feb '15

18 Feb '15

Hey all, I've pushed v2015.01-rc2 out. Due to a hiccup (that is being worked on right now), things aren't up in the usual place yet but I expect them to be in the next day or so. Until then, it's also available at https://github.com/u-boot/u-boot (but please don't start updating distro recipes to point there instead, that is a mirror of the regular site and I'm not moving us there by default right now). I'm a day late pushing this out but that's my fault for picking up some stuff at the last minute and then having to bisect a few issues, but we're close enough to on schedule that we can keep going with 2 weeks on Mondays. I'm still seeing a few boards fail to link that weren't linking at -rc1 time so I'm going to post the patches to drop them. In terms of big removal patches, now that -rc2 is out I'm going to take what Masahiro has posted and that didn't cause people to speak up and claim / fix the boards and then I'd like to see the re-org the directories patch again, unless people think that's a bad idea right now. Finally, the DM + SPL changes do need to come in, whatever still isn't, and we'll sort things out. I think that means Albert needs to ack a few changes tho, yes? As always, if anything is broken please speak up. Thanks all! -- Tom

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[U-Boot] [PATCH] Documentation: gpio: fix bindings document
by Masahiro Yamada 18 Feb '15

18 Feb '15

[ imported from Linux Kernel, commit 74981fb81d83 ] Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Acked-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- doc/device-tree-bindings/gpio/gpio.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/doc/device-tree-bindings/gpio/gpio.txt b/doc/device-tree-bindings/gpio/gpio.txt index b9bd1d6..f7a158d 100644 --- a/doc/device-tree-bindings/gpio/gpio.txt +++ b/doc/device-tree-bindings/gpio/gpio.txt @@ -69,7 +69,8 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. ---------------------------------- A gpio-specifier should contain a flag indicating the GPIO polarity; active- -high or active-low. If it does, the follow best practices should be followed: +high or active-low. If it does, the following best practices should be +followed: The gpio-specifier's polarity flag should represent the physical level at the GPIO controller that achieves (or represents, for inputs) a logically asserted @@ -147,7 +148,7 @@ contains information structures as follows: numeric-gpio-range ::= <pinctrl-phandle> <gpio-base> <pinctrl-base> <count> named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>' - gpio-phandle : phandle to pin controller node. + pinctrl-phandle : phandle to pin controller node gpio-base : Base GPIO ID in the GPIO controller pinctrl-base : Base pinctrl pin ID in the pin controller count : The number of GPIOs/pins in this range -- 1.9.1

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[U-Boot] [PATCH 1/3] dm: cros_ec: Convert to Kconfig
by Simon Glass 18 Feb '15

18 Feb '15

Since both I2C and SPI are converted to Kconfig, we can convert cros_ec to Kconfig for these buses. LPC will need to wait until driver mode PCI is available. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- configs/peach-pi_defconfig | 4 ++++ configs/peach-pit_defconfig | 4 ++++ configs/sandbox_defconfig | 5 ++++ configs/snow_defconfig | 5 ++++ drivers/input/Kconfig | 6 +++++ drivers/misc/Kconfig | 48 ++++++++++++++++++++++++++++++++++++- include/configs/exynos5-dt-common.h | 3 --- include/configs/peach-pi.h | 1 - include/configs/peach-pit.h | 1 - include/configs/sandbox.h | 4 ---- include/configs/snow.h | 2 -- 11 files changed, 71 insertions(+), 12 deletions(-) diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 8ada0db..333e335 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -3,3 +3,7 @@ CONFIG_SPL=y +S:CONFIG_ARCH_EXYNOS=y +S:CONFIG_TARGET_PEACH_PI=y CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi" +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index b944b3b..cf84444 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -3,3 +3,7 @@ CONFIG_SPL=y +S:CONFIG_ARCH_EXYNOS=y +S:CONFIG_TARGET_PEACH_PIT=y CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit" +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 0bf5ea3..70f5b86 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -7,3 +7,8 @@ CONFIG_DM=y CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_CROS_EC=y +CONFIG_DM_CROS_EC=y +CONFIG_CROS_EC_SANDBOX=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 14ed793..353ddb0 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -3,3 +3,8 @@ CONFIG_SPL=y +S:CONFIG_ARCH_EXYNOS=y +S:CONFIG_TARGET_SNOW=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow" +CONFIG_CROS_EC=y +CONFIG_DM_CROS_EC=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index e69de29..bb00de7 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -0,0 +1,6 @@ +config CROS_EC_KEYB + bool "Enable Chrome OS EC keyboard support" + help + Most ARM Chromebooks use an EC to provide access to the keyboard. + Messages are used to request key scans from the EC and these are + then decoded into keys by this driver. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 813d1c2..0df25c3 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -1,3 +1,49 @@ +config CMD_CROS_EC + bool "Enable crosec command" + depends on CROS_EC + help + Enable command-line access to the Chrome OS EC (Embedded + Controller). This provides the 'crosec' command which has + a number of sub-commands for performing EC tasks such as + updating its flash, accessing a small saved context area + and talking to the I2C bus behind the EC (if there is one). + +config CROS_EC + bool "Enable Chrome OS EC" + help + Enable access to the Chrome OS EC. This is a separate + microcontroller typically available on a SPI bus on Chromebooks. It + provides access to the keyboard, some internal storage and may + control access to the battery and main PMIC depending on the + device. You can use the 'crosec' command to access it. + +config CROS_EC_I2C + bool "Enable Chrome OS EC I2C driver" + depends on CROS_EC + help + Enable I2C access to the Chrome OS EC. This is used on older + ARM Chromebooks such as snow and spring before the standard bus + changed to SPI. The EC will accept commands across the I2C using + a special message protocol, and provide responses. + +config CROS_EC_LPC + bool "Enable Chrome OS EC LPC driver" + depends on CROS_EC + help + Enable I2C access to the Chrome OS EC. This is used on x86 + Chromebooks such as link and falco. The keyboard is provided + through a legacy port interface, so on x86 machines the main + function of the EC is power and thermal management. + +config CROS_EC_SPI + bool "Enable Chrome OS EC SPI driver" + depends on CROS_EC + help + Enable SPI access to the Chrome OS EC. This is used on newer + ARM Chromebooks such as pit, pi and nyan-big. The SPI interface + provides a faster and more robust interface than I2C but the bugs + are less interesting. + config DM_CROS_EC bool "Enable Driver Model for Chrome OS EC" depends on DM @@ -5,5 +51,5 @@ config DM_CROS_EC Enable driver model for the Chrome OS EC interface. This allows the cros_ec SPI driver to operate with CONFIG_DM_SPI but otherwise makes few changes. Since cros_ec also supports - I2C and LPC (which don't support driver model yet), a full + LPC (which doesn't support driver model yet), a full conversion is not yet possible. diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index 9cef0b0..b1b8e1a 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -24,9 +24,6 @@ #define CONFIG_POWER_TPS65090 /* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC #define CONFIG_KEYBOARD #endif diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index f724164..f04f061 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -43,7 +43,6 @@ #endif #define CONFIG_POWER_TPS65090_EC -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index de12a9e..b5efbdc 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -43,7 +43,6 @@ #endif #define CONFIG_POWER_TPS65090_EC -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 5c11650..febbfb6 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -141,9 +141,6 @@ #define CONFIG_BOOTARGS "" -#define CONFIG_CROS_EC -#define CONFIG_CMD_CROS_EC -#define CONFIG_CROS_EC_SANDBOX #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_BOARD_LATE_INIT @@ -166,7 +163,6 @@ #define LCD_BPP LCD_COLOR16 #define CONFIG_LCD_BMP_RLE8 -#define CONFIG_CROS_EC_KEYB #define CONFIG_KEYBOARD #define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \ diff --git a/include/configs/snow.h b/include/configs/snow.h index ce6676e..fe802f2 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -20,9 +20,7 @@ #include <configs/exynos5-dt-common.h> -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_POWER_TPS65090_I2C -#define CONFIG_DM_CROS_EC #define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH 1/2] ARM: tegra: add function to clear pinmux CLAMPING bit
by Stephen Warren 18 Feb '15

18 Feb '15

From: Stephen Warren <swarren(a)nvidia.com> This is needed to correctly apply the new Jetson TK1 pinmux config. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/cpu/tegra-common/pinmux-common.c | 10 ++++++++++ arch/arm/include/asm/arch-tegra/pinmux.h | 3 ++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c index 6e3ab0c14ca2..692de7629b9b 100644 --- a/arch/arm/cpu/tegra-common/pinmux-common.c +++ b/arch/arm/cpu/tegra-common/pinmux-common.c @@ -100,6 +100,16 @@ void pinmux_set_tristate_input_clamping(void) val |= CLAMP_INPUTS_WHEN_TRISTATED; writel(val, reg); } + +void pinmux_clear_tristate_input_clamping(void) +{ + u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0); + u32 val; + + val = readl(reg); + val &= ~CLAMP_INPUTS_WHEN_TRISTATED; + writel(val, reg); +} #endif void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index da477697bf02..ab764960fa7f 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -81,8 +81,9 @@ struct pmux_pingrp_config { }; #if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) -/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ +/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ void pinmux_set_tristate_input_clamping(void); +void pinmux_clear_tristate_input_clamping(void); #endif /* Set the mux function for a pin group */ -- 1.9.1

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[U-Boot] [PATCH 0/4] ARM / OMAP5 / DRA7 : Enable proper l2actl configuration
by Nishanth Menon 18 Feb '15

18 Feb '15

Hi, Triggered by a user report, it was seen that recommended errata workaround and performance trade-offs as recommended by TI architects for ARM configuration was not being followed in OMAP5+ ARM A15 platforms in u-boot configuration. Note OMAP5, DRA7 all share the same cortex A15 revision (ID=0x412fc0f2) and the workarounds and improvement configurations apply equally. Certain errata workaround done in this series obviously have the controversy potential considering that each of the SoCs implement workaround based on secure monitor calls, but both the service requested and the parameters of secure monitor calls can be widely variant. Examples: OMAP family of processors have quite the family of SMC calls: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/a… meanwhile Exynos has a much simpler invocation: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/a… To maintain some resemblance of symmetry the following series introduces a arch/machine dependent errata macro which must be enabled prior to any of such workarounds can be implemented. I am open to better ways of doing this which might benefit others in ARM community with similar needs. Lets discuss. These patches are based on: v2015.04-rc1 but also apply on latest master. Testing: AM5728 based Beagleboard-X15: http://pastebin.ubuntu.com/10280020/ DRA722 based Evm: http://pastebin.ubuntu.com/10280074/ DRA742 based Evm: http://pastebin.ubuntu.com/10280115/ OMAP5432 uEVM: http://pastebin.ubuntu.com/10280176/ OMAP4460 PandaBoard-ES: http://pastebin.ubuntu.com/10280208/ (just sanity) Appropriate CP15 configuration was cross verified by Lauterbach or by a custom kernel patch (http://paste.ubuntu.org.cn/2410711). Angela Stegmaier (1): configs: ti_omap5_common: Enable workaround for ARM errata 798870 Nishanth Menon (2): ARM: OMAP: Change set_pl310_ctrl_reg to be generic ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration Praveen Rao (1): ARM / OMAP5: Add workaround for ARM errata 798870 arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 8 ++++-- arch/arm/cpu/armv7/omap4/hwinit.c | 4 +-- arch/arm/cpu/armv7/omap5/hwinit.c | 16 +++++++++++ arch/arm/cpu/armv7/omap5/lowlevel_init.S | 35 ++++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/sys_proto.h | 5 +++- arch/arm/include/asm/arch-omap5/sys_proto.h | 4 +++ include/configs/ti_omap5_common.h | 4 +++ 7 files changed, 70 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S -- 1.7.9.5 Regards, Nishanth Menon

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[U-Boot] [U-boot][PATCH v2] keystone2: add support for UART download
by Vitaly Andrianov 17 Feb '15

17 Feb '15

Currently to flash u-boot image onto NAND or SPI NOR flash, very first time user need to use Code Composer Studio (CCS). This is cumbersome for an user not familiar with CCS. This patch add simpler procedure using uart boot mode for K2 EVMs. When UART bootmode is set and board is rebooted, the ROM boot loader transfers the image at the beginning of the internal RAM. After the transfer is complete the boot-loader sets the PC to the first internal RAM address 0x0c000000. The u-boot.bin is linked to the address 0x0c001000. In order to use the u-boot.bin as an image for UART download, we need to add 4K zeros prefix that act as 1K NOP instructions before reaching 0xc001000. Signed-off-by: Vitaly Andrianov <vitalya(a)ti.com> Acked-by: Murali Karicheri <m-karicheri2(a)ti.com> Tested-by: Murali Karicheri <m-karicheri2(a)ti.com> --- Changes in V2: - removed extra EOL - "MSMC" replaced by "internal RAM" in the commit message Makefile | 6 ++++++ board/ti/ks2_evm/README | 15 +++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/Makefile b/Makefile index 36a9a28..7a86cac 100644 --- a/Makefile +++ b/Makefile @@ -940,6 +940,12 @@ u-boot-nand.gph: u-boot.bin FORCE $(call if_changed,mkimage) @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@ +u-boot.uart.pad: + @dd if=/dev/zero bs=4 count=1024 2>/dev/null > $@ + +u-boot.uart: u-boot.uart.pad u-boot.bin FORCE + $(call if_changed,cat) + # x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including # reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in # the middle. diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index 9ee90a4..7e2e096 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -81,6 +81,21 @@ To build u-boot-nand.gph >make k2hk_evm_defconfig >make u-boot-nand.gph +To build u-boot.uart + >make k2hk_evm_defconfig + >make u-boot.uart + +Load and Run U-Boot on keystone EVMs using UART download +======================================================== + +Open BMC and regular UART terminals. + +1. On the regular UART port start xmodem transfer of the u-boot.uart +2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM + BMC> bootmode #4 + MBC> reboot +3. When xmodem is complete you should see the u-boot starts on the UART port + Load and Run U-Boot on keystone EVMs using CCS ========================================= -- 1.9.1

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