February 2015 - U-Boot

[U-Boot] [PATCH v3 0/7] kconfig: turnaround into single .config
by Masahiro Yamada 26 Feb '15

26 Feb '15

Masahiro Yamada (6): ARM: UniPhier: set CONFIG_SYS_MALLOC_F to the global default value malloc_f: fix broken .config caused by CONFIG_SYS_MALLOC_F malloc_f: add ARCH_MALLOC_F_LEN to specify SoC-default malloc_f_len kconfig: switch to single .config configuration kconfig: remove unneeded dependency on !SPL_BUILD malloc_f: enable SYS_MALLOC_F by default if DM is on Simon Glass (1): kconfig: Adjust ordering so that defaults work as expected Kconfig | 32 +--- arch/arm/Kconfig | 7 +- arch/arm/cpu/arm1176/bcm2835/Kconfig | 6 +- arch/arm/cpu/armv7/exynos/Kconfig | 30 ++-- arch/arm/cpu/armv7/omap3/Kconfig | 12 +- arch/arm/cpu/armv7/s5pc1xx/Kconfig | 4 +- arch/arm/cpu/armv7/tegra-common/Kconfig | 20 ++- arch/arm/cpu/armv7/uniphier/Kconfig | 8 - arch/x86/Kconfig | 6 +- board/amcc/canyonlands/Kconfig | 8 - board/compulab/cm_t335/Kconfig | 6 +- board/gumstix/pepper/Kconfig | 6 +- board/isee/igep0033/Kconfig | 6 +- board/phytec/pcm051/Kconfig | 6 +- board/samsung/goni/Kconfig | 6 +- board/samsung/smdkc100/Kconfig | 6 +- board/silica/pengwyn/Kconfig | 6 +- board/ti/am335x/Kconfig | 12 +- common/Kconfig | 1 - config.mk | 5 + configs/ph1_ld4_defconfig | 2 +- configs/ph1_pro4_defconfig | 2 +- configs/ph1_sld8_defconfig | 2 +- doc/README.kconfig | 132 ++++------------ drivers/core/Kconfig | 16 +- drivers/mtd/nand/Kconfig | 6 +- dts/Kconfig | 1 - include/config_uncmd_spl.h | 13 ++ scripts/Makefile.autoconf | 36 +++-- scripts/Makefile.build | 3 +- scripts/Makefile.spl | 10 +- scripts/Makefile.uncmd_spl | 18 +++ scripts/multiconfig.sh | 261 +------------------------------- 33 files changed, 183 insertions(+), 512 deletions(-) create mode 100644 scripts/Makefile.uncmd_spl -- 1.9.1

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Re: [U-Boot] Odroid XU3 - exynos5422 - SPL - iRAM/sRAM address
by Sjoerd Simons 26 Feb '15

26 Feb '15

(Corrected the u-boot list address in the cc of this thread and added Kevin hilman who is also quite interested in this topic) On Tue, 2015-01-20 at 10:36 +0100, Sjoerd Simons wrote: > Hey Suriyan, > > I just noticed the patchset Akshay Saraswat sent (Add support for > booting multiple cores), which would hopefully fix some issues wrt. > booting secondary cores we've seen on the XU3 thusfar. Unfortunately, > those fixes need to be applied in the SPL stage, hence coming back to > the BL2 story :). Any updates you can share? > > Separately i do wonder if getting a (very basic?) signed BL2 to > chainload an unsigned SPL might not be the best way forward here. Would > allow us to fix SPL issues in u-boot without having to ask hardkernel to > sign every time ? :/ > > > On Fri, 2014-12-19 at 15:45 -0800, Suriyan Ramasami wrote: > > Just to close the loop. > > > > For the XU3, scanning memory, I found the signed BL2 loaded at address > > 0x02027000. > > Regards > > - Suriyan > > > > PS: Any pointers with regards to mem_ctrl_init() is appreciated. > > > > On Fri, Dec 19, 2014 at 12:43 PM, Suriyan Ramasami <suriyan.r(a)gmail.com> wrote: > > > Hello All, > > > Greetings! > > > > > > I have been dabbling with trying to get mainline SPL working on > > > the Odroid XU3. The issue that I am facing is that currently I do not > > > know what address the BL1 loads and passes control to the SPL (signed > > > BL2). > > > Of course, I could get another SPL signed from Hard kernel and > > > have the address written out in some memory address, but I thought if > > > someone has access to the documents it might be faster to get this > > > information. > > > > > > As an update ... > > > So far, I have successfully gotten an Hardkernel based SPL to > > > chain load an unsigned SPL from mainline. I am hitting some issues in > > > mem_ctrl_init() or so I think. I was wondering if the issues were > > > cause of it being initialized twice (one from the signed BL2) and the > > > other from the mainline SPL that is chain loaded. > > > > > > Thanks > > > - Suriyan > >

4 16

[U-Boot] rpi_2 builds fine with make, fails with buildman
by Albert ARIBAUD 25 Feb '15

25 Feb '15

Hello, Can anyone confirm that on current u-boot/master, rpi_2 build fine with git clean -xfd; make rpi_2_defconfig; make but fails with tools/buildman/buildman rpi_2 with the following error: > arm: + rpi_2 > +make[3]: *** No rule to make target 'arch/arm/cpu/armv7/bcm2835/../../arm1176/bcm2835//init.o', needed by 'arch/arm/cpu/armv7/bcm2835/built-in.o'. Stop. > +make[2]: *** [arch/arm/cpu/armv7/bcm2835] Error 2 > +make[1]: *** [arch/arm/cpu/armv7] Error 2 > +make: *** [sub-make] Error 2 My gut feeling is that the problem lies with the fact that arch/arm/cpu/armv7/bcm2835/ contains a Makefile which refers to init.o, reset.o, timer.o and mbox.o but the source code for these resides in another directory, arch/arm/cpu/arm1176/bcm2835/. CC:ing Stephen as directory arch/arm/cpu/armv7/bcm2835/ was introduced by his commit db75356f (committed by Tom, also cc:) and Simon, since the issue is related to buildman. Amicalement, -- Albert.

2 2

[U-Boot] [PATCH][v6] crypto/fsl - Add progressive hashing support using hardware acceleration.
by Gaurav Rana 25 Feb '15

25 Feb '15

Currently only normal hashing is supported using hardware acceleration. Added support for progressive hashing using hardware. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana(a)freescale.com> CC: Simon Glass <sjg(a)chromium.org> --- Changes in v6: Modify description for CONFIG_SHA256, CONFIG_SHA256, CONFIG_SHA_PROG_HW_ACCEL, CONFIG_SHA_HW_ACCEL in README and Kconfig. Changes in v5: Modify description for CONFIG_SHA256, CONFIG_SHA256. Changes in v4: Add CONFIG_SHA256, CONFIG_SHA256, CONFIG_SHA_PROG_HW_ACCEL, CONFIG_SHA_HW_ACCEL to Kconfig. Modify README for these configs descriptions. Changes in v3: Remove duplication of code and create function gen_hash_type. Modify MAX_SG to MAX_SG_32 Changes in v2: Merge to common functions for SHA1 and SHA256. Replace malloc and memset with calloc. Remove cast conversions for void* pointers. Replace hardcoded errors with Macros. Corrected comments. Kconfig | 4 +- README | 20 ++++-- common/hash.c | 10 +++ drivers/crypto/fsl/fsl_hash.c | 138 +++++++++++++++++++++++++++++++++++++++++- drivers/crypto/fsl/fsl_hash.h | 34 +++++++++++ include/fsl_sec.h | 26 ++++++++ include/hw_sha.h | 41 ++++++++++++- lib/Kconfig | 36 +++++++++++ 8 files changed, 302 insertions(+), 7 deletions(-) create mode 100644 drivers/crypto/fsl/fsl_hash.h diff --git a/Kconfig b/Kconfig index 75bab7f..fb012cf 100644 --- a/Kconfig +++ b/Kconfig @@ -141,7 +141,9 @@ config FIT_SIGNATURE select RSA help This option enables signature verification of FIT uImages, - using a hash signed and verified using RSA. + using a hash signed and verified using RSA. If + CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive + hashing is available using hardware, RSA library will use it. See doc/uImage.FIT/signature.txt for more details. config SYS_EXTRA_OPTIONS diff --git a/README b/README index ba57dc5..9c139a0 100644 --- a/README +++ b/README @@ -3152,8 +3152,18 @@ CBFS (Coreboot Filesystem) support Enable the hash verify command (hash -v). This adds to code size a little. - CONFIG_SHA1 - support SHA1 hashing - CONFIG_SHA256 - support SHA256 hashing + CONFIG_SHA1 - This option enables support of hashing using SHA1 + algorithm. The hash is calculated in software. + CONFIG_SHA256 - This option enables support of hashing using + SHA256 algorithm. The hash is calculated in software. + CONFIG_SHA_HW_ACCEL - This option enables hardware acceleration + for SHA1/SHA256 hashing. + This affects the 'hash' command and also the + hash_lookup_algo() function. + CONFIG_SHA_PROG_HW_ACCEL - This option enables + hardware-acceleration for SHA1/SHA256 progressive hashing. + Data can be streamed in a block at a time and the hashing + is performed in hardware. Note: There is also a sha1sum command, which should perhaps be deprecated in favour of 'hash sha1'. @@ -3447,8 +3457,10 @@ FIT uImage format: CONFIG_FIT_SIGNATURE This option enables signature verification of FIT uImages, - using a hash signed and verified using RSA. See - doc/uImage.FIT/signature.txt for more details. + using a hash signed and verified using RSA. If + CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive + hashing is available using hardware, RSA library will use it. + See doc/uImage.FIT/signature.txt for more details. WARNING: When relying on signed FIT images with required signature check the legacy image format is default diff --git a/common/hash.c b/common/hash.c index d154d02..9e9f84b 100644 --- a/common/hash.c +++ b/common/hash.c @@ -127,11 +127,21 @@ static struct hash_algo hash_algo[] = { SHA1_SUM_LEN, hw_sha1, CHUNKSZ_SHA1, +#ifdef CONFIG_SHA_PROG_HW_ACCEL + hw_sha_init, + hw_sha_update, + hw_sha_finish, +#endif }, { "sha256", SHA256_SUM_LEN, hw_sha256, CHUNKSZ_SHA256, +#ifdef CONFIG_SHA_PROG_HW_ACCEL + hw_sha_init, + hw_sha_update, + hw_sha_finish, +#endif }, #endif #ifdef CONFIG_SHA1 diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index d77f257..c298404 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -10,6 +10,9 @@ #include "jobdesc.h" #include "desc.h" #include "jr.h" +#include "fsl_hash.h" +#include <hw_sha.h> +#include <asm-generic/errno.h> #define CRYPTO_MAX_ALG_NAME 80 #define SHA1_DIGEST_SIZE 20 @@ -39,6 +42,122 @@ static struct caam_hash_template driver_hash[] = { }, }; +static enum caam_hash_algos get_hash_type(struct hash_algo *algo) +{ + if (!strcmp(algo->name, driver_hash[SHA1].name)) + return SHA1; + else + return SHA256; +} + +/* Create the context for progressive hashing using h/w acceleration. + * + * @ctxp: Pointer to the pointer of the context for hashing + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -ENOMEM on error + */ +static int caam_hash_init(void **ctxp, enum caam_hash_algos caam_algo) +{ + *ctxp = calloc(1, sizeof(struct sha_ctx)); + if (*ctxp == NULL) { + debug("Cannot allocate memory for context\n"); + return -ENOMEM; + } + return 0; +} + +/* + * Update sg table for progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * We support at most 32 Scatter/Gather Entries. + * + * @hash_ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -EINVAL on error + */ +static int caam_hash_update(void *hash_ctx, const void *buf, + unsigned int size, int is_last, + enum caam_hash_algos caam_algo) +{ + uint32_t final = 0; + dma_addr_t addr = virt_to_phys((void *)buf); + struct sha_ctx *ctx = hash_ctx; + + if (ctx->sg_num >= MAX_SG_32) { + free(ctx); + return -EINVAL; + } + +#ifdef CONFIG_PHYS_64BIT + ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32; +#else + ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0; +#endif + ctx->sg_tbl[ctx->sg_num].addr_lo = addr; + + sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, + (size & SG_ENTRY_LENGTH_MASK)); + + ctx->sg_num++; + + if (is_last) { + final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) | + SG_ENTRY_FINAL_BIT; + sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final); + } + + return 0; +} + +/* + * Perform progressive hashing on the given buffer and copy hash at + * destination buffer + * + * The context is freed after completion of hash operation. + * + * @hash_ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -EINVAL on error + */ +static int caam_hash_finish(void *hash_ctx, void *dest_buf, + int size, enum caam_hash_algos caam_algo) +{ + uint32_t len = 0; + struct sha_ctx *ctx = hash_ctx; + int i = 0, ret = 0; + + if (size < driver_hash[caam_algo].digestsize) { + free(ctx); + return -EINVAL; + } + + for (i = 0; i < ctx->sg_num; i++) + len += (sec_in32(&ctx->sg_tbl[i].len_flag) & + SG_ENTRY_LENGTH_MASK); + + inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len, + ctx->hash, + driver_hash[caam_algo].alg_type, + driver_hash[caam_algo].digestsize, + 1); + + ret = run_descriptor_jr(ctx->sha_desc); + + if (ret) + debug("Error %x\n", ret); + else + memcpy(dest_buf, ctx->hash, sizeof(ctx->hash)); + + free(ctx); + return ret; +} + int caam_hash(const unsigned char *pbuf, unsigned int buf_len, unsigned char *pout, enum caam_hash_algos algo) { @@ -48,7 +167,7 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); - return -1; + return -ENOMEM; } inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout, @@ -75,3 +194,20 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, if (caam_hash(pbuf, buf_len, pout, SHA1)) printf("CAAM was not setup properly or it is faulty\n"); } + +int hw_sha_init(struct hash_algo *algo, void **ctxp) +{ + return caam_hash_init(ctxp, get_hash_type(algo)); +} + +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last) +{ + return caam_hash_update(ctx, buf, size, is_last, get_hash_type(algo)); +} + +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size) +{ + return caam_hash_finish(ctx, dest_buf, size, get_hash_type(algo)); +} diff --git a/drivers/crypto/fsl/fsl_hash.h b/drivers/crypto/fsl/fsl_hash.h new file mode 100644 index 0000000..f5be651 --- /dev/null +++ b/drivers/crypto/fsl/fsl_hash.h @@ -0,0 +1,34 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef _SHA_H +#define _SHA_H + +#include <fsl_sec.h> +#include <hash.h> +#include "jr.h" + +/* We support at most 32 Scatter/Gather Entries.*/ +#define MAX_SG_32 32 + +/* + * Hash context contains the following fields + * @sha_desc: Sha Descriptor + * @sg_num: number of entries in sg table + * @len: total length of buffer + * @sg_tbl: sg entry table + * @hash: index to the hash calculated + */ +struct sha_ctx { + uint32_t sha_desc[64]; + uint32_t sg_num; + uint32_t len; + struct sg_entry sg_tbl[MAX_SG_32]; + u8 hash[HASH_MAX_DIGEST_SIZE]; +}; + +#endif diff --git a/include/fsl_sec.h b/include/fsl_sec.h index aa850a3..b6e6f04 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -175,6 +175,32 @@ struct jr_regs { u32 jrcr; }; +/* + * Scatter Gather Entry - Specifies the the Scatter Gather Format + * related information + */ +struct sg_entry { +#ifdef CONFIG_SYS_FSL_SEC_LE + uint32_t addr_lo; /* Memory Address - lo */ + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint16_t reserved_zero; +#else + uint16_t reserved_zero; + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint32_t addr_lo; /* Memory Address - lo */ +#endif + + uint32_t len_flag; /* Length of the data in the frame */ +#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF +#define SG_ENTRY_EXTENSION_BIT 0x80000000 +#define SG_ENTRY_FINAL_BIT 0x40000000 + uint32_t bpid_offset; +#define SG_ENTRY_BPID_MASK 0x00FF0000 +#define SG_ENTRY_BPID_SHIFT 16 +#define SG_ENTRY_OFFSET_MASK 0x00001FFF +#define SG_ENTRY_OFFSET_SHIFT 0 +}; + int sec_init(void); #endif diff --git a/include/hw_sha.h b/include/hw_sha.h index 783350d..ab19a99 100644 --- a/include/hw_sha.h +++ b/include/hw_sha.h @@ -7,7 +7,7 @@ */ #ifndef __HW_SHA_H #define __HW_SHA_H - +#include <hash.h> /** * Computes hash value of input pbuf using h/w acceleration @@ -34,4 +34,43 @@ void hw_sha256(const uchar * in_addr, uint buflen, */ void hw_sha1(const uchar * in_addr, uint buflen, uchar * out_addr, uint chunk_size); + +/* + * Create the context for sha progressive hashing using h/w acceleration + * + * @algo: Pointer to the hash_algo struct + * @ctxp: Pointer to the pointer of the context for hashing + * @return 0 if ok, -ve on error + */ +int hw_sha_init(struct hash_algo *algo, void **ctxp); + +/* + * Update buffer for sha progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @return 0 if ok, -ve on error + */ +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last); + +/* + * Copy sha hash result at destination location + * + * The context is freed after completion of hash operation or after an error. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @return 0 if ok, -ve on error + */ +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size); + #endif diff --git a/lib/Kconfig b/lib/Kconfig index a1f30a2..c9d2767 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -29,4 +29,40 @@ config SYS_HZ source lib/rsa/Kconfig +menu "Hashing Support" + +config SHA1 + bool "Enable SHA1 support" + help + This option enables support of hashing using SHA1 algorithm. + The hash is calculated in software. + The SHA1 algorithm produces a 160-bit (20-byte) hash value + (digest). + +config SHA256 + bool "Enable SHA256 support" + help + This option enables support of hashing using SHA256 algorithm. + The hash is calculated in software. + The SHA256 algorithm produces a 256-bit (32-byte) hash value + (digest). + +config SHA_HW_ACCEL + bool "Enable hashing using hardware" + help + This option enables hardware acceleration + for SHA1/SHA256 hashing. + This affects the 'hash' command and also the + hash_lookup_algo() function. + +config SHA_PROG_HW_ACCEL + bool "Enable Progressive hashing support using hardware" + depends on SHA_HW_ACCEL + help + This option enables hardware-acceleration for + SHA1/SHA256 progressive hashing. + Data can be streamed in a block at a time and the hashing + is performed in hardware. +endmenu + endmenu -- 1.8.1.4

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[U-Boot] [PATCH][v3] crypto/fsl: Make function names consistent for blob encapsulation/decapsulation.
by Gaurav Rana 25 Feb '15

25 Feb '15

This patch does the following: 1. The function names for encapsulation and decapsulation were inconsitent in freescale's implementation and cmd_blob file. This patch corrects the issues. 2. The function protopye is also modified to change the length parameter from u8 to u32 to allow encapsulation and decapsulation of larger images. 3. Modified the description of km paramter in the command usage for better readability. Signed-off-by: Gaurav Rana <gaurav.rana(a)freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> --- Changes in v3: Fixed blob_help_text[] array declaration. Changes in v2: Modify blob_help_text[] array common/cmd_blob.c | 18 ++++++++++-------- drivers/crypto/fsl/fsl_blob.c | 4 ++-- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/common/cmd_blob.c b/common/cmd_blob.c index 82ecaf0..d3f22a1 100644 --- a/common/cmd_blob.c +++ b/common/cmd_blob.c @@ -90,17 +90,19 @@ static char blob_help_text[] = "enc src dst len km - Encapsulate and create blob of data\n" " $len bytes long at address $src and\n" " store the result at address $dst.\n" - " $km is the 16 byte key modifier\n" - " is also required for generation/use as\n" - " key for cryptographic operation. Key\n" - " modifier should be 16 byte long.\n" + " $km is the address where the key\n" + " modifier is stored.\n" + " The modifier is required for generation\n" + " /use as key for cryptographic operation.\n" + " Key modifier should be 16 byte long.\n" "blob dec src dst len km - Decapsulate the blob of data at address\n" " $src and store result of $len byte at\n" " addr $dst.\n" - " $km is the 16 byte key modifier\n" - " is also required for generation/use as\n" - " key for cryptographic operation. Key\n" - " modifier should be 16 byte long.\n"; + " $km is the address where the key\n" + " modifier is stored.\n" + " The modifier is required for generation\n" + " /use as key for cryptographic operation.\n" + " Key modifier should be 16 byte long.\n"; U_BOOT_CMD( blob, 6, 1, do_blob, diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index bc01075..9923bcb 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -11,7 +11,7 @@ #include "desc.h" #include "jr.h" -int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) +int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) { int ret, i = 0; u32 *desc; @@ -36,7 +36,7 @@ int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) return ret; } -int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len) +int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) { int ret, i = 0; u32 *desc; -- 1.8.1.4

2 1

[U-Boot] [PATCH v2] arm: ls1021x: Add support for initializing CAAM's stream id
by Alison Wang 25 Feb '15

25 Feb '15

There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- Changes in v2: - Move changing CCSR macros to a separated patch. arch/arm/include/asm/arch-ls102xa/config.h | 1 + .../include/asm/arch-ls102xa/ls102xa_stream_id.h | 57 ++++++++++++++++++++++ board/freescale/common/ls102xa_stream_id.c | 15 ++++++ board/freescale/ls1021aqds/ls1021aqds.c | 21 ++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 21 ++++++++ 5 files changed, 115 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 5e934da..f200bc8 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -36,6 +36,7 @@ #define CONFIG_SYS_LS102XA_USB1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h index abd70fc..fa571b3 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -7,11 +7,68 @@ #ifndef __FSL_LS102XA_STREAM_ID_H_ #define __FSL_LS102XA_STREAM_ID_H_ +#include <fsl_sec.h> + +#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ + { .compat = name, \ + .id = { idA }, .num_ids = 1, \ + .reg_offset = off + CONFIG_SYS_IMMR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ + { .compat = name, \ + .id = { idA, idB }, .num_ids = 2, \ + .reg_offset = off + CONFIG_SYS_IMMR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +/* + * handle both old and new versioned SEC properties: + * "fsl,secX.Y" became "fsl,sec-vX.Y" during development + */ +#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \ + offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \ + SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum) + +/* This is a bit evil since we treat rtic param as both a string & hex value */ +#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ + SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) + +#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ + SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ + offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, 0) + +struct liodn_id_table { + const char *compat; + u32 id[2]; + u8 num_ids; + phys_addr_t compat_offset; + unsigned long reg_offset; +}; + struct smmu_stream_id { uint16_t offset; uint16_t stream_id; char dev_name[32]; }; +void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size); void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num); #endif diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c index 6154c9c..f434269 100644 --- a/board/freescale/common/ls102xa_stream_id.c +++ b/board/freescale/common/ls102xa_stream_id.c @@ -16,3 +16,18 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) for (i = 0; i < num; i++) out_be32(scfg + id[i].offset, id[i].stream_id); } + +void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size) +{ + int i; + u32 liodn; + + for (i = 0; i < size; i++) { + if (tbl[i].num_ids == 2) + liodn = (tbl[i].id[0] << 16) | tbl[i].id[1]; + else + liodn = tbl[i].id[0]; + + out_le32((uint32_t *)(tbl[i].reg_offset), liodn); + } +} diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index f08e54f..a578ba7 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -450,6 +450,25 @@ static struct csu_ns_dev ns_dev[] = { }; #endif +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), + SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), +}; + struct smmu_stream_id dev_stream_id[] = { { 0x100, 0x01, "ETSEC MAC1" }, { 0x104, 0x02, "ETSEC MAC2" }, @@ -489,6 +508,8 @@ int board_init(void) config_serdes_mux(); #endif + ls1021x_config_caam_stream_id(sec_liodn_tbl, + ARRAY_SIZE(sec_liodn_tbl)); ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 8ab229d..8b73172 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -389,6 +389,25 @@ static struct csu_ns_dev ns_dev[] = { }; #endif +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), + SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), +}; + struct smmu_stream_id dev_stream_id[] = { { 0x100, 0x01, "ETSEC MAC1" }, { 0x104, 0x02, "ETSEC MAC2" }, @@ -425,6 +444,8 @@ int board_init(void) #endif #endif + ls1021x_config_caam_stream_id(sec_liodn_tbl, + ARRAY_SIZE(sec_liodn_tbl)); ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] arm: ls102xa: workaround for cache coherency problem
by Chenhui Zhao 25 Feb '15

25 Feb '15

The RCPM FSM may not be reset after power-on, for example, in the cases of cold boot and wakeup from deep sleep. It causes cache coherency problem and may block deep sleep. Therefore, reset them if they are not be reset. Signed-off-by: Chenhui Zhao <chenhui.zhao(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/cpu.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ce2d92f..a61f6d1 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -14,6 +14,13 @@ #include "fsl_epu.h" +#define DCSR_RCPM2_BLOCK_OFFSET 0x223000 +#define DCSR_RCPM2_CPMFSMCR0 0x400 +#define DCSR_RCPM2_CPMFSMSR0 0x404 +#define DCSR_RCPM2_CPMFSMCR1 0x414 +#define DCSR_RCPM2_CPMFSMSR1 0x418 +#define CPMFSMSR_FSM_STATE_MASK 0x7f + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_DISPLAY_CPUINFO) @@ -107,6 +114,27 @@ int cpu_eth_init(bd_t *bis) int arch_cpu_init(void) { void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *rcpm2_base = + (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + u32 state; + + /* + * The RCPM FSM state may not be reset after power-on. + * So, reset them. + */ + state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) & + CPMFSMSR_FSM_STATE_MASK; + if (state != 0) { + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80); + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0); + } + + state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) & + CPMFSMSR_FSM_STATE_MASK; + if (state != 0) { + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80); + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0); + } /* * After wakeup from deep sleep, Clear EPU registers -- 1.9.1

2 1

[U-Boot] [PATCH 1/4] arm/ls102xa: create TLB to map PCIe region
by Minghuan Lian 25 Feb '15

25 Feb '15

LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout. VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\\\\\| |\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\\\\\| ------- <---- 4GB DDR0 space end Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/cpu.c | 203 +++++++++++++++++++++++++++-- arch/arm/include/asm/arch-ls102xa/config.h | 14 ++ 2 files changed, 207 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ce2d92f..18665a3 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -8,6 +8,8 @@ #include <asm/arch/clock.h> #include <asm/io.h> #include <asm/arch/immap_ls102xa.h> +#include <asm/cache.h> +#include <asm/system.h> #include <tsec.h> #include <netdev.h> #include <fsl_esdhc.h> @@ -16,6 +18,197 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_SYS_DCACHE_OFF + +/* + * Bit[1] of the descriptor indicates the descriptor type, + * and bit[0] indicates whether the descriptor is valid. + */ +#define PMD_TYPE_TABLE 0x3 +#define PMD_TYPE_SECT 0x1 + +/* AttrIndx[2:0] */ +#define PMD_ATTRINDX(t) ((t) << 2) + +/* Section */ +#define PMD_SECT_AF (1 << 10) + +#define BLOCK_SIZE_L1 (1UL << 30) +#define BLOCK_SIZE_L2 (1UL << 21) + +/* TTBCR flags */ +#define TTBCR_EAE (1 << 31) +#define TTBCR_T0SZ(x) ((x) << 0) +#define TTBCR_T1SZ(x) ((x) << 16) +#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) +#define TTBCR_IRGN0_NC (0 << 8) +#define TTBCR_IRGN0_WBWA (1 << 8) +#define TTBCR_IRGN0_WT (2 << 8) +#define TTBCR_IRGN0_WBNWA (3 << 8) +#define TTBCR_IRGN0_MASK (3 << 8) +#define TTBCR_ORGN0_NC (0 << 10) +#define TTBCR_ORGN0_WBWA (1 << 10) +#define TTBCR_ORGN0_WT (2 << 10) +#define TTBCR_ORGN0_WBNWA (3 << 10) +#define TTBCR_ORGN0_MASK (3 << 10) +#define TTBCR_SHARED_NON (0 << 12) +#define TTBCR_SHARED_OUTER (2 << 12) +#define TTBCR_SHARED_INNER (3 << 12) +#define TTBCR_EPD0 (0 << 7) +#define TTBCR (TTBCR_SHARED_NON | \ + TTBCR_ORGN0_NC | \ + TTBCR_IRGN0_NC | \ + TTBCR_USING_TTBR0 | \ + TTBCR_EAE) + +/* + * Memory region attributes for LPAE (defined in pgtable): + * + * n = AttrIndx[2:0] + * + * n MAIR + * UNCACHED 000 00000000 + * BUFFERABLE 001 01000100 + * DEV_WC 001 01000100 + * WRITETHROUGH 010 10101010 + * WRITEBACK 011 11101110 + * DEV_CACHED 011 11101110 + * DEV_SHARED 100 00000100 + * DEV_NONSHARED 100 00000100 + * unused 101 + * unused 110 + * WRITEALLOC 111 11111111 + */ +#define MT_MAIR0 0xeeaa4400 +#define MT_MAIR1 0xff000004 +#define MT_STRONLY_ORDER 0 +#define MT_NORMAL_NC 1 +#define MT_DEVICE_MEM 4 +#define MT_NORMAL 7 + +/* The phy_addr must be aligned to 4KB */ +static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr) +{ + u32 value = phy_addr | PMD_TYPE_TABLE; + + page_table[2 * index] = value; + page_table[2 * index + 1] = 0; +} + +/* The phy_addr must be aligned to 4KB */ +static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, + u32 memory_type) +{ + u64 value; + + value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF; + value |= PMD_ATTRINDX(memory_type); + page_table[2 * index] = value & 0xFFFFFFFF; + page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF; +} + +/* + * Start MMU after DDR is available, we create MMU table in DRAM. + * The base address of TTLB is gd->arch.tlb_addr. We use two + * levels of translation tables here to cover 40-bit address space. + * + * The TTLBs are located at PHY 2G~4G. + * + * VA mapping: + * + * ------- <---- 0GB + * | | + * | | + * |-------| <---- 0x24000000 + * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 + * |-------| <---- 0x300000000 + * | | + * |-------| <---- 0x34000000 + * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 + * |-------| <---- 0x40000000 + * | | + * |-------| <---- 0x80000000 DDR0 space start + * |\\\\\\\| + *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space + * |\\\\\\\| + * ------- <---- 4GB DDR0 space end + */ +static void mmu_setup(void) +{ + u32 *level0_table = (u32 *)gd->arch.tlb_addr; + u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000); + u64 va_start = 0; + u32 reg; + int i; + + /* Level 0 Table 2-3 are used to map DDR */ + set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); + set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); + /* Level 0 Table 1 is used to map device */ + set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); + /* Level 0 Table 0 is used to map device including PCIe MEM */ + set_pgtable(level0_table, 0, (u32)level1_table); + + /* Level 1 has 512 entries */ + for (i = 0; i < 512; i++) { + /* Mapping for PCIe 1 */ + if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR && + va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR + + CONFIG_SYS_PCIE_MMAP_SIZE)) + set_pgsection(level1_table, i, + CONFIG_SYS_PCIE1_PHYS_BASE + va_start, + MT_DEVICE_MEM); + /* Mapping for PCIe 2 */ + else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR && + va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR + + CONFIG_SYS_PCIE_MMAP_SIZE)) + set_pgsection(level1_table, i, + CONFIG_SYS_PCIE2_PHYS_BASE + va_start, + MT_DEVICE_MEM); + else + set_pgsection(level1_table, i, + va_start, + MT_DEVICE_MEM); + va_start += BLOCK_SIZE_L2; + } + + asm volatile("dsb sy;isb"); + asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */ + : : "r" (TTBCR) : "memory"); + asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */ + : : "r" ((u32)level0_table), "r" (0) : "memory"); + asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */ + : : "r" (MT_MAIR0) : "memory"); + asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */ + : : "r" (MT_MAIR1) : "memory"); + + /* Set the access control to all-supervisor */ + asm volatile("mcr p15, 0, %0, c3, c0, 0" + : : "r" (~0)); + + /* Enable the mmu */ + reg = get_cr(); + set_cr(reg | CR_M); +} + +/* + * This function is called from lib/board.c. It recreates MMU + * table in main memory. MMU and i/d-cache are enabled here. + */ +void enable_caches(void) +{ + /* Invalidate all TLB */ + mmu_page_table_flush(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + /* Set up and enable mmu */ + mmu_setup(); + + /* Invalidate & Enable d-cache */ + invalidate_dcache_all(); + set_cr(get_cr() | CR_C); +} +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { @@ -78,16 +271,6 @@ int print_cpuinfo(void) } #endif -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - #ifdef CONFIG_FSL_ESDHC int cpu_mmc_init(bd_t *bis) { diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 5e934da..1c32f2e 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -61,6 +61,20 @@ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL +#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL +#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL +#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ +/* + * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) + * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. + */ +#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ + CONFIG_SYS_PCIE1_VIRT_ADDR) +#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ + CONFIG_SYS_PCIE2_VIRT_ADDR) + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM -- 1.9.1

2 5

[U-Boot] [PATCH] arm: ls102xa: Define default values for some CCSR macros
by Alison Wang 25 Feb '15

25 Feb '15

This patch is to define default values for some CCSR macros to make header files cleaner. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 697d4ca..a29c041 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -37,6 +37,43 @@ #define DCFG_DCSR_PORCR1 0 +/* + * Define default values for some CCSR macros to make header files cleaner + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#else +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH v1 0/24] Update ARMv8 LS2085a emulator and simulator boards
by York Sun 25 Feb '15

25 Feb '15

This set update LS2085a for both emulator and simulator "boards". There are also changes to DDR driver to accomodate new features and bug fix. U-boot still runs at EL3. This will change when we have the security monitor in place later. lowlevel.S will be trimmed down once both security monitor and PSCI are in place. Flushing L3 cache (Dickens) code will also be moved into security monitor. U-boot will eventually run at EL2. Arnab Basu (2): ARMv8/fsl-lsch3: Patch cpu node properties in DT for online cores ARMv8/ls2085a: Switch to passing earlycon to kernel Bhupesh Sharma (3): fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accesses armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodes ls2085/configs: Ensure right banners are printed for EMU and SIMU J. German Rivera (1): drivers/mc: Migrated MC Flibs to 0.5.2 Kuldip Giroh (1): ARMv8/LS2085A: HugeTLB support is required by default in LS NADK Stuart Yoder (1): ARMv8/ls2085a: Move kernel image load address York Sun (16): armv8/fsl-lsch3: Change normal memory shareability armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack armv8/ls2085a: Enable cluster timebase for all clusters driver/ddr/fsl: Adjust CAS to preamble override for emulator driver/ddr/fsl: Add bit operation accessors driver/ddr/fsl: Add workaround for A008336 driver/ddr/fsl: Add workround for erratumn A008514 armv8/fsl-lsch3: Add support for second DDR clock driver/ddr/fsl: Add support for multiple DDR clocks ARMv8/LS2085A: Enable auto precharge for DP-DDR driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation ARMv8/LS2085A: Adjust system clock and DDR clock driver/ddr/fsl: Add sync of refresh armv8/fsl-lsch3: Enable workaround for A008336 armv8/fsl-lsch3: Enable erratum workround for A008514 armv8/ls2085a_emu: Enable sync of refresh README | 3 + arch/arm/cpu/armv8/cache.S | 6 + arch/arm/cpu/armv8/cache_v8.c | 18 +- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 62 +----- arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 28 ++- arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 132 +++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/mp.c | 8 + arch/arm/cpu/armv8/fsl-lsch3/mp.h | 1 + arch/arm/cpu/armv8/fsl-lsch3/speed.c | 16 +- arch/arm/include/asm/arch-fsl-lsch3/config.h | 38 ++++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 3 + arch/arm/include/asm/armv8/mmu.h | 3 +- arch/arm/include/asm/global_data.h | 3 + arch/arm/include/asm/system.h | 1 + arch/arm/lib/bootm.c | 2 +- board/freescale/ls2085a/ddr.c | 1 + board/freescale/ls2085a/ls2085a.c | 29 ++- doc/README.fsl-trustzone-components | 25 +++ drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- drivers/ddr/fsl/ctrl_regs.c | 216 ++++++++++++--------- drivers/ddr/fsl/ddr1_dimm_params.c | 18 +- drivers/ddr/fsl/ddr2_dimm_params.c | 12 +- drivers/ddr/fsl/ddr3_dimm_params.c | 8 +- drivers/ddr/fsl/ddr4_dimm_params.c | 8 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 36 +++- drivers/ddr/fsl/lc_common_dimm_params.c | 27 +-- drivers/ddr/fsl/main.c | 29 +-- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 4 +- drivers/ddr/fsl/options.c | 6 +- drivers/ddr/fsl/util.c | 67 ++++++- drivers/net/Makefile | 2 +- drivers/net/{fsl_mc => fsl-mc}/Makefile | 4 +- drivers/net/fsl-mc/dpmng.c | 91 +++++++++ drivers/net/fsl-mc/fsl_dpmng_cmd.h | 49 +++++ drivers/net/{fsl_mc => fsl-mc}/mc.c | 132 ++++++++----- drivers/net/fsl-mc/mc_sys.c | 63 ++++++ include/configs/ls2085a_common.h | 19 +- include/configs/ls2085a_emu.h | 4 + include/configs/ls2085a_simu.h | 3 + include/fsl-mc/fsl_dpmng.h | 121 ++++++++++++ include/{ => fsl-mc}/fsl_mc.h | 0 include/fsl-mc/fsl_mc_cmd.h | 132 +++++++++++++ include/fsl-mc/fsl_mc_sys.h | 26 +++ include/fsl_ddr.h | 23 ++- include/fsl_ddr_dimm_params.h | 2 +- 45 files changed, 1185 insertions(+), 298 deletions(-) create mode 100644 doc/README.fsl-trustzone-components rename drivers/net/{fsl_mc => fsl-mc}/Makefile (75%) create mode 100644 drivers/net/fsl-mc/dpmng.c create mode 100644 drivers/net/fsl-mc/fsl_dpmng_cmd.h rename drivers/net/{fsl_mc => fsl-mc}/mc.c (67%) create mode 100644 drivers/net/fsl-mc/mc_sys.c create mode 100644 include/fsl-mc/fsl_dpmng.h rename include/{ => fsl-mc}/fsl_mc.h (100%) create mode 100644 include/fsl-mc/fsl_mc_cmd.h create mode 100644 include/fsl-mc/fsl_mc_sys.h -- 1.7.9.5

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