February 2015 - U-Boot

[U-Boot] [PATCH v4 00/11] Add support for booting multiple cores
by Akshay Saraswat 28 Feb '15

28 Feb '15

This patch series introduces changes for booting secondary CPUs on Exynos5420 and Exynos5800. Changes since v3: - Patch 2 & 3 : Added errata number in comments. - Patch 2 & 3 : Moved changes to ARM generic file. - Patch 6 : Removed this patch. Not required anymore. Changes since v2: - Patch 7 & 8 : Replaced #ifdef and #ifndef -> if(proid_is_soc()). - Patch 11 : Removed #ifdef from enum definition. Changes since v1: - Added Reviewed-by & Tested-by in the acked patches. - Removed unnecessary CONFIGS and macros. - Changed names of few macros for better understanding in patch 2. - Added MPIDR bit assignment info comment in power_down_core in patch 2. - Changed to SPDX header in sec_boot.S in patch 5. - Fixed compilation error for snow build in patch 11. Akshay Saraswat (9): Exynos542x: Config: Add various configs Exynos542x: CPU: Power down all secondary cores Exynos542x: Add workaround for ARM errata 798870 Exynos542x: Add workaround for ARM errata 799270 Exynos542x: Add workaround for exynos iROM errata Exynos542x: cache: Disable clean/evict push to external Exynos542x: add L2 control register configuration Exynos542x: Fix secondary core booting for thumb Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset Doug Anderson (1): Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800 arch/arm/cpu/armv7/exynos/Makefile | 2 + arch/arm/cpu/armv7/exynos/common_setup.h | 62 +++++++++++++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 3 + arch/arm/cpu/armv7/exynos/lowlevel_init.c | 147 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/exynos/sec_boot.S | 128 ++++++++++++++++++++++++++ arch/arm/cpu/armv7/exynos/soc.c | 35 ------- arch/arm/include/asm/arch-exynos/cpu.h | 5 + arch/arm/include/asm/arch-exynos/system.h | 88 ++++++++++++++++++ arch/arm/include/asm/armv7.h | 44 +++++++++ include/configs/exynos5420-common.h | 16 ++++ 10 files changed, 495 insertions(+), 35 deletions(-) create mode 100644 arch/arm/cpu/armv7/exynos/sec_boot.S -- 1.9.1

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[U-Boot] dfu_get_buf: Could not memalign 0x2000000 bytes
by Fabio Estevam 27 Feb '15

27 Feb '15

Hi, I am trying to run DFU in order to flash u-boot.imx into the SD card on a mx6qsabresd. The changes in config file are: --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -295,4 +295,10 @@ #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 #define CONFIG_G_DNL_MANUFACTURER "FSL" +#define CONFIG_CMD_DFU +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + #endif => mmc dev 1 => setenv dfu_alt_info 'boot raw 0x2 0x400' => save => dfu 0 mmc 1 Then on the host PC: $ sudo dfu-util -D u-boot.imx -a boot dfu-util 0.8 Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. Copyright 2010-2014 Tormod Volden and Stefan Schmidt This program is Free Software and has ABSOLUTELY NO WARRANTY Please report bugs to dfu-util(a)lists.gnumonks.org dfu-util: Invalid DFU suffix signature dfu-util: A valid DFU suffix will be required in a future dfu-util release!!! Opening DFU capable USB device... ID 0525:a4a5 Run-time device DFU version 0110 Claiming USB DFU Interface... Setting Alternate Setting #0 ... Determining device status: state = dfuIDLE, status = 0 dfuIDLE, continuing DFU mode device DFU version 0110 Device returned transfer size 4096 Copying data from PC to DFU device Download [ ] 0% 0 bytes failed! state(10) = dfuERROR, status(14) = Something went wrong, but the device does not know what it was and the following error is seen in U-boot: dfu_get_buf: Could not memalign 0x2000000 bytes Does anyone have any suggestions about this? Thanks, Fabio Estevam

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[U-Boot] [PATCH v1 1/2] fastboot: Add support to flash u-boot and MLO to QSPI
by Dileep Katta 27 Feb '15

27 Feb '15

This adds the functionality to flash u-boot and MLO images to QSPI using fastboot Signed-off-by: Dileep Katta <dileep.katta(a)linaro.org> --- Note: This is on top of Rob Herring patches submitted to support oem format command drivers/usb/gadget/f_fastboot.c | 75 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index f7d84bf..a170eea 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -492,10 +492,23 @@ static void cb_continue(struct usb_ep *ep, struct usb_request *req) } #ifdef CONFIG_FASTBOOT_FLASH +#ifdef CONFIG_SPL_SPI_SUPPORT +int boot_from_spi = 0; +#endif + static void cb_flash(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; char response[RESPONSE_LEN]; +#ifdef CONFIG_SPL_SPI_SUPPORT + char source[32]; + int status = 0; + char *sf_probe[3] = {"sf", "probe", "0"}; + char *sf_write_xloader[5] = {"sf", "write", NULL, "0", "20000"}; + char *sf_update_xloader[5] = {"sf", "update", NULL, "0", "20000"}; + char *sf_write_bl[5] = {"sf", "write", NULL, "80000", "80000"}; + char *sf_update_bl[5] = {"sf", "update", NULL, "80000", "80000"}; +#endif strsep(&cmd, ":"); if (!cmd) { @@ -505,6 +518,68 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req) } strcpy(response, "FAILno flash device defined"); +#ifdef CONFIG_SPL_SPI_SUPPORT + /* + * Check if this is for xloader or bootloader. + * Also, check if we have to flash to SPI + */ + if (strcmp(cmd, "xloader") == 0 && boot_from_spi) { + printf("Flashing %s to SPI\n", cmd); + status = do_spi_flash(NULL, 0, 3, sf_probe); + if (status) { + fastboot_tx_write_str("FAILcould not probe SPI"); + return; + } + sf_write_xloader[2] = source; + sf_update_xloader[2] = source; + sprintf(source, "0x%x", + (unsigned int)CONFIG_USB_FASTBOOT_BUF_ADDR); + + printf("Updating X-LOADER to SPI\n"); + status = do_spi_flash(NULL, 0, 5, sf_update_xloader); + if (status) { + fastboot_tx_write_str("FAILupdate xloader failed"); + return; + } + + printf("Writing X-LOADER to SPI\n"); + status = do_spi_flash(NULL, 0, 5, sf_write_xloader); + if (status) { + fastboot_tx_write_str("FAILwrite xloader failed"); + return; + } + printf("Writing xloader DONE\n"); + fastboot_tx_write_str("OKAY"); + return; + } + if (strcmp(cmd, "bootloader") == 0 && boot_from_spi) { + printf("Flashing %s to SPI\n", cmd); + status = do_spi_flash(NULL, 0, 3, sf_probe); + if (status) { + fastboot_tx_write_str("FAILcould not probe SPI"); + return; + } + sf_write_bl[2] = source; + sf_update_bl[2] = source; + sprintf(source, "0x%x", + (unsigned int)CONFIG_USB_FASTBOOT_BUF_ADDR); + printf("Updating bootloader to SPI\n"); + status = do_spi_flash(NULL, 0, 5, sf_update_bl); + if (status) { + fastboot_tx_write_str("FAILupdate bootloader failed"); + return; + } + printf("Writing bootloader to SPI\n"); + status = do_spi_flash(NULL, 0, 5, sf_write_bl); + if (status) { + fastboot_tx_write_str("FAILwrite bootloader failed"); + return; + } + printf("Writing bootloader DONE\n"); + fastboot_tx_write_str("OKAY"); + return; + } +#endif #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV fb_mmc_flash_write(cmd, (void *)CONFIG_USB_FASTBOOT_BUF_ADDR, download_bytes, response); -- 1.8.3.2

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Re: [U-Boot] U-Boot Digest, Vol 81, Issue 61
by Soeren Moch 27 Feb '15

27 Feb '15

> Date: Fri, 27 Feb 2015 10:04:23 +0100 > From: Stefano Babic<sbabic(a)denx.de> > To: Stefano Babic<sbabic(a)denx.de>, Fabio Estevam > <fabio.estevam(a)freescale.com> > Cc:u-boot@lists.denx.de,otavio@ossystems.com.br > Subject: Re: [U-Boot] [PATCH 1/2] warp: Add User Mass Storage support > Message-ID:<54F03317.3040709(a)denx.de> > Content-Type: text/plain; charset=windows-1252 > > On 27/02/2015 09:37, Stefano Babic wrote: >> >Hi Fabio, >> > >> >On 25/02/2015 13:55, Fabio Estevam wrote: >>> >>With UMS support we are able to flash the eMMC from U-boot, which is very >>> >>convenient. >>> >> >>> >>Add UMS support to make the eMMC flashing process easier. >>> >> >> > >> >Maybe you want to say USB and not UMS, is it ? > ok, after a coffe I get now this is User Mass Storage. I should remember > to take always a coffe before reading patches... > I would say: USB Mass Storage, as the command config option and the USB class is named. Only the help text for the u-boot ums command says "User Mass Storage", I have no idea where this comes from. Regards, Soeren

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[U-Boot] [PATCH 1/2] warp: Add User Mass Storage support
by Fabio Estevam 27 Feb '15

27 Feb '15

With UMS support we are able to flash the eMMC from U-boot, which is very convenient. Add UMS support to make the eMMC flashing process easier. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/warp/warp.c | 6 ++++++ include/configs/warp.h | 26 ++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/board/warp/warp.c b/board/warp/warp.c index 3b275c2..21ac5e7 100644 --- a/board/warp/warp.c +++ b/board/warp/warp.c @@ -21,6 +21,7 @@ #include <watchdog.h> #include <fsl_esdhc.h> #include <mmc.h> +#include <usb.h> DECLARE_GLOBAL_DATA_PTR; @@ -82,6 +83,11 @@ int board_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } +int board_usb_phy_mode(int port) +{ + return USB_INIT_DEVICE; +} + int board_early_init_f(void) { setup_iomux_uart(); diff --git a/include/configs/warp.h b/include/configs/warp.h index 82036e4..cfc2323 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -120,6 +120,32 @@ #define CONFIG_CMD_CACHE #endif +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG2 port enabled */ +#endif + +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "FSL" + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ -- 1.9.1

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[U-Boot] [PATCH 1/2][v4] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
by Aneesh Bansal 27 Feb '15

27 Feb '15

Secure Boot Target is added for NAND for P3041. Changes: In PowerPC, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on this SRAM at location 0xBFF40000 with entry point as 0xBFFFFFFC. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v4: - Created a patch set. Makefile | 4 ++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++++++++++++++++ board/freescale/common/p_corenet/tlb.c | 18 +++++++++++++++++- board/freescale/corenet_ds/MAINTAINERS | 5 +++++ configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4 ++++ include/configs/corenet_ds.h | 9 +++++++++ 6 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/Makefile b/Makefile index bd4abab..acfaa23 100644 --- a/Makefile +++ b/Makefile @@ -719,8 +719,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin else +ifneq ($(CONFIG_SECURE_BOOT), y) +# For Secure Boot The Image needs to be signed and Header must also +# be included. So The image has to be built explicitly ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl endif +endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4cf8853..ef56cc0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -843,6 +843,23 @@ int cpu_init_r(void) setup_mp(); #endif +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + defined(CONFIG_SECURE_BOOT) + /* Disable the TLB Created for L3 and create the TLB required for + * PCIE (CONFIG_SYS_PCIE1_MEM_VIRT) which was not created earlier. + */ + int tlb_index; + tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); + if (tlb_index != -1) { + disable_tlb(tlb_index); + + set_tlb(1, CONFIG_SYS_PCIE1_MEM_VIRT, + CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, tlb_index, BOOKE_PAGESZ_1G, 1); + } +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 { if (SVR_MAJ(svr) < 3) { diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 8148e46..1b60cfb 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -42,7 +42,9 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* In Case of Secure RAM Boot L3 address is defined at 0xbff00000 */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. @@ -76,11 +78,25 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + defined(CONFIG_SECURE_BOOT) + /* In case of Secure Boot, L3 is used as 1M SRAM + * and the address of the SRAM is at 0xbff00000. + * The PCIE TLB entry conflicts with the above entry. + * So, the entry for PCIE is not created at this point of time. + * It will be created later on in cpu_init_r() + * when U-Boot has relocated to DDR + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1M, 1), +#else /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), +#endif /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 745847c..6855446 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -28,3 +28,8 @@ F: configs/P5040DS_NAND_defconfig F: configs/P5040DS_SDCARD_defconfig F: configs/P5040DS_SPIFLASH_defconfig F: configs/P5040DS_SECURE_BOOT_defconfig + +CORENET_DS_SECURE_BOOT BOARD +M: Aneesh Bansal <aneesh.bansal(a)freescale.com> +S: Maintained +F: configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000..e810b1c --- /dev/null +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 225ffdd..64c6890 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -16,6 +16,14 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xbffffffc +#define CONFIG_BPTR_VIRT_ADDR 0xbffff000 +#ifdef CONFIG_NAND +#define CONFIG_RAMBOOT_NAND +#endif +#else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg @@ -29,6 +37,7 @@ #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif +#endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -- 1.8.1.4

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[U-Boot] BDI3000 U-Boot debugging questions (MX51/MX53)
by DaveKucharczyk 26 Feb '15

26 Feb '15

I would like to debug from the earliest possible point pre-relocation (for educational reasons). Couple questions.... In the Makefile, where do I place the following flags... -Os #-fomit-frame-pointer -g -fno-schedule-insns -fno-schedule-insns2 I've added the flags in a few different spots, but I still can't break on cpu_init_f. Here's the output... (gdb) b cpu_init_f Function "cpu_init_f" not defined. Make breakpoint pending on future shared library load? (y or [n]) y I assume the flags didn't get set, specifically -g. To backup a little here is what I get when I do target remote... (gdb) target remote 169.254.21.13:2001 Remote debugging using 169.254.21.13:2001 warning: Unable to find dynamic linker breakpoint function. GDB will be unable to debug shared library initializers and track explicitly loaded dynamic code. 0x00000000 in ?? () (gdb) I assume those warning are related to my issue above? Also, when I power on the target, u-boot just starts loading. How do I halt it? I tried to set a breakpoint at text base in the BDI, but it doesn't halt. -- View this message in context: http://u-boot.10912.n7.nabble.com/BDI3000-U-Boot-debugging-questions-MX51-M… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH v2 1/2] mx6sabre: Enable User Mass Storage
by Fabio Estevam 26 Feb '15

26 Feb '15

User Mass Storage is very useful for flashing the on-board eMMC. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - Remove EXT2/EXT4 and BOUNCE_BUFFER support include/configs/mx6sabre_common.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index f0f721e..337b865 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -279,4 +279,18 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "FSL" + #endif /* __MX6QSABRE_COMMON_CONFIG_H */ -- 1.9.1

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[U-Boot] [PATCH] powerpc/T104xD4RDB: Add T1040/T1042D4RDB boards support
by Vijay Rai 26 Feb '15

26 Feb '15

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. It is similar to T1040RDB board with the following differences : - Has DDR4 memory - PHY ports have different PHY addresses - RTC support - Both QE-TDM and DIU connector T1040D4RDB supports 0x66 serdes protocol with following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 T1042D4RDB is variant of T1040D4RDB which hosts T1042 SoC (Personality of T1040 without L2 switch) T1042D4RDB supports 0x86 serdes protocol with following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 Signed-off-by: Vijay Rai <vijay.rai(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- board/freescale/t104xrdb/MAINTAINERS | 8 ++++++ board/freescale/t104xrdb/ddr.c | 7 +++++ board/freescale/t104xrdb/ddr.h | 12 ++++++++ board/freescale/t104xrdb/eth.c | 20 +++++++++++-- board/freescale/t104xrdb/t1040d4_rcw.cfg | 7 +++++ board/freescale/t104xrdb/t1042d4_rcw.cfg | 7 +++++ configs/T1040D4RDB_NAND_defconfig | 5 ++++ configs/T1040D4RDB_SDCARD_defconfig | 5 ++++ configs/T1040D4RDB_SPIFLASH_defconfig | 5 ++++ configs/T1040D4RDB_defconfig | 4 +++ configs/T1042D4RDB_NAND_defconfig | 5 ++++ configs/T1042D4RDB_SDCARD_defconfig | 5 ++++ configs/T1042D4RDB_SPIFLASH_defconfig | 5 ++++ configs/T1042D4RDB_defconfig | 4 +++ include/configs/T104xRDB.h | 46 ++++++++++++++++++++++++------ 15 files changed, 134 insertions(+), 11 deletions(-) create mode 100644 board/freescale/t104xrdb/t1040d4_rcw.cfg create mode 100644 board/freescale/t104xrdb/t1042d4_rcw.cfg create mode 100644 configs/T1040D4RDB_NAND_defconfig create mode 100644 configs/T1040D4RDB_SDCARD_defconfig create mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig create mode 100644 configs/T1040D4RDB_defconfig create mode 100644 configs/T1042D4RDB_NAND_defconfig create mode 100644 configs/T1042D4RDB_SDCARD_defconfig create mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig create mode 100644 configs/T1042D4RDB_defconfig diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index 13d9be9..32e044f 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -6,7 +6,13 @@ F: include/configs/T104xRDB.h F: configs/T1040RDB_defconfig F: configs/T1040RDB_NAND_defconfig F: configs/T1040RDB_SPIFLASH_defconfig +F: configs/T1040D4RDB_defconfig +F: configs/T1040D4RDB_NAND_defconfig +F: configs/T1040D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_defconfig +F: configs/T1042D4RDB_defconfig +F: configs/T1042D4RDB_NAND_defconfig +F: configs/T1042D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_PI_defconfig F: configs/T1042RDB_PI_NAND_defconfig F: configs/T1042RDB_PI_SPIFLASH_defconfig @@ -15,6 +21,8 @@ T1040RDB_SDCARD BOARD #M: - S: Maintained F: configs/T1040RDB_SDCARD_defconfig +F: configs/T1040D4RDB_SDCARD_defconfig +F: configs/T1042D4RDB_SDCARD_defconfig F: configs/T1042RDB_PI_SDCARD_defconfig T1040RDB_SECURE_BOOT BOARD diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index e1148e5..217c8ea 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -91,9 +91,16 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } +#endif #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void) diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index ab1c32d..5d7124a 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -28,6 +28,13 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09}, + {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A}, + {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C}, +#elif defined(CONFIG_SYS_FSL_DDR3) {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, @@ -40,9 +47,14 @@ static const struct board_specific_parameters udimm0[] = { {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, +#else +#error DDR type not defined +#endif {} }; +#endif + static const struct board_specific_parameters *udimms[] = { udimm0, }; diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 7581a4cd..9c4e922 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis) int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_T1040RDB +#if defined(CONFIG_T1040RDB) || (CONFIG_T1040D4RDB) case PHY_INTERFACE_MODE_SGMII: - /* T1040RDB only supports SGMII on DTSEC3 */ + /* T1040RDB & T1040D4RDB only supports SGMII on + * DTSEC3 + */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); break; @@ -60,6 +62,20 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif +#ifdef CONFIG_T1042D4RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 + * & DTSEC3 + */ + if (FM1_DTSEC1 == i) + phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; + if (FM1_DTSEC2 == i) + phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; + if (FM1_DTSEC3 == i) + phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; +#endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; diff --git a/board/freescale/t104xrdb/t1040d4_rcw.cfg b/board/freescale/t104xrdb/t1040d4_rcw.cfg new file mode 100644 index 0000000..3300c18 --- /dev/null +++ b/board/freescale/t104xrdb/t1040d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 80000002 e8106000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042d4_rcw.cfg b/board/freescale/t104xrdb/t1042d4_rcw.cfg new file mode 100644 index 0000000..db4d52f --- /dev/null +++ b/board/freescale/t104xrdb/t1042d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 80000002 ec027000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig new file mode 100644 index 0000000..72b046b --- /dev/null +++ b/configs/T1040D4RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig new file mode 100644 index 0000000..9e63214 --- /dev/null +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..e0ab015 --- /dev/null +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig new file mode 100644 index 0000000..d650ab6 --- /dev/null +++ b/configs/T1040D4RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig new file mode 100644 index 0000000..5e33654 --- /dev/null +++ b/configs/T1042D4RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig new file mode 100644 index 0000000..7851a8b --- /dev/null +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..536ea79 --- /dev/null +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig new file mode 100644 index 0000000..715697f --- /dev/null +++ b/configs/T1042D4RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5263318..111bbfb 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -29,6 +29,14 @@ #ifdef CONFIG_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg #endif +#ifdef CONFIG_T1040D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg +#endif +#ifdef CONFIG_T1042D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -219,8 +227,14 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#ifdef CONFIG_T104XD4RDB +#define CONFIG_SYS_FSL_DDR4 +#endif + #define CONFIG_DDR_SPD +#ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 +#endif #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -278,7 +292,7 @@ #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) #define CPLD_DIU_SEL_DFP 0x80 #endif @@ -448,7 +462,7 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) /* Video */ #define CONFIG_FSL_DIU_FB @@ -493,11 +507,11 @@ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define I2C_MUX_CH_DEFAULT 0x8 #endif -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 @@ -666,7 +680,7 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define CONFIG_QE #define CONFIG_U_QE #endif @@ -695,7 +709,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_QE_FW_ADDR 0x130000 #elif defined(CONFIG_SDCARD) @@ -720,10 +734,20 @@ #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 +#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#endif + +#ifdef CONFIG_T104XD4RDB +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#else +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #endif -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #ifdef CONFIG_T1040RDB @@ -842,6 +866,10 @@ #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" #elif defined(CONFIG_T1042RDB) #define FDTFILE "t1042rdb/t1042rdb.dtb" +#elif defined(CONFIG_T1040D4RDB) +#define FDTFILE "t1042rdb/t1040d4rdb.dtb" +#elif defined(CONFIG_T1042D4RDB) +#define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif #ifdef CONFIG_FSL_DIU_FB -- 1.7.9.5

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[U-Boot] [PATCH 1/3] usb: ci_udc: Fix set address to work with older controllers
by Alban Bedel 26 Feb '15

26 Feb '15

Older controllers don't implement "Device Address Advance" which allow to pass the device address to the controller when it is received. To support such controller we need to store the requested address and only apply it after the next IN transfer completed on EP0. Signed-off-by: Alban Bedel <alban.bedel(a)avionic-design.de> --- drivers/usb/gadget/ci_udc.c | 18 +++++++++++++----- drivers/usb/gadget/ci_udc.h | 1 + 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index b0ef35e..694745f 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -523,6 +523,13 @@ static void handle_ep_complete(struct ci_ep *ci_ep) DBG("ept%d %s req %p, complete %x\n", num, in ? "in" : "out", ci_req, len); + /* The device address must be applied after the next IN transfer + * completed on ep0. */ + if (num == 0 && in && controller.set_address) { + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + writel(controller.set_address << 25, &udc->devaddr); + controller.set_address = 0; + } if (num != 0 || controller.ep0_data_phase) ci_req->req.complete(&ci_ep->ep, &ci_req->req); if (num == 0 && controller.ep0_data_phase) { @@ -614,11 +621,9 @@ static void handle_setup(void) return; case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS): - /* - * write address delayed (will take effect - * after the next IN txn) - */ - writel((r.wValue << 25) | (1 << 24), &udc->devaddr); + /* The device address must be updated after the next IN + * request completed */ + controller.set_address = r.wValue; req->length = 0; usb_ep_queue(controller.gadget.ep0, req, 0); return; @@ -670,6 +675,9 @@ static void stop_activity(void) ci_flush_qh(num); } } + + /* clear any pending set address */ + controller.set_address = 0; } void udc_irq(void) diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index 346164a..44e70b1 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -99,6 +99,7 @@ struct ci_drv { struct usb_gadget gadget; struct ci_req *ep0_req; bool ep0_data_phase; + uint8_t set_address; struct usb_gadget_driver *driver; struct ehci_ctrl *ctrl; struct ept_queue_head *epts; -- 2.3.0

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