February 2015 - U-Boot

[U-Boot] [PATCH v2] omap3: add support for QUIPOS Cairo board.
by Albert ARIBAUD (3ADEV) 06 Mar '15

06 Mar '15

This patch extends OMAP3 support for AM/DM37xx and introduces the AM3703-based Quipos Cairo board. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud(a)3adev.fr> --- NOTES: Two checkpatch diagnostics are left uncorrected: 1. "warning: arch/arm/cpu/armv7/omap3/Kconfig,94: please write a paragraph that describes the config symbol fully" No other symbol of the same nature has such a paragraph, so I left it out. 2. "check: board/quipos/cairo/cairo.c,87: Avoid CamelCase: <SDP_3430_SDRC_RFR_CTRL_165MHz>" Symbol was not defined in this patch. If requested, I will post a separate change to fix the symbol. Changes in v2: - removed v1 patches 1..5 applied to mainline - corrected serial device name from ttyS1 to ttyO1 - rewrote config file based on omap3_beagle's - moved serial support to DM - fixed environment arch/arm/cpu/armv7/omap3/Kconfig | 5 + board/quipos/cairo/Kconfig | 12 ++ board/quipos/cairo/Makefile | 8 + board/quipos/cairo/cairo.c | 110 ++++++++++++++ board/quipos/cairo/cairo.h | 319 +++++++++++++++++++++++++++++++++++++++ configs/cairo_defconfig | 4 + include/configs/omap3_cairo.h | 286 +++++++++++++++++++++++++++++++++++ 7 files changed, 744 insertions(+) create mode 100644 board/quipos/cairo/Kconfig create mode 100644 board/quipos/cairo/Makefile create mode 100644 board/quipos/cairo/cairo.c create mode 100644 board/quipos/cairo/cairo.h create mode 100644 configs/cairo_defconfig create mode 100644 include/configs/omap3_cairo.h diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index a029379..88a9544 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -91,6 +91,10 @@ config TARGET_TWISTER bool "Twister" select SUPPORT_SPL +config TARGET_OMAP3_CAIRO + bool "QUIPOS CAIRO" + select SUPPORT_SPL + endchoice config SYS_SOC @@ -118,5 +122,6 @@ source "board/matrix_vision/mvblx/Kconfig" source "board/nokia/rx51/Kconfig" source "board/technexion/tao3530/Kconfig" source "board/technexion/twister/Kconfig" +source "board/quipos/cairo/Kconfig" endif diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig new file mode 100644 index 0000000..8df9421 --- /dev/null +++ b/board/quipos/cairo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_CAIRO + +config SYS_BOARD + default "cairo" + +config SYS_VENDOR + default "quipos" + +config SYS_CONFIG_NAME + default "omap3_cairo" + +endif diff --git a/board/quipos/cairo/Makefile b/board/quipos/cairo/Makefile new file mode 100644 index 0000000..445088f --- /dev/null +++ b/board/quipos/cairo/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 DENX Software Engineering +# Written-By: Albert ARIBAUD <albert.aribaud(a)3adev.fr> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cairo.o diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c new file mode 100644 index 0000000..b97a09a --- /dev/null +++ b/board/quipos/cairo/cairo.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2014 DENX + * Written-by: Albert ARIBAUD <albert.aribaud(a)3adev.fr> + * + * Derived from code written by Robert Aigner (ra(a)spiid.net) + * + * Itself derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <netdev.h> +#include <ns16550.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <asm/mach-types.h> +#include <asm/omap_mmc.h> +#include "cairo.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. + */ +u8 omap3_evm_need_extvbus(void) +{ + u8 retval = 0; + + /* TODO: verify if cairo handheld platform needs extvbus programming */ + + return retval; +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_CAIRO(); +} + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} +#endif + +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + * + * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6 + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->sharing = SAMSUNG_SHARING; + timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20); + timings->ctrla = SAMSUNG_V_ACTIMA_165; + timings->ctrlb = SAMSUNG_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mr = SAMSUNG_V_MR_165; +} +#endif + +static const struct ns16550_platdata cairo_serial = { + OMAP34XX_UART2, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(cairo_uart) = { + "serial_omap", + &cairo_serial +}; + +/* force SPL booting into U-Boot, not Linux */ +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 1; +} +#endif diff --git a/board/quipos/cairo/cairo.h b/board/quipos/cairo/cairo.h new file mode 100644 index 0000000..50734d0 --- /dev/null +++ b/board/quipos/cairo/cairo.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) DENX + * Written-by: Albert ARIBAUD <albert.aribaud(a)3adev.fr> + * + * Original code (C) Copyright 2010 + * Robert Aigner (ra(a)spiid.net) + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _EVM_H_ +#define _EVM_H_ + + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "OMAP3 Cairo board", + "NAND", +}; + +/* + * OMAP3 Cairo handheld hardware revision + */ +enum { + OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */ + OMAP3_CAIRO_BOARD_GEN_2, +}; + +#define MUX_CAIRO() \ +MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \ +MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \ +MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \ +MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \ + (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \ +MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \ + +#endif diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig new file mode 100644 index 0000000..ae1dda2 --- /dev/null +++ b/configs/cairo_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_OMAP3_CAIRO=y diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h new file mode 100644 index 0000000..3030054 --- /dev/null +++ b/include/configs/omap3_cairo.h @@ -0,0 +1,286 @@ +/* + * Configuration settings for the QUIPOS Cairo board. + * + * Copyright (C) DENX GmbH + * + * Author : + * Albert ARIBAUD <albert.aribaud(a)3adev.fr> + * + * Derived from EVM code by + * Manikandan Pillai <mani.pillai(a)ti.com> + * Itself derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * Also derived from include/configs/omap3_beagle.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP3_CAIRO_CONFIG_H +#define __OMAP3_CAIRO_CONFIG_H + +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. We use this rather than the inherited defines from + * ti_armv7_common.h for backwards compatibility. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +#define CONFIG_NAND + +#include <configs/ti_omap3_common.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CONFIG_MISC_INIT_R + +#define CONFIG_REVISION_TAG 1 +#define CONFIG_ENV_OVERWRITE + +/* Enable Multi Bus support for I2C */ +#define CONFIG_I2C_MULTI_BUS 1 + +/* Probe all devices */ +#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} } + +#define CONFIG_NAND + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_SETEXPR /* Evaluate expressions */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK + +/* Disable some commands */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_LED 1 + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST 1 +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +/* override default CONFIG_BOOTDELAY */ +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "machid=ffffffff\0" \ + "fdt_high=0x87000000\0" \ + "baudrate=115200\0" \ + "ethaddr=00:50:C2:7E:90:F0\0" \ + "fec_addr=00:50:C2:7E:90:F0\0" \ + "netmask=255.255.255.0\0" \ + "ipaddr=192.168.2.9\0" \ + "gateway=192.168.2.1\0" \ + "serverip=192.168.2.10\0" \ + "nfshost=192.168.2.10\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootargs_mmc_ramdisk=mem=128M " \ + "console=ttyO1,115200n8 " \ + "root=/dev/ram0 rw " \ + "initrd=0x81600000,16M " \ + "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \ + "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \ + "mmcboot=mmc init; " \ + "fatload mmc 0 0x80000000 uImage; " \ + "fatload mmc 0 0x81600000 ramdisk.gz; " \ + "setenv bootargs ${bootargs_mmc_ramdisk}; " \ + "bootm 0x80000000\0" \ + "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \ + "root=/dev/nfs " \ + "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \ + "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \ + "omap_vout.vid1_static_vrfb_alloc=y\0" \ + "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \ + "bootm 0x80000000\0" \ + "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \ + "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \ + "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \ + "omapfb.rotate_type=1\0" \ + "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \ + "bootargs ${bootargs_nand}; bootm 0x80000000\0" \ + "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ + "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \ + "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \ + "mw 60 09 00 1; i2c mw 60 06 10 1\0" \ + "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ + "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \ + "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ + "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ + "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \ + "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \ + "nand erase 0 20000; " \ + "fatload mmc 0 0x81600000 MLO; " \ + "nandecc hw; " \ + "nand write.i 0x81600000 0 20000;\0" \ + "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \ + "nand erase 80000 40000; " \ + "fatload mmc 0 0x81600000 u-boot.bin; " \ + "nandecc sw; " \ + "nand write.i 0x81600000 80000 40000;\0" \ + "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \ + "nand erase 280000 300000; " \ + "fatload mmc 0 0x81600000 uImage; " \ + "nandecc sw; " \ + "nand write.i 0x81600000 280000 300000;\0" \ + "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \ + "nandecc sw; " \ + "nand write.jffs2 0x680000 0xFF ${filesize}; " \ + "nand erase 680000 ${filesize}; " \ + "nand write.jffs2 81600000 680000 ${filesize};\0" \ + "flash_scrub=nand scrub; " \ + "run flash_xloader; " \ + "run flash_uboot; " \ + "run flash_kernel; " \ + "run flash_rootfs;\0" \ + "flash_all=run ledred; " \ + "nand erase.chip; " \ + "run ledorange; " \ + "run flash_xloader; " \ + "run flash_uboot; " \ + "run flash_kernel; " \ + "run flash_rootfs; " \ + "run ledgreen; " \ + "run boot_nand; \0" \ + +#define CONFIG_BOOTCOMMAND \ + "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \ + "else run boot_nand; fi" + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE +#endif + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +#define CONFIG_OMAP3_SPI + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Defines for SPL */ +#define CONFIG_SPL_OMAP3_ID_NAND + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif + +/* env defaults */ +#define CONFIG_BOOTFILE "uImage" + +/* Override OMAP3 common serial console configuration from UART3 + * to UART2. + * + * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) + * are needed and peripheral clocks for UART2 must be enabled in + * function per_clocks_enable(). + */ +#undef CONFIG_CONS_INDEX +#define CONFIG_CONS_INDEX 2 +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SYS_NS16550_COM3 +#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 +#undef CONFIG_SERIAL3 +#define CONFIG_SERIAL2 +#endif + +/* Keep old prompt in case some existing script depends on it */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "Cairo # " + +/* Provide MACH_TYPE for compatibility with non-DT kernels */ +#define MACH_TYPE_OMAP3_CAIRO 3063 +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ + /* on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#endif /* __OMAP3_CAIRO_CONFIG_H */ -- 2.1.0

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[U-Boot] [PATCH] cmd_yaffs: Clean up command usage messages
by Peter Tyser 06 Mar '15

06 Mar '15

Remove duplicate command names in usage messages to fix issues such as: => help yls yls - yaffs ls Usage: yls yls [-l] dirname Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- common/cmd_yaffs2.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/common/cmd_yaffs2.c b/common/cmd_yaffs2.c index d43a9d4..9244606 100644 --- a/common/cmd_yaffs2.c +++ b/common/cmd_yaffs2.c @@ -281,46 +281,46 @@ int do_ymv(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) U_BOOT_CMD(ytrace, 2, 0, do_ytrace, "show/set yaffs trace mask", - "ytrace [new_mask] show/set yaffs trace mask"); + "[new_mask] show/set yaffs trace mask"); U_BOOT_CMD(ydevls, 1, 0, do_ydevls, "list yaffs mount points", "list yaffs mount points"); U_BOOT_CMD(ydevconfig, 5, 0, do_ydevconfig, "configure yaffs mount point", - "ydevconfig mtpoint mtd_id start_block end_block configures a yaffs2 mount point"); + "mtpoint mtd_id start_block end_block configures a yaffs2 mount point"); U_BOOT_CMD(ymount, 2, 0, do_ymount, - "mount yaffs", "ymount mtpoint mounts a yaffs2 mount point"); + "mount yaffs", "mtpoint mounts a yaffs2 mount point"); U_BOOT_CMD(yumount, 2, 0, do_yumount, - "unmount yaffs", "yunmount mtpoint unmounts a yaffs2 mount point"); + "unmount yaffs", "mtpoint unmounts a yaffs2 mount point"); -U_BOOT_CMD(yls, 3, 0, do_yls, "yaffs ls", "yls [-l] dirname"); +U_BOOT_CMD(yls, 3, 0, do_yls, "yaffs ls", "[-l] dirname"); U_BOOT_CMD(yrd, 2, 0, do_yrd, - "read file from yaffs", "yrd path read file from yaffs"); + "read file from yaffs", "path read file from yaffs"); U_BOOT_CMD(ywr, 4, 0, do_ywr, "write file to yaffs", - "ywr filename value num_vlues write values to yaffs file"); + "filename value num_vlues write values to yaffs file"); U_BOOT_CMD(yrdm, 3, 0, do_yrdm, "read file to memory from yaffs", - "yrdm filename offset reads yaffs file into memory"); + "filename offset reads yaffs file into memory"); U_BOOT_CMD(ywrm, 4, 0, do_ywrm, "write file from memory to yaffs", - "ywrm filename offset size writes memory to yaffs file"); + "filename offset size writes memory to yaffs file"); U_BOOT_CMD(ymkdir, 2, 0, do_ymkdir, - "YAFFS mkdir", "ymkdir dir create a yaffs directory"); + "YAFFS mkdir", "dir create a yaffs directory"); U_BOOT_CMD(yrmdir, 2, 0, do_yrmdir, - "YAFFS rmdir", "yrmdir dirname removes a yaffs directory"); + "YAFFS rmdir", "dirname removes a yaffs directory"); -U_BOOT_CMD(yrm, 2, 0, do_yrm, "YAFFS rm", "yrm path removes a yaffs file"); +U_BOOT_CMD(yrm, 2, 0, do_yrm, "YAFFS rm", "path removes a yaffs file"); U_BOOT_CMD(ymv, 4, 0, do_ymv, "YAFFS mv", - "ymv old_path new_path moves/rename files within a yaffs mount point"); + "old_path new_path moves/rename files within a yaffs mount point"); -- 1.9.1

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[U-Boot] [PATCH] arm: spear: Move to generic board support
by Stefan Roese 06 Mar '15

06 Mar '15

Without this change the board support for these SPEAr boards would be dropped soon. Generic board support seems to work just fine. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Viresh Kumar <viresh.kumar(a)linaro.org> Cc: Vipin Kumar <vk.vipin(a)gmail.com> --- Unfortunately I missed the merge window by one day. I totally forget to check here. But I'm currently busy with updating U-Boot on at least the x600 board. Including updated SPL support (which is quite outdated). So I really would like to not have these SPEAr board dropped from mainline for now. Thanks, Stefan include/configs/spear-common.h | 2 ++ include/configs/x600.h | 1 + 2 files changed, 3 insertions(+) diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index a11f4ed..16281f5 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -11,6 +11,8 @@ * Common configurations used for both spear3xx as well as spear6xx */ +#define CONFIG_SYS_GENERIC_BOARD + /* U-boot Load Address */ #define CONFIG_SYS_TEXT_BASE 0x00700000 diff --git a/include/configs/x600.h b/include/configs/x600.h index 04187c0..241bf65 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -16,6 +16,7 @@ */ #define CONFIG_SPEAR600 /* SPEAr600 SoC */ #define CONFIG_X600 /* on X600 board */ +#define CONFIG_SYS_GENERIC_BOARD #include <asm/arch/hardware.h> -- 2.2.2

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[U-Boot] [PATCH] common: Move dram_init() declaration to common location
by Michal Simek 06 Mar '15

06 Mar '15

Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Build tested for Microblaze and x86. Created based on my discussion with Simon. --- arch/arm/include/asm/u-boot-arm.h | 1 - arch/nds32/include/asm/u-boot-nds32.h | 1 - arch/sandbox/include/asm/u-boot-sandbox.h | 1 - arch/x86/include/asm/u-boot-x86.h | 6 ------ include/common.h | 1 + 5 files changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index f97f3dd1496a..414042d4039b 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -36,7 +36,6 @@ int arch_early_init_r(void); /* board/.../... */ int board_init(void); -int dram_init (void); void dram_init_banksize (void); /* cpu/.../interrupt.c */ diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h index b07908692a92..dee5f43ae155 100644 --- a/arch/nds32/include/asm/u-boot-nds32.h +++ b/arch/nds32/include/asm/u-boot-nds32.h @@ -22,7 +22,6 @@ int cleanup_before_linux(void); /* board/.../... */ int board_init(void); -int dram_init(void); /* cpu/.../interrupt.c */ void reset_timer_masked(void); diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h index d2f1b6566d70..770ab5c9cc07 100644 --- a/arch/sandbox/include/asm/u-boot-sandbox.h +++ b/arch/sandbox/include/asm/u-boot-sandbox.h @@ -17,7 +17,6 @@ /* board/.../... */ int board_init(void); -int dram_init(void); /* start.c */ int sandbox_early_getopt_check(void); diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index b98afa801d3a..c24846b3ed50 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -26,15 +26,9 @@ unsigned long get_tbclk_mhz(void); void timer_set_base(uint64_t base); int pcat_timer_init(void); -/* Architecture specific DRAM init */ -int dram_init(void); - /* cpu/.../interrupts.c */ int cpu_init_interrupts(void); -/* board/.../... */ -int dram_init(void); - int cleanup_before_linux(void); int x86_cleanup_before_linux(void); void x86_enable_caches(void); diff --git a/include/common.h b/include/common.h index 4b3e0d3bbd75..81edc7d2788c 100644 --- a/include/common.h +++ b/include/common.h @@ -183,6 +183,7 @@ typedef void (interrupt_handler_t)(void *); /* * Function Prototypes */ +int dram_init(void); void hang (void) __attribute__ ((noreturn)); -- 1.8.2.3

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[U-Boot] [PATCH] net: Support DMA threshold mode in DWMAC driver
by Sonic Zhang 06 Mar '15

06 Mar '15

From: Sonic Zhang <sonic.zhang(a)analog.com> - DMA threshold mode can be selected in board config head file. Signed-off-by: Sonic Zhang <sonic.zhang(a)analog.com> --- drivers/net/designware.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 51eff85..bc3c88f 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -251,8 +251,13 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); +#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, &dma_p->opmode); +#else + writel(readl(&dma_p->opmode) | FLUSHTXFIFO, + &dma_p->opmode); +#endif writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); -- 1.7.9.5

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[U-Boot] [PATCH v3] net: configure DWMAC DMA by default AXI burst length
by Sonic Zhang 06 Mar '15

06 Mar '15

From: Sonic Zhang <sonic.zhang(a)analog.com> Board can define its own AXI burst length to improve DWMAC DMA performance. v2-changes: - Avoid write burst len register when the Macro is not defined. v3-changes: - Add axi_bus register member to struct eth_dma_regs. Signed-off-by: Sonic Zhang <sonic.zhang(a)analog.com> --- drivers/net/designware.c | 4 ++++ drivers/net/designware.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9ded895..51eff85 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -256,6 +256,10 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); +#ifdef CONFIG_DW_AXI_BURST_LEN + writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); +#endif + /* Start up the PHY */ if (phy_startup(priv->phydev)) { printf("Could not initialize PHY %s\n", diff --git a/drivers/net/designware.h b/drivers/net/designware.h index ce51102..49d900c 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -68,7 +68,9 @@ struct eth_dma_regs { u32 status; /* 0x14 */ u32 opmode; /* 0x18 */ u32 intenable; /* 0x1c */ - u8 reserved[40]; + u32 reserved1[2]; + u32 axibus; /* 0x28 */ + u32 reserved2[7]; u32 currhosttxdesc; /* 0x48 */ u32 currhostrxdesc; /* 0x4c */ u32 currhosttxbuffaddr; /* 0x50 */ -- 1.7.9.5

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[U-Boot] checkstack.pl
by York Sun 06 Mar '15

06 Mar '15

Masahiro, Do you mind to add aarch64 support for checkstack.pl? $ make checkstack /opt/linaro/gcc-linaro-aarch64-linux-gnu-4.8-2013.12_linux/bin/aarch64-linux-gnu-objdump -d u-boot $(find . -name u-boot-spl) | \ perl ./scripts/checkstack.pl aarch64 wrong or unknown architecture "aarch64" York

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[U-Boot] [PATCH] gpt: support random UUIDs without setting environment variables
by Rob Herring 06 Mar '15

06 Mar '15

Currently, an environment variable must be used to store the randomly generated UUID for each partition. This is not necessary, so make storing the UUID optional. Now passing uuid_disk and uuid are optional when random UUIDs are enabled. Signed-off-by: Rob Herring <robh(a)kernel.org> --- common/cmd_gpt.c | 48 ++++++++++++++++++++++++++++++------------------ doc/README.gpt | 8 +++++--- 2 files changed, 35 insertions(+), 21 deletions(-) diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c index 75df3fe..c56fe15 100644 --- a/common/cmd_gpt.c +++ b/common/cmd_gpt.c @@ -154,17 +154,24 @@ static int set_gpt_info(block_dev_desc_t *dev_desc, /* extract disk guid */ s = str; - tok = strsep(&s, ";"); - val = extract_val(tok, "uuid_disk"); + val = extract_val(str, "uuid_disk"); if (!val) { +#ifdef CONFIG_RANDOM_UUID + *str_disk_guid = malloc(UUID_STR_LEN + 1); + gen_rand_uuid_str(*str_disk_guid, UUID_STR_FORMAT_STD); +#else free(str); return -2; +#endif + } else { + val = strsep(&val, ";"); + if (extract_env(val, &p)) + p = val; + *str_disk_guid = strdup(p); + free(val); + /* Move s to first partition */ + strsep(&s, ";"); } - if (extract_env(val, &p)) - p = val; - *str_disk_guid = strdup(p); - free(val); - if (strlen(s) == 0) return -3; @@ -192,20 +199,25 @@ static int set_gpt_info(block_dev_desc_t *dev_desc, /* uuid */ val = extract_val(tok, "uuid"); - if (!val) { /* 'uuid' is mandatory */ - errno = -4; - goto err; - } - if (extract_env(val, &p)) - p = val; - if (strlen(p) >= sizeof(parts[i].uuid)) { - printf("Wrong uuid format for partition %d\n", i); + if (!val) { + /* 'uuid' is optional if random uuid's are enabled */ +#ifdef CONFIG_RANDOM_UUID + gen_rand_uuid_str(parts[i].uuid, UUID_STR_FORMAT_STD); +#else errno = -4; goto err; +#endif + } else { + if (extract_env(val, &p)) + p = val; + if (strlen(p) >= sizeof(parts[i].uuid)) { + printf("Wrong uuid format for partition %d\n", i); + errno = -4; + goto err; + } + strcpy((char *)parts[i].uuid, p); + free(val); } - strcpy((char *)parts[i].uuid, p); - free(val); - /* name */ val = extract_val(tok, "name"); if (!val) { /* name is mandatory */ diff --git a/doc/README.gpt b/doc/README.gpt index ec0156d..59fdeeb 100644 --- a/doc/README.gpt +++ b/doc/README.gpt @@ -157,11 +157,13 @@ To restore GUID partition table one needs to: "partitions=uuid_disk=${uuid_gpt_disk};name=${uboot_name}, size=${uboot_size},uuid=${uboot_uuid};" - Fields 'name', 'size' and 'uuid' are mandatory for every partition. + The fields 'name' and 'size' are mandatory for every partition. The field 'start' is optional. - option: CONFIG_RANDOM_UUID - If any partition "UUID" no exists then it is randomly generated. + The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is + enabled. A random uuid will be used if omitted or they point to an empty/ + non-existent environment variable. The environment variable will be set to + the generated UUID. 2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT' -- 2.1.0

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[U-Boot] [PATCH] gpt: fix error reporting on partition table write failures
by Rob Herring 06 Mar '15

06 Mar '15

The gpt command always reports success even if writing the partition table failed. Propagate the return value of gpt_restore so we get proper status reported. Signed-off-by: Rob Herring <robh(a)kernel.org> --- common/cmd_gpt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c index e38422d..75df3fe 100644 --- a/common/cmd_gpt.c +++ b/common/cmd_gpt.c @@ -281,11 +281,11 @@ static int gpt_default(block_dev_desc_t *blk_dev_desc, const char *str_part) } /* save partitions layout to disk */ - gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count); + ret = gpt_restore(blk_dev_desc, str_disk_guid, partitions, part_count); free(str_disk_guid); free(partitions); - return 0; + return ret; } /** -- 2.1.0

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[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 06 Mar '15

06 Mar '15

Hi Tom, SoCFPGA stuff for current release. The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08: Merge branch 'master' of git://git.denx.de/u-boot-ubi (2015-02-04 13:30:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git HEAD for you to fetch changes up to 6da3e0c1758f7316025e342ef0801efba9bd7f23: dt: socfpga: Import and enable Arria V DK DTS (2015-02-09 20:10:22 +0100) ---------------------------------------------------------------- Marek Vasut (10): arm: socfpga: Minor coding style fix arm: socfpga: Sync Cyclone V DK pinmux configuration arm: socfpga: Sync Cyclone V DK PLL configuration arm: socfpga: Add USB and UDC support for Cyclone V DK arm: socfpga: Drop cyclone5 suffix from board file name arm: socfpga: Zap checkboard() arm: socfpga: Zap board_early_init_f() arm: socfpga: Add Altera Arria V DK support dt: socfpga: Import and enable Cyclone V DK DTS dt: socfpga: Import and enable Arria V DK DTS arch/arm/Kconfig | 5 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/socfpga_arria5.dtsi | 34 +++++ arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++++++++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 79 ++++++++++ board/altera/socfpga/Kconfig | 16 ++ board/altera/socfpga/Makefile | 2 +- board/altera/socfpga/iocsr_config.c | 688 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 17 ++- board/altera/socfpga/pinmux_config.c | 403 +++++++++++++++++++++++++++++++++++++------------ board/altera/socfpga/pinmux_config.h | 14 +- board/altera/socfpga/pll_config.h | 34 ++--- board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} | 17 --- configs/socfpga_arria5_defconfig | 5 + configs/socfpga_cyclone5_defconfig | 2 + include/configs/socfpga_arria5.h | 107 +++++++++++++ include/configs/socfpga_common.h | 3 +- include/configs/socfpga_cyclone5.h | 9 ++ 18 files changed, 1365 insertions(+), 149 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria5.dtsi create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts rename board/altera/socfpga/{socfpga_cyclone5.c => socfpga.c} (86%) create mode 100644 configs/socfpga_arria5_defconfig create mode 100644 include/configs/socfpga_arria5.h

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