December 2015 - U-Boot

[U-Boot] [PATCH][v2] armv8: fsl-layerscape: fixes lsch2 serdes registers define
by shh.xie＠gmail.com 27 Jan '16

27 Jan '16

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- changes in v2: 1. fixes indent. .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 67 +++++++++++++++------- 1 file changed, 47 insertions(+), 20 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 83caa91..b794982 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -450,7 +450,8 @@ struct ccsr_serdes { u32 res_0c; /* 0x00c */ u32 pllcr3; u32 pllcr4; - u8 res_18[0x20-0x18]; + u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ + u8 res_1c[0x20-0x1c]; } bank[2]; u8 res_40[0x90-0x40]; u32 srdstcalcr; /* 0x90 TX Calibration Control */ @@ -458,25 +459,25 @@ struct ccsr_serdes { u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ u8 res_a4[0xb0-0xa4]; u32 srdsgr0; /* 0xb0 General Register 0 */ - u8 res_b4[0xe0-0xb4]; - u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ - u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ - u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ - u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ - u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ - u8 res_f4[0x100-0xf4]; + u8 res_b4[0x100-0xb4]; struct { - u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ u8 res_104[0x120-0x104]; - } srdslnpssr[4]; - u8 res_180[0x300-0x180]; - u32 srdspexeqcr; - u32 srdspexeqpcr[11]; - u8 res_330[0x400-0x330]; - u32 srdspexapcr; - u8 res_404[0x440-0x404]; - u32 srdspexbpcr; - u8 res_444[0x800-0x444]; + } lnpssr[4]; /* Lane A, B, C, D */ + u8 res_180[0x200-0x180]; + u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ + u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ + u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ + u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ + u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ + u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ + u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ + u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ + u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ + u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ + u32 srdspccra; /* 0x228 Protocol Configuration A */ + u32 srdspccrb; /* 0x22c Protocol Configuration B */ + u8 res_230[0x800-0x230]; struct { u32 gcr0; /* 0x800 General Control Register 0 */ u32 gcr1; /* 0x804 General Control Register 1 */ @@ -489,8 +490,34 @@ struct ccsr_serdes { u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ u8 res_824[0x83c-0x824]; u32 tcsr3; - } lane[4]; /* Lane A, B, C, D, E, F, G, H */ - u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ + } lane[4]; /* Lane A, B, C, D */ + u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ + struct { + u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ + u8 res_1004[0x1040-0x1004]; + } pcie[3]; + u8 res_10c0[0x1800-0x10c0]; + struct { + u8 res_1800[0x1804-0x1800]; + u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ + u8 res_1808[0x180c-0x1808]; + u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ + } sgmii[4]; /* Lane A, B, C, D */ + u8 res_1840[0x1880-0x1840]; + struct { + u8 res_1880[0x1884-0x1880]; + u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ + u8 res_1888[0x188c-0x1888]; + u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ + } qsgmii[2]; /* Lane A, B */ + u8 res_18a0[0x1980-0x18a0]; + struct { + u8 res_1980[0x1984-0x1980]; + u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ + u8 res_1988[0x198c-0x1988]; + u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ + } xfi[2]; /* Lane A, B */ + u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] arm: ls1021a: Adjust sata register default values
by Yuantian.Tang＠freescale.com 27 Jan '16

27 Jan '16

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> Updated the default sata register values to enhance the performance and stability. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c index deeb674..144f2c3 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c @@ -11,11 +11,11 @@ /* port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28183411 -#define AHCI_PORT_PHY_3_CFG 0x0e081004 -#define AHCI_PORT_PHY_4_CFG 0x00480811 -#define AHCI_PORT_PHY_5_CFG 0x192c96a4 -#define AHCI_PORT_TRANS_CFG 0x08000025 +#define AHCI_PORT_PHY_2_CFG 0x28183414 +#define AHCI_PORT_PHY_3_CFG 0x0e080e06 +#define AHCI_PORT_PHY_4_CFG 0x064a080b +#define AHCI_PORT_PHY_5_CFG 0x2aa86470 +#define AHCI_PORT_TRANS_CFG 0x08000029 #define SATA_ECC_REG_ADDR 0x20220520 #define SATA_ECC_DISABLE 0x00020000 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] driver/ddr/fsl: Add workaround for A009663
by Shengzhou Liu 27 Jan '16

27 Jan '16

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- v2: add more comments. arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ drivers/ddr/fsl/fsl_ddr_gen4.c | 10 ++++++++++ include/fsl_ddr_sdram.h | 1 + 6 files changed, 20 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6e5224e..fac82ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -118,6 +118,8 @@ #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 +#define CONFIG_SYS_FSL_ERRATUM_A009663 + #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -165,6 +167,7 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index f066480..424fe87 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -131,6 +131,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #else #error SoC not defined #endif diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a493556..3b06ae4 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -326,6 +326,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) puts("Work-around for Erratum XFI on B4860QDS enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + puts("Work-around for Erratum A009663 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 674fac8..eccc146 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -808,6 +808,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) @@ -856,6 +857,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3fca5c2..6bd447d 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -151,7 +151,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, + regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); +#else ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU @@ -379,6 +384,11 @@ step2: if (timeout <= 0) printf("Waiting for D_INIT timeout. Memory may not work.\n"); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif + #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { /* exit self-refresh */ diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 4b022d4..504903d 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -131,6 +131,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_ODT_ONLY_READ 2 #define SDRAM_CFG2_ODT_ALWAYS 3 +#define SDRAM_INTERVAL_BSTOPRE 0x3FFF #define TIMING_CFG_2_CPO_MASK 0x0F800000 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] armv8: fsl-lsch3: fixup SYSCLK frequency in device tree
by Prabhakar Kushwaha 27 Jan '16

27 Jan '16

SYSCLK frequency is dependent on on-board switch settings. It may vary as per requirement. boot-loader is aware of board switch configurations. So Fixup Linux device tree from boot-loader. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> CC: Mingkai Hu <Mingkai.Hu(a)freescale.com> --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index eafdd71..4e4861d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -190,6 +190,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif + do_fixup_by_compat_u32(blob, "fixed-clock", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif -- 1.9.1

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[U-Boot] [Patch V2 0/3] QIXIS related patches
by Gong Qianyu 27 Jan '16

27 Jan '16

Hi all, The version 2 patchset fixed to: - use qixis_write_i2c() instead of QIXIS_WRITE once QSPI is enabled. [Patch V2 1/3] freescale/qixis: Add support for booting from SD/QSPI [Patch V2 2/3] armv8/ls1043aqds: fix qixis_reset command issue [Patch V2 3/3] armv8/ls1043aqds: enable qixis_reset command to boot Regards, Qianyu

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[U-Boot] [PATCH v3 0/5] ARM: at91: improve peripheral and system clock handle functions
by Wenyou Yang 27 Jan '16

27 Jan '16

To reduce the duplicated code, rework the peripheral's and system's clock handle functions, use these functions to replace the clock handle code. Changes in v3: - fix incorrectly used the indicator '&' to achieve the variable pointer of pmc->pcer and pmc->pcdr. Changes in v2: - fix checkpatch warning. Wenyou Yang (5): ARM: at91: asm/at91_pmc.h: fix trival register offset ARM: at91: clock: add a new file to handle clock ARM: cpu: at91: clean up peripheral clock code board: atmel: clean up peripheral clock code drivers: at91: clean up peripheral clock code arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/arm920t/at91rm9200_devices.c | 13 +--- arch/arm/mach-at91/arm920t/timer.c | 4 +- arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c | 36 +++------- arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c | 37 +++------- .../mach-at91/arm926ejs/at91sam9m10g45_devices.c | 33 +++------ arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 40 +++-------- arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 38 +++-------- arch/arm/mach-at91/arm926ejs/clock.c | 7 -- arch/arm/mach-at91/arm926ejs/cpu.c | 1 - arch/arm/mach-at91/arm926ejs/timer.c | 5 +- arch/arm/mach-at91/armv7/clock.c | 26 ------- arch/arm/mach-at91/armv7/cpu.c | 1 - arch/arm/mach-at91/armv7/timer.c | 1 - arch/arm/mach-at91/clock.c | 72 ++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 8 +-- arch/arm/mach-at91/include/mach/clk.h | 2 + arch/arm/mach-at91/phy.c | 1 - arch/arm/mach-at91/sdram.c | 1 - board/atmel/at91rm9200ek/at91rm9200ek.c | 1 - board/atmel/at91rm9200ek/led.c | 5 +- board/atmel/at91sam9260ek/at91sam9260ek.c | 15 ++-- board/atmel/at91sam9261ek/at91sam9261ek.c | 8 +-- board/atmel/at91sam9261ek/led.c | 6 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 23 ++----- board/atmel/at91sam9263ek/led.c | 9 +-- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 20 ++---- board/atmel/at91sam9m10g45ek/led.c | 7 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 6 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 18 ++--- board/atmel/at91sam9rlek/led.c | 7 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 10 +-- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 1 - board/atmel/sama5d3_xplained/sama5d3_xplained.c | 5 +- board/atmel/sama5d3xek/sama5d3xek.c | 5 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 5 +- board/atmel/sama5d4ek/sama5d4ek.c | 5 +- board/bluewater/snapper9260/snapper9260.c | 15 ++-- board/calao/usb_a9263/usb_a9263.c | 11 ++- board/egnite/ethernut5/ethernut5.c | 20 +++--- board/esd/meesc/meesc.c | 15 ++-- board/mini-box/picosam9g45/led.c | 7 +- board/mini-box/picosam9g45/picosam9g45.c | 17 ++--- board/ronetix/pm9261/led.c | 7 +- board/ronetix/pm9261/pm9261.c | 22 ++---- board/ronetix/pm9263/led.c | 7 +- board/ronetix/pm9263/pm9263.c | 19 ++---- board/ronetix/pm9g45/pm9g45.c | 20 ++---- board/siemens/corvus/board.c | 6 +- board/siemens/smartweb/smartweb.c | 3 +- board/siemens/taurus/taurus.c | 3 +- drivers/net/at91_emac.c | 9 ++- drivers/usb/host/ehci-atmel.c | 8 --- drivers/usb/host/ohci-at91.c | 20 ++---- 56 files changed, 252 insertions(+), 496 deletions(-) create mode 100644 arch/arm/mach-at91/clock.c -- 1.7.9.5

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[U-Boot] [PATCH v3] net: macb: Not all the GEM are gigabit capable
by Gregory CLEMENT 27 Jan '16

27 Jan '16

During the initialization of PHY the gigabit bit capable is set if the controller is a GEM. However, for sama5d2 and sama5d4, the GEM is configured to support only 10/100. Improperly setting the GBE capability leads to an unresponsive MAC controller. This patch fixes this behavior allowing using the gmac with these SoCs. Suggested-by: Nicolas Ferre <nicolas.ferre(a)atmel.com> Signed-off-by: Gregory CLEMENT <gregory.clement(a)free-electrons.com> --- Hi, in this v3, I fixed the sama5d2 typo and the missing brace. I also took care of the cpu_is_* symbols which may not be defined depending of the choice of the SoC. Gregory drivers/net/macb.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index a5c1880..e801313 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -109,6 +109,23 @@ static int macb_is_gem(struct macb_device *macb) return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2; } +#ifndef cpu_is_sama5d2 +#define cpu_is_sama5d2() 0 +#endif + +#ifndef cpu_is_sama5d4 +#define cpu_is_sama5d4() 0 +#endif + +static int gem_is_gigabit_capable(struct macb_device *macb) +{ + /* + * The GEM controllers embeded in SAMA5D2 and SAMA5D4 are + * configured to support only 10/100. + */ + return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4(); +} + static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) { unsigned long netctl; @@ -480,8 +497,8 @@ static int macb_phy_init(struct macb_device *macb) return 0; } - /* First check for GMAC */ - if (macb_is_gem(macb)) { + /* First check for GMAC and that it is GiB capable */ + if (gem_is_gigabit_capable(macb)){ lpa = macb_mdio_read(macb, MII_STAT1000); if (lpa & (LPA_1000FULL | LPA_1000HALF)) { -- 2.5.0

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[U-Boot] [PATCH v2] mmc: atmel: Properly fix clock configuration
by Gregory CLEMENT 27 Jan '16

27 Jan '16

Timing issue occurs on eMMC not only when modifying the frequency but also for all the switch command(CMD6). According to the MMC spec waiting 8 clocks after a switch command would be the thing to do. This patch allows fixing CPU hang observed when trying to changing the bus width on a eMMC on SAMA5D4. Signed-off-by: Gregory CLEMENT <gregory.clement(a)free-electrons.com> Tested-by: Marek Vasut <marex(a)denx.de> # on DENX MA5D4EV --- drivers/mmc/gen_atmel_mci.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index da870c6..f090b27 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -36,6 +36,7 @@ struct atmel_mci_priv { struct mmc_config cfg; struct atmel_mci *mci; unsigned int initialized:1; + unsigned int curr_clk; }; /* Read Atmel MCI IP version */ @@ -91,7 +92,10 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) } } - + if (version >= 0x500) + priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2); + else + priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2; blklen &= 0xfffc; mr = MMCI_BF(CLKDIV, clkdiv); @@ -118,8 +122,6 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS) writel(MMCI_BIT(HSMODE), &mci->cfg); - udelay(50); - priv->initialized = 1; } @@ -323,6 +325,13 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) } } + /* + * After the switch command, wait for 8 clocks before the next + * command + */ + if (cmd->cmdidx == MMC_CMD_SWITCH) + udelay(8*1000000/ priv->curr_clk); /* 8 clk in us */ + return 0; } -- 2.5.0

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[U-Boot] [PATCH V6] sf: Turn SPI flash chip into 3-Byte address mode
by Zhiqiang Hou 27 Jan '16

27 Jan '16

From: Hou Zhiqiang <B48286(a)freescale.com> For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte address mode, and only the 3-Byte address mode is supported in U-Boot so far. So, reset the SPI flash to 3-Byte address mode in probe to ensure the SPI flash work correctly, because it may has been set to 4-Byte address mode after warm boot. Signed-off-by: Hou Zhiqiang <B48286(a)freescale.com> --- Tested on T1042RDB board. V6: Add the spi_release_bus. V5: 1. Removed #ifdef for STMICRO. 2. Add support for Spansion chips (>16MiB) switch to 3-Byte address mode. V4: Split the the patch to 2 patches for clear FSR and SPI flash address mode. V3: Generate the patch based on the latest tree git://git.denx.de/u-boot.git. V2: Add the operation of enter 3 Byte address mode in probe. V1: Based on git://git.denx.de/u-boot.git. drivers/mtd/spi/sf_internal.h | 7 +++++++ drivers/mtd/spi/sf_ops.c | 40 ++++++++++++++++++++++++++++++++++++++++ drivers/mtd/spi/sf_probe.c | 10 ++++++++++ 3 files changed, 57 insertions(+) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 1de1dac..9519bd8 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -75,6 +75,10 @@ enum { #define CMD_FLAG_STATUS 0x70 #define CMD_CLEAR_FLAG_STATUS 0x50 +/* Used for Micron, Macronix and Winbond flashes */ +#define CMD_ENTER_4B_ADDR 0xB7 +#define CMD_EXIT_4B_ADDR 0xE9 + /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_FAST 0x0b @@ -231,6 +235,9 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data); +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, + int enable, u8 idcode0); + #ifdef CONFIG_SPI_FLASH_MTD int spi_flash_mtd_register(struct spi_flash *flash); void spi_flash_mtd_unregister(void); diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index deebcab..de30c55 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -93,6 +93,46 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) } #endif +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, + int enable, u8 idcode0) +{ + int ret; + u8 cmd, bar; + bool need_wren = false; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + + switch (idcode0) { + case SPI_FLASH_CFI_MFR_STMICRO: + /* Some Micron need WREN command; all will accept it */ + need_wren = true; + case SPI_FLASH_CFI_MFR_MACRONIX: + case SPI_FLASH_CFI_MFR_WINBOND: + if (need_wren) + spi_flash_cmd_write_enable(flash); + + cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR; + ret = spi_flash_cmd(flash->spi, cmd, NULL, 0); + if (need_wren) + spi_flash_cmd_write_disable(flash); + + break; + default: + /* Spansion style */ + bar = enable << 7; + cmd = CMD_BANKADDR_BRWR; + ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &bar, 1); + } + + spi_release_bus(flash->spi); + + return ret; +} + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index e0283dc..3b204f8 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -170,6 +170,16 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode, flash->page_size <<= flash->shift; flash->sector_size = params->sector_size << flash->shift; flash->size = flash->sector_size * params->nr_sectors << flash->shift; + + /* + * So far, the 4-byte address mode haven't been supported in U-Boot, + * and make sure the chip (> 16MiB) in default 3-byte address mode, + * in case of warm bootup, the chip was set to 4-byte mode in kernel. + */ + if (flash->size > SPI_FLASH_16MB_BOUN) { + if (spi_flash_cmd_4B_addr_switch(flash, false, idcode[0]) < 0) + debug("SF: enter 3B address mode failed\n"); + } #ifdef CONFIG_SF_DUAL_FLASH if (flash->dual_flash & SF_DUAL_STACKED_FLASH) flash->size <<= 1; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2 0/5] Retrieve MAC address from EEPROM
by Olliver Schinagl 26 Jan '16

26 Jan '16

Changes since v1: * Do not CRC the id byte, move it just after the crc byte. One of the reasons I decided to move it after the crc8 was mostly due to mass generation of MAC + CRC combo's where the ID is still unknown. Also not crc-ing the ID means that it is much easier for a user to change it (via the u-boot i2c cmd line or from within linux) without having to worry about the crc. * Add a generator to convert a MAC address from the input to a MAC + CRC8 on the output. Olliver Schinagl (5): net: Add ability to set MAC address via EEPROM to Kconfig sunxi: net: Allow the sunxi to set the MAC from an EEPROM sunxi: net: Enable eeprom on OLinuXino Lime2 boards tools: Allow crc8 to be used tools: Add tool to add crc8 to a mac address board/sunxi/Kconfig | 4 +++ board/sunxi/board.c | 36 +++++++++++++++++++++ configs/A20-OLinuXino-Lime2_defconfig | 3 ++ doc/README.enetaddr | 34 ++++++++++++++++++++ include/u-boot/crc.h | 3 ++ net/Kconfig | 59 +++++++++++++++++++++++++++++++++++ tools/Makefile | 5 +++ tools/gen_mac_addr.c | 51 ++++++++++++++++++++++++++++++ 8 files changed, 195 insertions(+) create mode 100644 tools/gen_mac_addr.c -- 2.6.2

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