December 2015 - U-Boot

[U-Boot] [PATCH v3 0/4] x86: gpio: Tidy up GPIO driver
by Simon Glass 13 Mar '16

13 Mar '16

The ICH GPIO driver does not work correctly at present. This series tidies things up and fixes a few bugs. One issue remaining is that reading from output GPIOs does not work - it always returns 0. Changes in v3: - Correct failure logic in pci_get_bus() - Use pci_get_bus in pci_bus_to_hose() Changes in v2: - Adjust pci_get_bus() to probe bus 0 so that the required bus is found Simon Glass (4): dm: pci: Allow a PCI bus to be found without an alias gpio: Report errors when GPIOs cannot be read WIP: x86: gpio: Handle the case where reading a GPIO fails WIP: x86: gpio: Make sure that output GPIOs can be read common/cmd_gpio.c | 34 +++++++++++++++++++++++++++------- drivers/gpio/intel_ich6_gpio.c | 28 ++++++++++++++++++++++++++-- drivers/pci/pci-uclass.c | 28 ++++++++++++++++++++++++---- 3 files changed, 77 insertions(+), 13 deletions(-) -- 2.5.0.457.gab17608

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[U-Boot] [PATCH v4] x86: baytrail: Configure FSP UPD from device tree
by Andrew Bradford 12 Mar '16

12 Mar '16

From: Andrew Bradford <andrew.bradford(a)kodakalaris.com> Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself. Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used. Signed-off-by: Andrew Bradford <andrew.bradford(a)kodakalaris.com> --- Changes from v3: - Fix small typographical issues (lowercase hex numbers, grammar, etc), no functional changes. Changes from v2: - Switch to using booleans in dts, where appropriate. - Add Bayley Bay dts modifications. - Clarify docs to show bool versus int properties. - Include enable-igt property from FSPv4. Changes from v1: - Use "-" rather than "_" in dt property names. - Use "Bay Trail" for the formal name of the Intel product family. - Use an "fsp," prefix for dt property names for clarity. - Fix minor code indentation issues. - Create a dt subnode for the memory-down-params. - Clarify documentation that dt overrides the FSP's config, so we don't use booleans. arch/x86/cpu/baytrail/fsp_configs.c | 167 +++++++++++++++++---- arch/x86/dts/bayleybay.dts | 40 +++++ arch/x86/dts/minnowmax.dts | 58 +++++++ .../misc/intel,baytrail-fsp.txt | 158 +++++++++++++++++++ include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 6 files changed, 397 insertions(+), 30 deletions(-) create mode 100644 doc/device-tree-bindings/misc/intel,baytrail-fsp.txt diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 86b6926..ba56ebb 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -1,14 +1,18 @@ /* * Copyright (C) 2013, Intel Corporation * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * Copyright (C) 2015, Kodak Alaris, Inc * * SPDX-License-Identifier: Intel */ #include <common.h> +#include <fdtdec.h> #include <asm/arch/fsp/azalia.h> #include <asm/fsp/fsp_support.h> +DECLARE_GLOBAL_DATA_PTR; + /* ALC262 Verb Table - 10EC0262 */ static const uint32_t verb_table_data13[] = { /* Pin Complex (NID 0x11) */ @@ -116,41 +120,144 @@ const struct pch_azalia_config azalia_config = { .reset_wait_timer_us = 300 }; +/** + * Override the FSP's UPD. + * If the device tree does not specify an integer setting, use the default + * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. + */ void update_fsp_upd(struct upd_region *fsp_upd) { struct memory_down_data *mem; + const void *blob = gd->fdt_blob; + int node; - /* - * Configure everything here to avoid the poor hard-pressed user - * needing to run Intel's binary configuration tool. It may also allow - * us to support the 1GB single core variant easily. - * - * TODO(sjg(a)chromium.org): Move to device tree - */ - fsp_upd->mrc_init_tseg_size = 8; - fsp_upd->mrc_init_mmio_size = 0x800; - fsp_upd->emmc_boot_mode = 0xff; - fsp_upd->enable_sdio = 1; - fsp_upd->enable_sdcard = 1; - fsp_upd->enable_hsuart0 = 1; fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; - fsp_upd->enable_i2_c0 = 0; - fsp_upd->enable_i2_c2 = 0; - fsp_upd->enable_i2_c3 = 0; - fsp_upd->enable_i2_c4 = 0; - fsp_upd->enable_xhci = 0; - fsp_upd->igd_render_standby = 1; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-tseg-size", + 0); + fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-mmio-size", + 0x800); + fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr1", + 0xa0); + fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr2", + 0xa2); + fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node, + "fsp,emmc-boot-mode", 2); + fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio"); + fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node, + "fsp,enable-sdcard"); + fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart0"); + fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart1"); + fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi"); + fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata"); + fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", 1); + fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, + "fsp,enable-azalia"); + fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); + fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe"); + fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node, + "fsp,lpss-sio-enable-pci-mode"); + fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0"); + fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1"); + fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0"); + fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1"); + fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2"); + fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3"); + fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4"); + fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5"); + fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6"); + fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0"); + fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1"); + fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi"); + fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, + "fsp,igd-dvmt50-pre-alloc", + 2); + fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size", + 2); + fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2); + fsp_upd->serial_debug_port_address = fdtdec_get_int(blob, node, + "fsp,serial-debug-port-address", + 0x3f8); + fsp_upd->serial_debug_port_type = fdtdec_get_int(blob, node, + "fsp,serial-debug-port-type", + 1); + fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, + "fsp,mrc-debug-msg"); + fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); + fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node, + "fsp,scc-enable-pci-mode"); + fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node, + "fsp,igd-render-standby"); + fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node, + "fsp,txe-uma-enable"); + fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection", 4); + fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node, + "fsp,emmc45-ddr50-enabled"); + fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node, + "fsp,emmc45-hs200-enabled"); + fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node, + "fsp,emmc45-retune-timer-value", + 8); + fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd"); mem = &fsp_upd->memory_params; - mem->enable_memory_down = 1; - mem->dram_speed = 1; - mem->dimm_width = 1; - mem->dimm_density = 2; - mem->dimm_tcl = 0xb; - mem->dimm_trpt_rcd = 0xb; - mem->dimm_twr = 0xc; - mem->dimm_twtr = 6; - mem->dimm_trrd = 6; - mem->dimm_trtp = 6; - mem->dimm_tfaw = 0x14; + mem->enable_memory_down = fdtdec_get_bool(blob, node, + "fsp,enable-memory-down"); + if (mem->enable_memory_down) { + node = fdtdec_next_compatible(blob, node, + COMPAT_INTEL_BAYTRAIL_FSP_MDP); + if (node < 0) { + debug("%s: Cannot find FSP memory-down-params node\n", + __func__); + } else { + mem->dram_speed = fdtdec_get_int(blob, node, + "fsp,dram-speed", + 0x02); + mem->dram_type = fdtdec_get_int(blob, node, + "fsp,dram-type", 0x01); + mem->dimm_0_enable = fdtdec_get_bool(blob, node, + "fsp,dimm-0-enable"); + mem->dimm_1_enable = fdtdec_get_bool(blob, node, + "fsp,dimm-1-enable"); + mem->dimm_width = fdtdec_get_int(blob, node, + "fsp,dimm-width", + 0x00); + mem->dimm_density = fdtdec_get_int(blob, node, + "fsp,dimm-density", + 0x01); + mem->dimm_bus_width = fdtdec_get_int(blob, node, + "fsp,dimm-bus-width", + 0x03); + mem->dimm_sides = fdtdec_get_int(blob, node, + "fsp,dimm-sides", + 0x00); + mem->dimm_tcl = fdtdec_get_int(blob, node, + "fsp,dimm-tcl", 0x09); + mem->dimm_trpt_rcd = fdtdec_get_int(blob, node, + "fsp,dimm-trpt-rcd", + 0x09); + mem->dimm_twr = fdtdec_get_int(blob, node, + "fsp,dimm-twr", 0x0A); + mem->dimm_twtr = fdtdec_get_int(blob, node, + "fsp,dimm-twtr", 0x05); + mem->dimm_trrd = fdtdec_get_int(blob, node, + "fsp,dimm-trrd", 0x04); + mem->dimm_trtp = fdtdec_get_int(blob, node, + "fsp,dimm-trtp", 0x05); + mem->dimm_tfaw = fdtdec_get_int(blob, node, + "fsp,dimm-tfaw", 0x14); + } + } } diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 9f8fa70..0ca7c3e 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -188,6 +188,46 @@ }; }; + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <2>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-xhci; + fsp,enable-lpe; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,serial-debug-port-address = <0x3f8>; + fsp,serial-debug-port-type = <1>; + fsp,mrc-debug-msg; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + }; + microcode { update@0 { #include "microcode/m0230671117.dtsi" diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 9527233..4c9e265 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -122,6 +122,64 @@ 0x01000000 0x0 0x2000 0x2000 0 0xe000>; }; + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <2>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-xhci; + fsp,enable-lpe; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,serial-debug-port-address = <0x3f8>; + fsp,serial-debug-port-type = <1>; + fsp,mrc-debug-msg; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + fsp,enable-memory-down; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <1>; + fsp,dram-type = <1>; + fsp,dimm-0-enable; + fsp,dimm-width = <1>; + fsp,dimm-density = <2>; + fsp,dimm-bus-width = <3>; + fsp,dimm-sides = <0>; + fsp,dimm-tcl = <0xb>; + fsp,dimm-trpt-rcd = <0xb>; + fsp,dimm-twr = <0xc>; + fsp,dimm-twtr = <6>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <6>; + fsp,dimm-tfaw = <0x14>; + }; + }; + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt new file mode 100644 index 0000000..b44b5b5 --- /dev/null +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -0,0 +1,158 @@ +Intel Bay Trail FSP UPD Binding +=============================== + +The device tree node which describes the overriding of the Intel Bay Trail FSP +UPD data for configuring the SoC. + +All properties can be found within the `upd-region` struct in +arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in +Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties is +matched up to Intel's E3800 FSPv4 release. + +# Boolean properties: + +- fsp,enable-sdio +- fsp,enable-sdcard +- fsp,enable-hsuart0 +- fsp,enable-hsuart1 +- fsp,enable-spi +- fsp,enable-sata +- fsp,enable-azalia +- fsp,enable-xhci +- fsp,enable-lpe +- fsp,lpss-sio-enable-pci-mode +- fsp,enable-dma0 +- fsp,enable-dma1 +- fsp,enable-i2-c0 +- fsp,enable-i2-c1 +- fsp,enable-i2-c2 +- fsp,enable-i2-c3 +- fsp,enable-i2-c4 +- fsp,enable-i2-c5 +- fsp,enable-i2-c6 +- fsp,enable-pwm0 +- fsp,enable-pwm1 +- fsp,enable-hsi +- fsp,mrc-debug-msg +- fsp,isp-enable +- fsp,scc-enable-pci-mode +- fsp,igd-render-standby +- fsp,txe-uma-enable +- fsp,emmc45-ddr50-enabled +- fsp,emmc45-hs200-enabled +- fsp,enable-igd +- fsp,enable-memory-down + +If you set "fsp,enable-memory-down" you are strongly encouraged to provide an +"fsp,memory-down-params{};" to specify how your memory is configured. If you do +not set "fsp,enable-memory-down", then the DIMM SPD information will be +discovered by the FSP and used to setup main memory. + + +# Integer properties: + +- fsp,mrc-init-tseg-size +- fsp,mrc-init-mmio-size +- fsp,mrc-init-spd-addr1 +- fsp,mrc-init-spd-addr2 +- fsp,emmc-boot-mode +- fsp,sata-mode +- fsp,igd-dvmt50-pre-alloc +- fsp,aperture-size +- fsp,gtt-size +- fsp,serial-debug-port-address +- fsp,serial-debug-port-type +- fsp,os-selection +- fsp,emmc45-retune-timer-value + +- fsp,memory-down-params { + + # Boolean properties: + + - fsp,dimm-0-enable + - fsp,dimm-1-enable + + # Integer properties: + + - fsp,dram-speed + - fsp,dram-type + - fsp,dimm-width + - fsp,dimm-density + - fsp,dimm-bus-width + - fsp,dimm-sides + - fsp,dimm-tcl + - fsp,dimm-trpt-rcd + - fsp,dimm-twr + - fsp,dimm-twtr + - fsp,dimm-trrd + - fsp,dimm-trtp + - fsp,dimm-tfaw +}; + + +Example (from MinnowMax Dual Core): +----------------------------------- + +/ { + ... + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <2>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-xhci; + fsp,enable-lpe; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,serial-debug-port-address = <0x3f8>; + fsp,serial-debug-port-type = <1>; + fsp,mrc-debug-msg; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + fsp,enable-memory-down; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <1>; + fsp,dram-type = <1>; + fsp,dimm-0-enable; + fsp,dimm-width = <1>; + fsp,dimm-density = <2>; + fsp,dimm-bus-width = <3>; + fsp,dimm-sides = <0>; + fsp,dimm-tcl = <0xb>; + fsp,dimm-trpt-rcd = <0xb>; + fsp,dimm-twr = <0xc>; + fsp,dimm-twtr = <6>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <6>; + fsp,dimm-tfaw = <0x14>; + }; + }; + + ... +}; diff --git a/include/fdtdec.h b/include/fdtdec.h index 4b3f8d1..987d51a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -186,6 +186,8 @@ enum fdt_compat_id { COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ + COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ + COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel Bay Trail FSP memory-down params */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 48667ef..42e8a8b 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -78,6 +78,8 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"), COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"), COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"), + COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), + COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- 1.9.1

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[U-Boot] [PATCH v1 1/3] fastboot: OUT transaction length must be aligned to wMaxPacketSize
by Dileep Katta 11 Mar '16

11 Mar '16

OUT transactions must be aligned to wMaxPacketSize for each transfer, or else transfer will not complete successfully. This patch modifies rx_bytes_expected to return a transfer length that is aligned to wMaxPacketSize. Note that the value of ep->desc->wMaxPacketSize and ep->maxpacket may not be the same value, and it is the value of ep->desc->wMaxPacketSize that should be used for alignment. Signed-off-by: Dileep Katta <dileep.katta(a)linaro.org> --- drivers/usb/gadget/f_fastboot.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index a8d8205..0d53a61 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -370,13 +370,20 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) fastboot_tx_write_str(response); } -static unsigned int rx_bytes_expected(void) +static unsigned int rx_bytes_expected(unsigned maxpacket) { int rx_remain = download_size - download_bytes; + int rem = 0; if (rx_remain < 0) return 0; if (rx_remain > EP_BUFFER_SIZE) return EP_BUFFER_SIZE; + if (rx_remain < maxpacket) { + rx_remain = maxpacket; + } else if (rx_remain % maxpacket != 0) { + rem = rx_remain % maxpacket; + rx_remain = rx_remain + (maxpacket - rem); + } return rx_remain; } @@ -425,7 +432,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) printf("\ndownloading of %d bytes finished\n", download_bytes); } else { - req->length = rx_bytes_expected(); + req->length = rx_bytes_expected(ep->desc->wMaxPacketSize); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } @@ -453,7 +460,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) } else { sprintf(response, "DATA%08x", download_size); req->complete = rx_handler_dl_image; - req->length = rx_bytes_expected(); + req->length = rx_bytes_expected(ep->desc->wMaxPacketSize); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } -- 1.8.3.2

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[U-Boot] How do I tell buildman to use a /specific/ toolchain?
by Stephen Warren 07 Mar '16

07 Mar '16

Simon, I have 3 different ARM toolchains installed into /usr/bin via distro packages. How do I tell buildman which of those to use? I had originally thought that ~/.buildman's [toolchain] section contained CROSS_COMPILE-like values, so I tried: > [toolchain] > root: / > arm0-not-installed: arm-none-gnueabi- > arm1: arm-none-eabi- > arm2: arm-linux-gnueabihf- > arm3: arm-linux-gnueabi- > arch64: aarch64-linux-gnu- > > [toolchain-alias] > arm: arm1 > aarch64: aarch64 (I intended to change the "arm: arm1" line to point at arm1/2/3 based on which I wanted to use at a particular time). However, running "buildman --list-toolchains" and re-reading the docs shows me that the [toolchain] values are absolute directories that buildman searches for files named *-gcc: > - scanning path 'arm-none-gnueabi-' > - looking in 'arm-none-gnueabi-/.' > - looking in 'arm-none-gnueabi-/bin' > - looking in 'arm-none-gnueabi-/usr/bin' If buildman finds multiple toolchains, there doesn't seem to be a way to tell it which one to use. Am I missing something? I suppose a solution wouuld be to move the compiler binaries into different separate directories, and only list one of those directories in ~/.buildman. However, I can't do that for distro-packaged toolchains (well, I suppose I could manually mv everything all over the place, but that's really fragile since it'd break any time the package got upgraded or removed and re-installed). I think it makes sense to add new syntax into ~/.buildman to specify "don't do automagical searching, just use this CROSS_COMPILE value that I say". Does that sound reasonable? Automagic stuff makes for great defaults, but if it can't be overridden, it sucks when you actually know what you want.

3 10

[U-Boot] Weird error message on buildman
by Masahiro Yamada 07 Mar '16

07 Mar '16

Hi Simon, When I try to run Buildman against a branch named "test", it fails with a weird error message. $ git branch * master $ git checkout -b test master Switched to a new branch 'test' $ echo foo >> README $ git add README $ git commit -m foo [test f8f6569] foo 1 file changed, 1 insertion(+) $ tools/buildman/buildman -b test Branch 'test' not found $ git branch master * test Indeed, the branch "test" exists, but Buildman reports "Branch "test' not found". Could you check it out, please? Best Regards Masahiro Yamada

2 2

[U-Boot] Samsung I2C driver
by Simon Glass 01 Mar '16

01 Mar '16

Hi Przemyslaw, At present this driver has a few implementations and supports non-device-tree and non-driver model. From I can see the odroid and perhaps one other platform need conversion and then all of this old stuff can be removed. Do you have any plans to look at this? Regards, Simon

3 7

[U-Boot] [PATCH 1/3][v3] Pointers in ESBC header made 32 bit
by Aneesh Bansal 23 Feb '16

23 Feb '16

For the Chain of Trust, the esbc_validate command supports 32 bit fields for location of the image. In the header structure definition, these were declared as pointers which made them 64 bit on a 64 bit core. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v3: Patch Rebased and removed compile time warnings board/freescale/common/fsl_validate.c | 20 ++++++++++---------- include/fsl_validate.h | 14 +++++++------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 5283648..465676f 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img) * address */ #if defined(CONFIG_MPC85xx) -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); - ulong flash_addr, addr; + u32 flash_addr, addr; int found = 0; int i = 0; @@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) flash_addr = flash_info[i].start[0]; addr = flash_info[i].start[0] + csf_flash_offset; if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { - debug("Barker found on addr %lx\n", addr); + debug("Barker found on addr %x\n", addr); found = 1; break; } @@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) /* For platforms like LS1020, correct flash address is present in * the header. So the function reqturns flash base address as 0 */ -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); @@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) } #endif -static int get_ie_info_addr(ulong *ie_addr) +static int get_ie_info_addr(u32 *ie_addr) { struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_sg_table *sg_tbl; - ulong flash_base_addr, csf_addr; + u32 flash_base_addr, csf_addr; if (get_csf_base_addr(&csf_addr, &flash_base_addr)) return -1; @@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr) */ #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) sg_tbl = (struct fsl_secboot_sg_table *) - (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr + - (ulong)hdr->psgtable); + (u32)hdr->psgtable); #endif /* IE Key Table is the first entry in the SG Table */ @@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr) *ie_addr = sg_tbl->src_addr; #endif - debug("IE Table address is %lx\n", *ie_addr); + debug("IE Table address is %x\n", *ie_addr); return 0; } @@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; - sprintf(buf, "%p", hdr->pimg); + sprintf(buf, "%x", hdr->pimg); setenv("img_addr", buf); if (!hdr->img_size) diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c460534..92dd98b 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr { u32 psign; /* signature offset */ u32 sign_len; /* length of the signature in bytes */ union { - struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */ - u8 *pimg; /* ptr to ESBC client image */ + u32 psgtable; /* ptr to SG table */ + u32 pimg; /* ptr to ESBC client image */ }; union { u32 sg_entries; /* no of entries in SG table */ u32 img_size; /* ESBC client image size in bytes */ }; - ulong img_start; /* ESBC client entry point */ + u32 img_start; /* ESBC client entry point */ u32 sg_flag; /* Scatter gather flag */ u32 uid_flag; u32 fsl_uid_0; @@ -133,7 +133,7 @@ struct srk_table { */ struct fsl_secboot_sg_table { u32 len; /* length of the segment in bytes */ - ulong src_addr; /* ptr to the data segment */ + u32 src_addr; /* ptr to the data segment */ }; #else /* @@ -146,8 +146,8 @@ struct fsl_secboot_sg_table { struct fsl_secboot_sg_table { u32 len; u32 trgt_id; - ulong src_addr; - ulong dst_addr; + u32 src_addr; + u32 dst_addr; }; #endif @@ -162,7 +162,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - ulong ie_addr; + u32 ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr; -- 1.8.1.4

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[U-Boot] [PATCH 01/10] video: Add S3C24xx framebuffer support
by Marek Vasut 22 Feb '16

22 Feb '16

Add basic framebuffer driver for the S3C24xx family of CPUs. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Anatolij Gustschin <agust(a)denx.de> Cc: Kyungmin Park <kyungmin.park(a)samsung.com> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> Cc: Vladimir Zapolskiy <vz(a)mleia.com> V2: Keep the Makefile sorted. --- drivers/video/Makefile | 1 + drivers/video/cfb_console.c | 2 +- drivers/video/s3c-fb.c | 172 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 174 insertions(+), 1 deletion(-) create mode 100644 drivers/video/s3c-fb.c diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 14a6781..0e407d0 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +obj-$(CONFIG_VIDEO_S3C) += s3c-fb.o videomodes.o obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 9231927..98d10e3 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -135,7 +135,7 @@ #endif #endif -#ifdef CONFIG_VIDEO_MXS +#if defined(CONFIG_VIDEO_MXS) || defined(CONFIG_VIDEO_S3C) #define VIDEO_FB_16BPP_WORD_SWAP #endif diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c new file mode 100644 index 0000000..521eb75 --- /dev/null +++ b/drivers/video/s3c-fb.c @@ -0,0 +1,172 @@ +/* + * S3C24x0 LCD driver + * + * NOTE: Only 16/24 bpp operation with TFT LCD is supported. + * + * Copyright (C) 2014 Marek Vasut <marex(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <video_fb.h> + +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> + +#include "videomodes.h" + +static GraphicDevice panel; + +/* S3C requires the FB to be 4MiB aligned. */ +#define S3CFB_ALIGN (4 << 20) + +#define S3CFB_LCDCON1_CLKVAL(x) ((x) << 8) +#define S3CFB_LCDCON1_PNRMODE_TFT (0x3 << 5) +#define S3CFB_LCDCON1_BPPMODE_TFT_16BPP (0xc << 1) +#define S3CFB_LCDCON1_BPPMODE_TFT_24BPP (0xd << 1) + +#define S3CFB_LCDCON2_VBPD(x) ((x) << 24) +#define S3CFB_LCDCON2_LINEVAL(x) ((x) << 14) +#define S3CFB_LCDCON2_VFPD(x) ((x) << 6) +#define S3CFB_LCDCON2_VSPW(x) ((x) << 0) + +#define S3CFB_LCDCON3_HBPD(x) ((x) << 19) +#define S3CFB_LCDCON3_HOZVAL(x) ((x) << 8) +#define S3CFB_LCDCON3_HFPD(x) ((x) << 0) + +#define S3CFB_LCDCON4_HSPW(x) ((x) << 0) + +#define S3CFB_LCDCON5_BPP24BL (1 << 12) +#define S3CFB_LCDCON5_FRM565 (1 << 11) +#define S3CFB_LCDCON5_HWSWP (1 << 0) + +#define PS2KHZ(ps) (1000000000UL / (ps)) + +/* + * Example: + * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\ + * pclk:30066,le:41,ri:89,up:45,lo:12, + * hs:1,vs:1,sync:100663296,vmode:0 + */ +static void s3c_lcd_init(GraphicDevice *panel, + struct ctfb_res_modes *mode, int bpp) +{ + uint32_t clk_divider; + struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd(); + + /* Stop the controller. */ + clrbits_le32(&regs->lcdcon1, 1); + + /* Calculate clock divider. */ + clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000; + clk_divider = DIV_ROUND_UP(clk_divider, 2); + if (clk_divider) + clk_divider -= 1; + + /* Program LCD configuration. */ + switch (bpp) { + case 16: + writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + &regs->lcdcon1); + writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565, + &regs->lcdcon5); + break; + case 24: + writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + &regs->lcdcon1); + writel(S3CFB_LCDCON5_BPP24BL, &regs->lcdcon5); + break; + } + + writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) | + S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) | + S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) | + S3CFB_LCDCON2_VSPW(mode->vsync_len - 1), + &regs->lcdcon2); + + writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) | + S3CFB_LCDCON3_HFPD(mode->left_margin - 1) | + S3CFB_LCDCON3_HOZVAL(mode->xres - 1), + &regs->lcdcon3); + + writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1), + &regs->lcdcon4); + + /* Write FB address. */ + writel(panel->frameAdrs >> 1, &regs->lcdsaddr1); + writel((panel->frameAdrs + + (mode->xres * mode->yres * panel->gdfBytesPP)) >> 1, + &regs->lcdsaddr2); + writel(mode->xres * bpp / 16, &regs->lcdsaddr3); + + /* Start the controller. */ + setbits_le32(&regs->lcdcon1, 1); +} + +void *video_hw_init(void) +{ + int bpp = -1; + char *penv; + void *fb; + struct ctfb_res_modes mode; + + puts("Video: "); + + /* Suck display configuration from "videomode" variable */ + penv = getenv("videomode"); + if (!penv) { + puts("S3CFB: 'videomode' variable not set!\n"); + return NULL; + } + + bpp = video_get_params(&mode, penv); + + /* fill in Graphic device struct */ + sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); + + panel.winSizeX = mode.xres; + panel.winSizeY = mode.yres; + panel.plnSizeX = mode.xres; + panel.plnSizeY = mode.yres; + + switch (bpp) { + case 24: + panel.gdfBytesPP = 4; + panel.gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + panel.gdfBytesPP = 2; + panel.gdfIndex = GDF_16BIT_565RGB; + break; + default: + printf("S3CFB: Invalid BPP specified! (bpp = %i)\n", bpp); + return NULL; + } + + panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; + + /* Allocate framebuffer */ + fb = memalign(S3CFB_ALIGN, roundup(panel.memSize, S3CFB_ALIGN)); + if (!fb) { + printf("S3CFB: Error allocating framebuffer!\n"); + return NULL; + } + + /* Wipe framebuffer */ + memset(fb, 0, panel.memSize); + + panel.frameAdrs = (u32)fb; + + printf("%s\n", panel.modeIdent); + + /* Start framebuffer */ + s3c_lcd_init(&panel, &mode, bpp); + + return (void *)&panel; +} -- 2.1.1

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[U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support
by Bin Meng 19 Feb '16

19 Feb '16

This series adds Intel FSP support to IvyBridge processor and Panther Point chipset (aka Chief River platform), and is validated on Intel Cougar Canyon 2 board. This only adds basic features like serial, keyboard, RTC, timer, SPI, GPIO, PCI, SATA, USB. Other features will be enabled in future patch set. Bin Meng (10): fdtdec: Add compatible string for Intel IvyBridge FSP x86: ivybridge: Add FSP support tools: microcode-tool: Support parsing header file with a license block x86: ivybridge: Add microcode blobs for all the steppings superio: Add SMSC SIO1007 driver x86: ivybridge: Do not require HAVE_INTEL_ME x86: fsp: Make sure HOB list is not overwritten by U-Boot x86: fsp: Always use hex numbers in the hob command output x86: ivybridge: Add macros for LPC decode ranges x86: Add Intel Cougar Canyon 2 board arch/x86/cpu/ivybridge/Kconfig | 9 +- arch/x86/cpu/ivybridge/Makefile | 4 + arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++ arch/x86/cpu/ivybridge/ivybridge.c | 22 + arch/x86/dts/Makefile | 1 + arch/x86/dts/cougarcanyon2.dts | 96 +++ arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++ arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++ arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++ arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 +++++++++++++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 ++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 + arch/x86/include/asm/arch-ivybridge/pch.h | 10 + arch/x86/lib/fsp/cmd_fsp.c | 4 +- arch/x86/lib/fsp/fsp_support.c | 27 + board/google/chromebook_link/Kconfig | 1 + board/google/chromebox_panther/Kconfig | 1 + board/intel/Kconfig | 9 + board/intel/cougarcanyon2/Kconfig | 25 + board/intel/cougarcanyon2/MAINTAINERS | 6 + board/intel/cougarcanyon2/Makefile | 7 + board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++ board/intel/cougarcanyon2/start.S | 9 + configs/cougarcanyon2_defconfig | 21 + drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++ include/configs/cougarcanyon2.h | 34 + include/fdtdec.h | 1 + include/smsc_sio1007.h | 115 ++++ lib/fdtdec.c | 1 + tools/microcode-tool.py | 14 + 31 files changed, 3158 insertions(+), 3 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/dts/cougarcanyon2.dts create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h create mode 100644 board/intel/cougarcanyon2/Kconfig create mode 100644 board/intel/cougarcanyon2/MAINTAINERS create mode 100644 board/intel/cougarcanyon2/Makefile create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c create mode 100644 board/intel/cougarcanyon2/start.S create mode 100644 configs/cougarcanyon2_defconfig create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/configs/cougarcanyon2.h create mode 100644 include/smsc_sio1007.h -- 1.8.2.1

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[U-Boot] Adding support for SPI-attached MR25H256 MRAM with Device Tree
by Simon Falsig 15 Feb '16

15 Feb '16

I have a custom board based on a TI AM3356 processor (quite similar to a BeagleBone) with an Everspin MR25H256 MRAM attached to the SPI bus, currently using U-Boot 2015.10 to boot a 3.18.9-rt5 Linux kernel. I'd like to use this MRAM to store the MAC address for one of the Ethernet interfaces, but I'm having a bit of trouble getting started on how support for this should be added. I can access the MRAM just fine from Linux (using the m25p80 driver and the MTD framework), so with the appropriate drivers compiled into the kernel, Linux picks the chip up without any issue by simply adding the following to the device tree: mram: m25p80@0 { #address-cells = <1>; #size-cells = <1>; compatible = "mr25h256"; reg = <0>; spi-max-frequency = <40000000>; status = "okay"; }; I'd like U-Boot to do something similar, but there are a few issues: 1. The chip is not JEDEC compatible, so it cannot be probed like the other chips currently listed in drivers/mtd/spi/sf_params.c 2. Since it's an MRAM, it doesn't need to be erased before being written - Linux has a flag for this, but it doesn't seem as if U-Boot has anything similar. (Not that I need this currently though, as I only need to be able to read the chip for now - but it'd be nice to have, and others might be able to use it too.) I've tried having a look at doc/driver-model/spi-howto.txt, hoping that this would have up-to-date information on how to implement/modify a SPI driver, but when I for instance look at spi_setup_slave_fdt(), which seems to be one of the necessary functions, I can only find it implemented in drivers/spi/spi-uclass.c, with a comment saying that it is only for compatibility, and that it is to be removed?... If anyone can help me with a few hints on how to get started adding support for this chip, it'd be much appreciated! Thanks in advance and best regards, Simon Falsig simon(a)newtec.dk

2 3