November 2015 - U-Boot

[U-Boot] [PATCH 1/2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
by Prabhakar Kushwaha 03 Nov '15

03 Nov '15

From: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)freescale.com> LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)freescale.com> --- README | 3 + arch/arm/Kconfig | 44 +++++++---- arch/arm/cpu/armv8/fsl-lsch3/Makefile | 2 +- arch/arm/cpu/armv8/fsl-lsch3/README | 4 +- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 10 ++- arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 2 +- .../{ls2085a_serdes.c => ls2080a_serdes.c} | 2 +- arch/arm/cpu/armv8/fsl-lsch3/speed.c | 10 +++ arch/arm/dts/Makefile | 4 +- .../{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts} | 8 +- .../{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts} | 8 +- .../arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} | 4 +- arch/arm/include/asm/arch-fsl-lsch3/config.h | 8 +- arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 2 + .../{ls2085a_stream_id.h => ls2080a_stream_id.h} | 4 +- arch/arm/include/asm/global_data.h | 2 +- board/freescale/{ls2085a => ls2080a}/Kconfig | 12 +-- board/freescale/ls2080a/MAINTAINERS | 8 ++ board/freescale/{ls2085a => ls2080a}/Makefile | 2 +- board/freescale/{ls2085a => ls2080a}/README | 2 +- board/freescale/{ls2085a => ls2080a}/ddr.c | 3 +- board/freescale/{ls2085a => ls2080a}/ddr.h | 0 .../{ls2085a/ls2085a.c => ls2080a/ls2080a.c} | 4 +- board/freescale/{ls2085aqds => ls2080aqds}/Kconfig | 6 +- board/freescale/ls2080aqds/MAINTAINERS | 8 ++ .../freescale/{ls2085aqds => ls2080aqds}/Makefile | 2 +- board/freescale/{ls2085aqds => ls2080aqds}/README | 16 ++-- board/freescale/{ls2085aqds => ls2080aqds}/ddr.c | 5 +- board/freescale/{ls2085aqds => ls2080aqds}/ddr.h | 0 board/freescale/{ls2085aqds => ls2080aqds}/eth.c | 92 +++++++++++----------- .../ls2085aqds.c => ls2080aqds/ls2080aqds.c} | 6 +- .../ls2080aqds_qixis.h} | 0 board/freescale/{ls2085ardb => ls2080ardb}/Kconfig | 6 +- board/freescale/ls2080ardb/MAINTAINERS | 8 ++ .../freescale/{ls2085ardb => ls2080ardb}/Makefile | 2 +- board/freescale/{ls2085ardb => ls2080ardb}/README | 12 +-- board/freescale/{ls2085ardb => ls2080ardb}/ddr.c | 5 +- board/freescale/{ls2085ardb => ls2080ardb}/ddr.h | 0 .../eth_ls2085rdb.c => ls2080ardb/eth_ls2080rdb.c} | 2 +- .../ls2085ardb.c => ls2080ardb/ls2080ardb.c} | 6 +- .../ls2080ardb_qixis.h} | 0 board/freescale/ls2085a/MAINTAINERS | 8 -- board/freescale/ls2085aqds/MAINTAINERS | 8 -- board/freescale/ls2085ardb/MAINTAINERS | 8 -- ...ls2085a_emu_defconfig => ls2080a_emu_defconfig} | 3 +- ...2085a_simu_defconfig => ls2080a_simu_defconfig} | 3 +- .../{ls2085ardb_defconfig => ls2080aqds_defconfig} | 5 +- ...ds_nand_defconfig => ls2080aqds_nand_defconfig} | 3 +- .../{ls2085aqds_defconfig => ls2080ardb_defconfig} | 5 +- ...db_nand_defconfig => ls2080ardb_nand_defconfig} | 3 +- doc/README.fsl-trustzone-components | 4 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 4 +- drivers/mmc/fsl_esdhc.c | 12 +-- drivers/net/ldpaa_eth/Makefile | 2 +- drivers/net/ldpaa_eth/{ls2085a.c => ls2080a.c} | 0 drivers/pci/pcie_layerscape.c | 2 +- .../configs/{ls2085a_common.h => ls2080a_common.h} | 7 +- include/configs/{ls2085a_emu.h => ls2080a_emu.h} | 8 +- include/configs/{ls2085a_simu.h => ls2080a_simu.h} | 8 +- include/configs/{ls2085aqds.h => ls2080aqds.h} | 4 +- include/configs/{ls2085ardb.h => ls2080ardb.h} | 4 +- include/fsl_esdhc.h | 2 +- include/linux/usb/xhci-fsl.h | 6 +- 63 files changed, 241 insertions(+), 192 deletions(-) rename arch/arm/cpu/armv8/fsl-lsch3/{ls2085a_serdes.c => ls2080a_serdes.c} (98%) rename arch/arm/dts/{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts} (80%) rename arch/arm/dts/{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts} (67%) rename arch/arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} (97%) rename arch/arm/include/asm/arch-fsl-lsch3/{ls2085a_stream_id.h => ls2080a_stream_id.h} (93%) rename board/freescale/{ls2085a => ls2080a}/Kconfig (66%) create mode 100644 board/freescale/ls2080a/MAINTAINERS rename board/freescale/{ls2085a => ls2080a}/Makefile (83%) rename board/freescale/{ls2085a => ls2080a}/README (97%) rename board/freescale/{ls2085a => ls2080a}/ddr.c (99%) rename board/freescale/{ls2085a => ls2080a}/ddr.h (100%) rename board/freescale/{ls2085a/ls2085a.c => ls2080a/ls2080a.c} (98%) rename board/freescale/{ls2085aqds => ls2080aqds}/Kconfig (66%) create mode 100644 board/freescale/ls2080aqds/MAINTAINERS rename board/freescale/{ls2085aqds => ls2080aqds}/Makefile (83%) rename board/freescale/{ls2085aqds => ls2080aqds}/README (95%) rename board/freescale/{ls2085aqds => ls2080aqds}/ddr.c (98%) rename board/freescale/{ls2085aqds => ls2080aqds}/ddr.h (100%) rename board/freescale/{ls2085aqds => ls2080aqds}/eth.c (88%) rename board/freescale/{ls2085aqds/ls2085aqds.c => ls2080aqds/ls2080aqds.c} (98%) rename board/freescale/{ls2085aqds/ls2085aqds_qixis.h => ls2080aqds/ls2080aqds_qixis.h} (100%) rename board/freescale/{ls2085ardb => ls2080ardb}/Kconfig (66%) create mode 100644 board/freescale/ls2080ardb/MAINTAINERS rename board/freescale/{ls2085ardb => ls2080ardb}/Makefile (72%) rename board/freescale/{ls2085ardb => ls2080ardb}/README (94%) rename board/freescale/{ls2085ardb => ls2080ardb}/ddr.c (98%) rename board/freescale/{ls2085ardb => ls2080ardb}/ddr.h (100%) rename board/freescale/{ls2085ardb/eth_ls2085rdb.c => ls2080ardb/eth_ls2080rdb.c} (98%) rename board/freescale/{ls2085ardb/ls2085ardb.c => ls2080ardb/ls2080ardb.c} (98%) rename board/freescale/{ls2085ardb/ls2085ardb_qixis.h => ls2080ardb/ls2080ardb_qixis.h} (100%) delete mode 100644 board/freescale/ls2085a/MAINTAINERS delete mode 100644 board/freescale/ls2085aqds/MAINTAINERS delete mode 100644 board/freescale/ls2085ardb/MAINTAINERS rename configs/{ls2085a_emu_defconfig => ls2080a_emu_defconfig} (89%) rename configs/{ls2085a_simu_defconfig => ls2080a_simu_defconfig} (89%) rename configs/{ls2085ardb_defconfig => ls2080aqds_defconfig} (73%) rename configs/{ls2085aqds_nand_defconfig => ls2080aqds_nand_defconfig} (75%) rename configs/{ls2085aqds_defconfig => ls2080ardb_defconfig} (73%) rename configs/{ls2085ardb_nand_defconfig => ls2080ardb_nand_defconfig} (75%) rename drivers/net/ldpaa_eth/{ls2085a.c => ls2080a.c} (100%) rename include/configs/{ls2085a_common.h => ls2080a_common.h} (98%) rename include/configs/{ls2085a_emu.h => ls2080a_emu.h} (94%) rename include/configs/{ls2085a_simu.h => ls2080a_simu.h} (96%) rename include/configs/{ls2085aqds.h => ls2080aqds.h} (99%) rename include/configs/{ls2085ardb.h => ls2080ardb.h} (99%) diff --git a/README b/README index c22b60b..c775664 100644 --- a/README +++ b/README @@ -611,6 +611,9 @@ The following options need to be configured: CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS Number of controllers used for other than main memory. + CONFIG_SYS_FSL_HAS_DP_DDR + Defines the SoC has DP-DDR used for DPAA. + CONFIG_SYS_FSL_SEC_BE Defines the SEC controller register space as Big Endian diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3a336e6..05224ed 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -571,36 +571,46 @@ config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select ARM64 -config TARGET_LS2085A_EMU - bool "Support ls2085a_emu" +config TARGET_LS2080A_EMU + bool "Support ls2080a_emu" select ARM64 select ARMV8_MULTIENTRY + help + Support for Freescale LS2080A_EMU platform + The LS2080A Development System (EMULATOR) is a pre silicon + development platform that supports the QorIQ LS2080A + Layerscape Architecture processor. -config TARGET_LS2085A_SIMU - bool "Support ls2085a_simu" +config TARGET_LS2080A_SIMU + bool "Support ls2080a_simu" select ARM64 select ARMV8_MULTIENTRY + help + Support for Freescale LS2080A_SIMU platform + The LS2080A Development System (QDS) is a pre silicon + development platform that supports the QorIQ LS2080A + Layerscape Architecture processor. -config TARGET_LS2085AQDS - bool "Support ls2085aqds" +config TARGET_LS2080AQDS + bool "Support ls2080aqds" select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL help - Support for Freescale LS2085AQDS platform - The LS2085A Development System (QDS) is a high-performance - development platform that supports the QorIQ LS2085A + Support for Freescale LS2080AQDS platform + The LS2080A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS2080A Layerscape Architecture processor. -config TARGET_LS2085ARDB - bool "Support ls2085ardb" +config TARGET_LS2080ARDB + bool "Support ls2080ardb" select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL help - Support for Freescale LS2085ARDB platform. - The LS2085A Reference design board (RDB) is a high-performance - development platform that supports the QorIQ LS2085A + Support for Freescale LS2080ARDB platform. + The LS2080A Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS2080A Layerscape Architecture processor. config TARGET_HIKEY @@ -731,9 +741,9 @@ source "board/compulab/cm_t43/Kconfig" source "board/creative/xfi3/Kconfig" source "board/denx/m28evk/Kconfig" source "board/denx/m53evk/Kconfig" -source "board/freescale/ls2085a/Kconfig" -source "board/freescale/ls2085aqds/Kconfig" -source "board/freescale/ls2085ardb/Kconfig" +source "board/freescale/ls2080a/Kconfig" +source "board/freescale/ls2080aqds/Kconfig" +source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/mx23evk/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile index 9f7815b..2cee7d3 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile +++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile @@ -8,6 +8,6 @@ obj-y += cpu.o obj-y += lowlevel.o obj-y += soc.o obj-y += speed.o -obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2080a_serdes.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 08da7e4..fe400f5 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -7,7 +7,7 @@ Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, -for example LS2085A. +for example LS2080A. DDR Layout ============ @@ -152,7 +152,7 @@ u-boot command nand write <rcw image in memory> 0 <size of rcw image> To form the NAND image, build u-boot with NAND config, for example, -ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. +ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. The u-boot image should be written to match SRC_ADDR, in above example 0x20000. nand write <u-boot image in memory> 200000 <size of u-boot image> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index eb1213e..b219c76 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -25,11 +25,11 @@ DECLARE_GLOBAL_DATA_PTR; static struct cpu_type cpu_type_list[] = { -#ifdef CONFIG_LS2085A - CPU_TYPE_ENTRY(LS2085, LS2085, 8), +#ifdef CONFIG_LS2080A CPU_TYPE_ENTRY(LS2080, LS2080, 8), - CPU_TYPE_ENTRY(LS2045, LS2045, 4), #endif + CPU_TYPE_ENTRY(LS2085, LS2085, 8), + CPU_TYPE_ENTRY(LS2045, LS2045, 4), }; void cpu_name(char *name) @@ -174,7 +174,7 @@ static const struct sys_mmu_table lsch3_final_mmu_table[] = { CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, #endif @@ -551,7 +551,9 @@ int print_cpuinfo(void) printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); +#endif puts("\n"); /* Display the RCW, so that no one gets confused as to what RCW diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index 567c419..6d6dd16 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -130,7 +130,7 @@ void append_mmu_masters(void *blob, const char *smmu_path, /* * The info below summarizes how streamID partitioning works - * for ls2085a and how it is conveyed to the OS via the device tree. + * for ls2080a and how it is conveyed to the OS via the device tree. * * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) * -all legacy devices get a unique ICID assigned and programmed in diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c similarity index 98% rename from arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c rename to arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c index 0b79a50..64da31c 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c @@ -29,7 +29,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII1 } }, {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, - {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, + {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } }, {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c index d9f137c..4cd072b 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c @@ -77,11 +77,15 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_systembus = sysclk; #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; +#endif #else sys_info->freq_ddrbus = sysclk; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR sys_info->freq_ddrbus2 = sysclk; #endif +#endif sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & @@ -91,9 +95,11 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; +#endif for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { /* @@ -133,7 +139,9 @@ int get_clocks(void) gd->cpu_clk = sys_info.freq_processor[0]; gd->bus_clk = sys_info.freq_systembus; gd->mem_clk = sys_info.freq_ddrbus; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR gd->arch.mem2_clk = sys_info.freq_ddrbus2; +#endif #if defined(CONFIG_FSL_ESDHC) gd->arch.sdhc_clk = gd->bus_clk / 2; #endif /* defined(CONFIG_FSL_ESDHC) */ @@ -169,8 +177,10 @@ ulong get_ddr_freq(ulong ctrl_num) * DDR controller 0 & 1 are on memory complex 0 * DDR controler 2 is on memory complext 1 */ +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num >= 2) return gd->arch.mem2_clk; +#endif return gd->mem_clk; } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 65b4230..7c59ae6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -74,8 +74,8 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr.dtb -dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \ - fsl-ls2085a-rdb.dtb +dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-rdb.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/fsl-ls2085a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts similarity index 80% rename from arch/arm/dts/fsl-ls2085a-qds.dts rename to arch/arm/dts/fsl-ls2080a-qds.dts index 4477e54..547ec27 100644 --- a/arch/arm/dts/fsl-ls2085a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -1,5 +1,5 @@ /* - * Freescale ls2085a QDS board device tree source + * Freescale ls2080a QDS board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. * @@ -8,11 +8,11 @@ /dts-v1/; -#include "fsl-ls2085a.dtsi" +#include "fsl-ls2080a.dtsi" / { - model = "Freescale Layerscape 2085a QDS Board"; - compatible = "fsl,ls2085a-qds", "fsl,ls2085a"; + model = "Freescale Layerscape 2080a QDS Board"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; aliases { spi1 = &dspi; diff --git a/arch/arm/dts/fsl-ls2085a-rdb.dts b/arch/arm/dts/fsl-ls2080a-rdb.dts similarity index 67% rename from arch/arm/dts/fsl-ls2085a-rdb.dts rename to arch/arm/dts/fsl-ls2080a-rdb.dts index 25278df..1a1813b 100644 --- a/arch/arm/dts/fsl-ls2085a-rdb.dts +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts @@ -1,5 +1,5 @@ /* - * Freescale ls2085a RDB board device tree source + * Freescale ls2080a RDB board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. * @@ -8,11 +8,11 @@ /dts-v1/; -#include "fsl-ls2085a.dtsi" +#include "fsl-ls2080a.dtsi" / { - model = "Freescale Layerscape 2085a RDB Board"; - compatible = "fsl,ls2085a-rdb", "fsl,ls2085a"; + model = "Freescale Layerscape 2080a RDB Board"; + compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; aliases { spi1 = &dspi; diff --git a/arch/arm/dts/fsl-ls2085a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi similarity index 97% rename from arch/arm/dts/fsl-ls2085a.dtsi rename to arch/arm/dts/fsl-ls2080a.dtsi index 96404c5..a5c579c 100644 --- a/arch/arm/dts/fsl-ls2085a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -1,5 +1,5 @@ /* - * Freescale ls2085a SOC common device tree source + * Freescale ls2080a SOC common device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. * @@ -7,7 +7,7 @@ */ / { - compatible = "fsl,ls2085a"; + compatible = "fsl,ls2080a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 96d6c98..78562ea 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -65,8 +65,8 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) -#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 @@ -163,7 +163,7 @@ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 3 @@ -174,7 +174,7 @@ #error SoC not defined #endif -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A #define CONFIG_SYS_FSL_ERRATUM_A008336 #define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index d6bee60..941f99a 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -15,7 +15,9 @@ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; unsigned long freq_ddrbus; +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR unsigned long freq_ddrbus2; +#endif unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-lsch3/ls2080a_stream_id.h similarity index 93% rename from arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h rename to arch/arm/include/asm/arch-fsl-lsch3/ls2080a_stream_id.h index 5c94530..954104b 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/ls2080a_stream_id.h @@ -7,7 +7,7 @@ #ifndef __FSL_STREAM_ID_H #define __FSL_STREAM_ID_H -/* Stream IDs on ls2085a devices are not hardwired and are +/* Stream IDs on ls2080a devices are not hardwired and are * programmed by sw. There are a limited number of stream IDs * available, and the partitioning of them is scenario dependent. * This header defines the partitioning between legacy, PCI, @@ -17,7 +17,7 @@ * on the specific hardware config-- e.g. perhaps not all * PEX controllers are in use. * - * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for + * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bit streamID bit diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 4e3ea55..bd27281 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -46,7 +46,7 @@ struct arch_global_data { u32 omap_boot_mode; u8 omap_ch_flags; #endif -#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) unsigned long mem2_clk; #endif }; diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2080a/Kconfig similarity index 66% rename from board/freescale/ls2085a/Kconfig rename to board/freescale/ls2080a/Kconfig index f51afc8..942cce2 100644 --- a/board/freescale/ls2085a/Kconfig +++ b/board/freescale/ls2080a/Kconfig @@ -1,7 +1,7 @@ -if TARGET_LS2085A_EMU +if TARGET_LS2080A_EMU config SYS_BOARD - default "ls2085a" + default "ls2080a" config SYS_VENDOR default "freescale" @@ -10,14 +10,14 @@ config SYS_SOC default "fsl-lsch3" config SYS_CONFIG_NAME - default "ls2085a_emu" + default "ls2080a_emu" endif -if TARGET_LS2085A_SIMU +if TARGET_LS2080A_SIMU config SYS_BOARD - default "ls2085a" + default "ls2080a" config SYS_VENDOR default "freescale" @@ -26,6 +26,6 @@ config SYS_SOC default "fsl-lsch3" config SYS_CONFIG_NAME - default "ls2085a_simu" + default "ls2080a_simu" endif diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS new file mode 100644 index 0000000..bb25084 --- /dev/null +++ b/board/freescale/ls2080a/MAINTAINERS @@ -0,0 +1,8 @@ +LS2080A BOARD +M: York Sun <yorksun(a)freescale.com> +S: Maintained +F: board/freescale/ls2080a/ +F: include/configs/ls2080a_emu.h +F: configs/ls2080a_emu_defconfig +F: include/configs/ls2080a_simu.h +F: configs/ls2080a_simu_defconfig diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2080a/Makefile similarity index 83% rename from board/freescale/ls2085a/Makefile rename to board/freescale/ls2080a/Makefile index 701b35c..6038626 100644 --- a/board/freescale/ls2085a/Makefile +++ b/board/freescale/ls2080a/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls2085a.o +obj-y += ls2080a.o obj-y += ddr.o diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2080a/README similarity index 97% rename from board/freescale/ls2085a/README rename to board/freescale/ls2080a/README index bc1d0bb..7e53f1f 100644 --- a/board/freescale/ls2085a/README +++ b/board/freescale/ls2080a/README @@ -1,4 +1,4 @@ -Freescale ls2085a_emu +Freescale ls2080a_emu This is a emulator target with limited peripherals. diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2080a/ddr.c similarity index 99% rename from board/freescale/ls2085a/ddr.c rename to board/freescale/ls2080a/ddr.c index 4884fa2..47d73ef 100644 --- a/board/freescale/ls2085a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -71,7 +71,7 @@ found: pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num == CONFIG_DP_DDR_CTRL) { /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; @@ -79,6 +79,7 @@ found: popts->burst_length = DDR_BL8; popts->bstopre = 0; /* enable auto precharge */ } +#endif /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2080a/ddr.h similarity index 100% rename from board/freescale/ls2085a/ddr.h rename to board/freescale/ls2080a/ddr.h diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2080a/ls2080a.c similarity index 98% rename from board/freescale/ls2085a/ls2085a.c rename to board/freescale/ls2080a/ls2080a.c index 73c4410..b285fef 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -35,7 +35,7 @@ int board_early_init_f(void) fsl_lsch3_early_init_f(); return 0; } - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR void detail_board_ddr_info(void) { puts("\nDDR "); @@ -47,7 +47,7 @@ void detail_board_ddr_info(void) print_ddr_info(CONFIG_DP_DDR_CTRL); } } - +#endif int dram_init(void) { gd->ram_size = initdram(0); diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig similarity index 66% rename from board/freescale/ls2085aqds/Kconfig rename to board/freescale/ls2080aqds/Kconfig index deb640d..7b89f95 100644 --- a/board/freescale/ls2085aqds/Kconfig +++ b/board/freescale/ls2080aqds/Kconfig @@ -1,8 +1,8 @@ -if TARGET_LS2085AQDS +if TARGET_LS2080AQDS config SYS_BOARD - default "ls2085aqds" + default "ls2080aqds" config SYS_VENDOR default "freescale" @@ -11,6 +11,6 @@ config SYS_SOC default "fsl-lsch3" config SYS_CONFIG_NAME - default "ls2085aqds" + default "ls2080aqds" endif diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS new file mode 100644 index 0000000..3d82482 --- /dev/null +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -0,0 +1,8 @@ +LS2080A BOARD +M: Prabhakar Kushwaha <prabhakar(a)freescale.com> +S: Maintained +F: board/freescale/ls2080aqds/ +F: board/freescale/ls2080a/ls2080aqds.c +F: include/configs/ls2080aqds.h +F: configs/ls2080aqds_defconfig +F: configs/ls2080aqds_nand_defconfig diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2080aqds/Makefile similarity index 83% rename from board/freescale/ls2085aqds/Makefile rename to board/freescale/ls2080aqds/Makefile index da69a7d..e0da8a5 100644 --- a/board/freescale/ls2085aqds/Makefile +++ b/board/freescale/ls2080aqds/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls2085aqds.o +obj-y += ls2080aqds.o obj-y += ddr.o obj-y += eth.o diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2080aqds/README similarity index 95% rename from board/freescale/ls2085aqds/README rename to board/freescale/ls2080aqds/README index e4a6f69..a4abb7e 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2080aqds/README @@ -1,19 +1,19 @@ Overview -------- -The LS2085A Development System (QDS) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2085A -Layerscape Architecture processor. The LS2085AQDS provides validation and -SW development platform for the Freescale LS2085A processor series, with +The LS2080A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2080A +Layerscape Architecture processor. The LS2080AQDS provides validation and +SW development platform for the Freescale LS2080A processor series, with a complete debugging environment. -LS2085A SoC Overview +LS2080A SoC Overview ------------------ -The LS2085A integrated multicore processor combines eight ARM Cortex-A57 +The LS2080A integrated multicore processor combines eight ARM Cortex-A57 processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. -The LS2085A SoC includes the following function and features: +The LS2080A SoC includes the following function and features: - Eight 64-bit ARM Cortex-A57 CPUs - 1 MB platform cache with ECC @@ -50,7 +50,7 @@ The LS2085A SoC includes the following function and features: - Service processor (SP) provides pre-boot initialization and secure-boot capabilities - LS2085AQDS board Overview + LS2080AQDS board Overview ----------------------- - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c similarity index 98% rename from board/freescale/ls2085aqds/ddr.c rename to board/freescale/ls2080aqds/ddr.c index 8d71ae1..ae681de 100644 --- a/board/freescale/ls2085aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; +#endif const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; int slot; @@ -79,7 +81,7 @@ found: pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num == CONFIG_DP_DDR_CTRL) { /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; @@ -114,6 +116,7 @@ found: pdimm[slot].dq_mapping[16] = 0; pdimm[slot].dq_mapping[17] = 0; } +#endif /* To work at higher than 1333MT/s */ popts->half_strength_driver_enable = 0; /* diff --git a/board/freescale/ls2085aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h similarity index 100% rename from board/freescale/ls2085aqds/ddr.h rename to board/freescale/ls2080aqds/ddr.h diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2080aqds/eth.c similarity index 88% rename from board/freescale/ls2085aqds/eth.c rename to board/freescale/ls2080aqds/eth.c index 007b433..e95096d 100644 --- a/board/freescale/ls2085aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -19,16 +19,16 @@ #include "../common/qixis.h" -#include "ls2085aqds_qixis.h" +#include "ls2080aqds_qixis.h" #ifdef CONFIG_FSL_MC_ENET - /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks. + /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. * Bank 1 -> Lanes A, B, C, D, E, F, G, H * Bank 2 -> Lanes A,B, C, D, E, F, G, H */ - /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here + /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here * means that the mapping must be determined dynamically, or that the lane * maps to something other than a board slot. */ @@ -75,16 +75,16 @@ static int sgmii_riser_phy_addr[] = { #define SFP_TX 0 static const char * const mdio_names[] = { - "LS2085A_QDS_MDIO0", - "LS2085A_QDS_MDIO1", - "LS2085A_QDS_MDIO2", - "LS2085A_QDS_MDIO3", - "LS2085A_QDS_MDIO4", - "LS2085A_QDS_MDIO5", + "LS2080A_QDS_MDIO0", + "LS2080A_QDS_MDIO1", + "LS2080A_QDS_MDIO2", + "LS2080A_QDS_MDIO3", + "LS2080A_QDS_MDIO4", + "LS2080A_QDS_MDIO5", DEFAULT_WRIOP_MDIO2_NAME, }; -struct ls2085a_qds_mdio { +struct ls2080a_qds_mdio { u8 muxval; struct mii_dev *realbus; }; @@ -96,7 +96,7 @@ static void sgmii_configure_repeater(int serdes_port) int i, j, ret; int dpmac_id = 0, dpmac, mii_bus = 0; unsigned short value; - char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"}; + char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"}; uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60}; uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; @@ -223,7 +223,7 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; - const char *dev = "LS2085A_QDS_MDIO0"; + const char *dev = "LS2080A_QDS_MDIO0"; int ret = 0; unsigned short value; @@ -319,7 +319,7 @@ error: return; } -static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval) +static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval) { return mdio_names[muxval]; } @@ -327,7 +327,7 @@ static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval) struct mii_dev *mii_dev_for_muxval(u8 muxval) { struct mii_dev *bus; - const char *name = ls2085a_qds_mdio_name_for_muxval(muxval); + const char *name = ls2080a_qds_mdio_name_for_muxval(muxval); if (!name) { printf("No bus for muxval %x\n", muxval); @@ -344,7 +344,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval) return bus; } -static void ls2085a_qds_enable_SFP_TX(u8 muxval) +static void ls2080a_qds_enable_SFP_TX(u8 muxval) { u8 brdcfg9; @@ -354,7 +354,7 @@ static void ls2085a_qds_enable_SFP_TX(u8 muxval) QIXIS_WRITE(brdcfg[9], brdcfg9); } -static void ls2085a_qds_mux_mdio(u8 muxval) +static void ls2080a_qds_mux_mdio(u8 muxval) { u8 brdcfg4; @@ -366,54 +366,54 @@ static void ls2085a_qds_mux_mdio(u8 muxval) } } -static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr, +static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr, int devad, int regnum) { - struct ls2085a_qds_mdio *priv = bus->priv; + struct ls2080a_qds_mdio *priv = bus->priv; - ls2085a_qds_mux_mdio(priv->muxval); + ls2080a_qds_mux_mdio(priv->muxval); return priv->realbus->read(priv->realbus, addr, devad, regnum); } -static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, +static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, int regnum, u16 value) { - struct ls2085a_qds_mdio *priv = bus->priv; + struct ls2080a_qds_mdio *priv = bus->priv; - ls2085a_qds_mux_mdio(priv->muxval); + ls2080a_qds_mux_mdio(priv->muxval); return priv->realbus->write(priv->realbus, addr, devad, regnum, value); } -static int ls2085a_qds_mdio_reset(struct mii_dev *bus) +static int ls2080a_qds_mdio_reset(struct mii_dev *bus) { - struct ls2085a_qds_mdio *priv = bus->priv; + struct ls2080a_qds_mdio *priv = bus->priv; return priv->realbus->reset(priv->realbus); } -static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval) +static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval) { - struct ls2085a_qds_mdio *pmdio; + struct ls2080a_qds_mdio *pmdio; struct mii_dev *bus = mdio_alloc(); if (!bus) { - printf("Failed to allocate ls2085a_qds MDIO bus\n"); + printf("Failed to allocate ls2080a_qds MDIO bus\n"); return -1; } pmdio = malloc(sizeof(*pmdio)); if (!pmdio) { - printf("Failed to allocate ls2085a_qds private data\n"); + printf("Failed to allocate ls2080a_qds private data\n"); free(bus); return -1; } - bus->read = ls2085a_qds_mdio_read; - bus->write = ls2085a_qds_mdio_write; - bus->reset = ls2085a_qds_mdio_reset; - sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval)); + bus->read = ls2080a_qds_mdio_read; + bus->write = ls2080a_qds_mdio_write; + bus->reset = ls2080a_qds_mdio_reset; + sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); @@ -512,7 +512,7 @@ static void initialize_dpmac_to_slot(void) } } -void ls2085a_handle_phy_interface_sgmii(int dpmac_id) +void ls2080a_handle_phy_interface_sgmii(int dpmac_id) { int lane, slot; struct mii_dev *bus; @@ -633,7 +633,7 @@ serdes2: } } -void ls2085a_handle_phy_interface_qsgmii(int dpmac_id) +void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) { int lane = 0, slot; struct mii_dev *bus; @@ -707,7 +707,7 @@ void ls2085a_handle_phy_interface_qsgmii(int dpmac_id) qsgmii_configure_repeater(dpmac_id); } -void ls2085a_handle_phy_interface_xsgmii(int i) +void ls2080a_handle_phy_interface_xsgmii(int i) { struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & @@ -726,7 +726,7 @@ void ls2085a_handle_phy_interface_xsgmii(int i) * error. */ wriop_set_phy_address(i, i + 4); - ls2085a_qds_enable_SFP_TX(SFP_TX); + ls2080a_qds_enable_SFP_TX(SFP_TX); break; default: @@ -779,25 +779,25 @@ int board_eth_init(bd_t *bis) fm_memac_mdio_init(bis, memac_mdio1_info); /* Register the muxing front-ends to the MDIO buses */ - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6); - ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2); + ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2); for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { switch (wriop_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: - ls2085a_handle_phy_interface_qsgmii(i); + ls2080a_handle_phy_interface_qsgmii(i); break; case PHY_INTERFACE_MODE_SGMII: - ls2085a_handle_phy_interface_sgmii(i); + ls2080a_handle_phy_interface_sgmii(i); break; case PHY_INTERFACE_MODE_XGMII: - ls2085a_handle_phy_interface_xsgmii(i); + ls2080a_handle_phy_interface_xsgmii(i); break; default: break; diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c similarity index 98% rename from board/freescale/ls2085aqds/ls2085aqds.c rename to board/freescale/ls2080aqds/ls2080aqds.c index 2315bdb..8f114a5 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -21,7 +21,7 @@ #include <hwconfig.h> #include "../common/qixis.h" -#include "ls2085aqds_qixis.h" +#include "ls2080aqds_qixis.h" #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -220,7 +220,7 @@ int board_early_init_f(void) fsl_lsch3_early_init_f(); return 0; } - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR void detail_board_ddr_info(void) { puts("\nDDR "); @@ -232,7 +232,7 @@ void detail_board_ddr_info(void) print_ddr_info(CONFIG_DP_DDR_CTRL); } } - +#endif int dram_init(void) { gd->ram_size = initdram(0); diff --git a/board/freescale/ls2085aqds/ls2085aqds_qixis.h b/board/freescale/ls2080aqds/ls2080aqds_qixis.h similarity index 100% rename from board/freescale/ls2085aqds/ls2085aqds_qixis.h rename to board/freescale/ls2080aqds/ls2080aqds_qixis.h diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig similarity index 66% rename from board/freescale/ls2085ardb/Kconfig rename to board/freescale/ls2080ardb/Kconfig index 85a3dcd..55aa468 100644 --- a/board/freescale/ls2085ardb/Kconfig +++ b/board/freescale/ls2080ardb/Kconfig @@ -1,8 +1,8 @@ -if TARGET_LS2085ARDB +if TARGET_LS2080ARDB config SYS_BOARD - default "ls2085ardb" + default "ls2080ardb" config SYS_VENDOR default "freescale" @@ -11,6 +11,6 @@ config SYS_SOC default "fsl-lsch3" config SYS_CONFIG_NAME - default "ls2085ardb" + default "ls2080ardb" endif diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS new file mode 100644 index 0000000..aac8110 --- /dev/null +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -0,0 +1,8 @@ +LS2080A BOARD +M: Prabhakar Kushwaha <prabhakar(a)freescale.com> +S: Maintained +F: board/freescale/ls2080ardb/ +F: board/freescale/ls2080a/ls2080ardb.c +F: include/configs/ls2080ardb.h +F: configs/ls2080ardb_defconfig +F: configs/ls2080ardb_nand_defconfig diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2080ardb/Makefile similarity index 72% rename from board/freescale/ls2085ardb/Makefile rename to board/freescale/ls2080ardb/Makefile index de383cc..6a52167 100644 --- a/board/freescale/ls2085ardb/Makefile +++ b/board/freescale/ls2080ardb/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls2085ardb.o eth_ls2085rdb.o +obj-y += ls2080ardb.o eth_ls2080rdb.o obj-y += ddr.o diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2080ardb/README similarity index 94% rename from board/freescale/ls2085ardb/README rename to board/freescale/ls2080ardb/README index 2f18243..7fc2569 100644 --- a/board/freescale/ls2085ardb/README +++ b/board/freescale/ls2080ardb/README @@ -1,17 +1,17 @@ Overview -------- -The LS2085A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2085A +The LS2080A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2080A Layerscape Architecture processor. -LS2085A SoC Overview +LS2080A SoC Overview ------------------ -The LS2085A integrated multicore processor combines eight ARM Cortex-A57 +The LS2080A integrated multicore processor combines eight ARM Cortex-A57 processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. -The LS2085A SoC includes the following function and features: +The LS2080A SoC includes the following function and features: - Eight 64-bit ARM Cortex-A57 CPUs - 1 MB platform cache with ECC @@ -48,7 +48,7 @@ The LS2085A SoC includes the following function and features: - Service processor (SP) provides pre-boot initialization and secure-boot capabilities - LS2085ARDB board Overview + LS2080ARDB board Overview ----------------------- - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c similarity index 98% rename from board/freescale/ls2085ardb/ddr.c rename to board/freescale/ls2080ardb/ddr.c index 8d71ae1..ae681de 100644 --- a/board/freescale/ls2085ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; +#endif const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; int slot; @@ -79,7 +81,7 @@ found: pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num == CONFIG_DP_DDR_CTRL) { /* force DDR bus width to 32 bits */ popts->data_bus_width = 1; @@ -114,6 +116,7 @@ found: pdimm[slot].dq_mapping[16] = 0; pdimm[slot].dq_mapping[17] = 0; } +#endif /* To work at higher than 1333MT/s */ popts->half_strength_driver_enable = 0; /* diff --git a/board/freescale/ls2085ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h similarity index 100% rename from board/freescale/ls2085ardb/ddr.h rename to board/freescale/ls2080ardb/ddr.h diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c similarity index 98% rename from board/freescale/ls2085ardb/eth_ls2085rdb.c rename to board/freescale/ls2080ardb/eth_ls2080rdb.c index 0a1163a..dfa0800 100644 --- a/board/freescale/ls2085ardb/eth_ls2085rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -98,7 +98,7 @@ int board_eth_init(bd_t *bis) break; default: - printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n", + printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n", srds_s1); break; } diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c similarity index 98% rename from board/freescale/ls2085ardb/ls2085ardb.c rename to board/freescale/ls2080ardb/ls2080ardb.c index 5e7997c..5451b2e 100644 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -20,7 +20,7 @@ #include <asm/arch-fsl-lsch3/soc.h> #include "../common/qixis.h" -#include "ls2085ardb_qixis.h" +#include "ls2080ardb_qixis.h" #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -186,7 +186,7 @@ int misc_init_r(void) return 0; } - +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR void detail_board_ddr_info(void) { puts("\nDDR "); @@ -198,7 +198,7 @@ void detail_board_ddr_info(void) print_ddr_info(CONFIG_DP_DDR_CTRL); } } - +#endif int dram_init(void) { gd->ram_size = initdram(0); diff --git a/board/freescale/ls2085ardb/ls2085ardb_qixis.h b/board/freescale/ls2080ardb/ls2080ardb_qixis.h similarity index 100% rename from board/freescale/ls2085ardb/ls2085ardb_qixis.h rename to board/freescale/ls2080ardb/ls2080ardb_qixis.h diff --git a/board/freescale/ls2085a/MAINTAINERS b/board/freescale/ls2085a/MAINTAINERS deleted file mode 100644 index 90b4e47..0000000 --- a/board/freescale/ls2085a/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: York Sun <yorksun(a)freescale.com> -S: Maintained -F: board/freescale/ls2085a/ -F: include/configs/ls2085a_emu.h -F: configs/ls2085a_emu_defconfig -F: include/configs/ls2085a_simu.h -F: configs/ls2085a_simu_defconfig diff --git a/board/freescale/ls2085aqds/MAINTAINERS b/board/freescale/ls2085aqds/MAINTAINERS deleted file mode 100644 index fbed672..0000000 --- a/board/freescale/ls2085aqds/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: Prabhakar Kushwaha <prabhakar(a)freescale.com> -S: Maintained -F: board/freescale/ls2085aqds/ -F: board/freescale/ls2085a/ls2085aqds.c -F: include/configs/ls2085aqds.h -F: configs/ls2085aqds_defconfig -F: configs/ls2085aqds_nand_defconfig diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS deleted file mode 100644 index d5cce40..0000000 --- a/board/freescale/ls2085ardb/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS2085A BOARD -M: Prabhakar Kushwaha <prabhakar(a)freescale.com> -S: Maintained -F: board/freescale/ls2085ardb/ -F: board/freescale/ls2085a/ls2085ardb.c -F: include/configs/ls2085ardb.h -F: configs/ls2085ardb_defconfig -F: configs/ls2085ardb_nand_defconfig diff --git a/configs/ls2085a_emu_defconfig b/configs/ls2080a_emu_defconfig similarity index 89% rename from configs/ls2085a_emu_defconfig rename to configs/ls2080a_emu_defconfig index 9c82e17..7fda0f9 100644 --- a/configs/ls2085a_emu_defconfig +++ b/configs/ls2080a_emu_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085A_EMU=y +CONFIG_TARGET_LS2080A_EMU=y CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" +CONFIG_LS2080A=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/ls2085a_simu_defconfig b/configs/ls2080a_simu_defconfig similarity index 89% rename from configs/ls2085a_simu_defconfig rename to configs/ls2080a_simu_defconfig index de9776d..777e866 100644 --- a/configs/ls2085a_simu_defconfig +++ b/configs/ls2080a_simu_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085A_SIMU=y +CONFIG_TARGET_LS2080A_SIMU=y CONFIG_SYS_EXTRA_OPTIONS="SIMU" +CONFIG_LS2080A=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/ls2085ardb_defconfig b/configs/ls2080aqds_defconfig similarity index 73% rename from configs/ls2085ardb_defconfig rename to configs/ls2080aqds_defconfig index 7956533..5b9143a 100644 --- a/configs/ls2085ardb_defconfig +++ b/configs/ls2080aqds_defconfig @@ -1,9 +1,10 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085ARDB=y +CONFIG_TARGET_LS2080AQDS=y # CONFIG_SYS_MALLOC_F is not set +CONFIG_LS2080A=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig similarity index 75% rename from configs/ls2085aqds_nand_defconfig rename to configs/ls2080aqds_nand_defconfig index 10eda97..21cefe1 100644 --- a/configs/ls2085aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085AQDS=y +CONFIG_TARGET_LS2080AQDS=y CONFIG_SPL=y +CONFIG_LS2080A=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y diff --git a/configs/ls2085aqds_defconfig b/configs/ls2080ardb_defconfig similarity index 73% rename from configs/ls2085aqds_defconfig rename to configs/ls2080ardb_defconfig index 0c770e4..8ba93b8 100644 --- a/configs/ls2085aqds_defconfig +++ b/configs/ls2080ardb_defconfig @@ -1,9 +1,10 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085AQDS=y +CONFIG_TARGET_LS2080ARDB=y # CONFIG_SYS_MALLOC_F is not set CONFIG_DM_SPI=y +CONFIG_LS2080A=y CONFIG_DM_SPI_FLASH=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb" CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig similarity index 75% rename from configs/ls2085ardb_nand_defconfig rename to configs/ls2080ardb_nand_defconfig index 96a0dfd..90d306e 100644 --- a/configs/ls2085ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -1,7 +1,8 @@ CONFIG_ARM=y -CONFIG_TARGET_LS2085ARDB=y +CONFIG_TARGET_LS2080ARDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" +CONFIG_LS2080A=y # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_E1000=y diff --git a/doc/README.fsl-trustzone-components b/doc/README.fsl-trustzone-components index a3afd1f..e122346 100644 --- a/doc/README.fsl-trustzone-components +++ b/doc/README.fsl-trustzone-components @@ -1,4 +1,4 @@ -Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like +Freescale ARM64 SoCs like LS2080A have ARM TrustZone components like TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone Address Space Controller). @@ -7,7 +7,7 @@ is left to a root-of-trust security software layer (running in EL3 privilege mode), but still some configurations of these peripherals might be required while the bootloader is executing in EL3 privilege mode. The following sections define how to turn on these features for -LS2085A like SoCs. +LS2080A like SoCs. TZPC-BP147 (TrustZone Protection Controller) ============================================ diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 49e4688..eefe709 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -107,14 +107,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, goto step2; #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A /* A008336 only applies to general DDR controllers */ if ((ctrl_num == 0) || (ctrl_num == 1)) #endif ddr_out32(eddrtqcr1, 0x63b30002); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A /* A008514 only applies to DP-DDR controler */ if (ctrl_num == 2) #endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0b37002..c1cd377 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -106,7 +106,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) xfertyp |= XFERTYP_RSPTYP_48; #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) + defined(CONFIG_LS102XA) || defined(CONFIG_LS2080A) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif @@ -184,7 +184,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) int timeout; struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A dma_addr_t addr; #endif uint wml_value; @@ -197,7 +197,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A addr = virt_to_phys((void *)(data->dest)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -223,7 +223,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK, wml_value << 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A addr = virt_to_phys((void *)(data->src)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -277,7 +277,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) static void check_and_invalidate_dcache_range (struct mmc_cmd *cmd, struct mmc_data *data) { -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A unsigned start = 0; #else unsigned start = (unsigned)data->dest ; @@ -285,7 +285,7 @@ static void check_and_invalidate_dcache_range unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); unsigned end = start+size ; -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A dma_addr_t addr; addr = virt_to_phys((void *)(data->dest)); diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index c37633f..5587aa6 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -6,4 +6,4 @@ obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o -obj-$(CONFIG_LS2085A) += ls2085a.o +obj-$(CONFIG_LS2080A) += ls2080a.o diff --git a/drivers/net/ldpaa_eth/ls2085a.c b/drivers/net/ldpaa_eth/ls2080a.c similarity index 100% rename from drivers/net/ldpaa_eth/ls2085a.c rename to drivers/net/ldpaa_eth/ls2080a.c diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 2f24a6a..a24e36f 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -663,7 +663,7 @@ void ft_pci_setup(void *blob, bd_t *bd) } #endif -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A void pcie_set_available_streamids(void *blob, const char *pcie_path, u32 *stream_ids, int count) diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2080a_common.h similarity index 98% rename from include/configs/ls2085a_common.h rename to include/configs/ls2080a_common.h index 55b909c..cf37729 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2080a_common.h @@ -11,7 +11,6 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LSCH3 -#define CONFIG_LS2085A #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 @@ -19,7 +18,7 @@ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 -#include <asm/arch-fsl-lsch3/ls2085a_stream_id.h> +#include <asm/arch-fsl-lsch3/ls2080a_stream_id.h> #include <asm/arch-fsl-lsch3/config.h> #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) #define CONFIG_SYS_HAS_SERDES @@ -74,6 +73,7 @@ #define CPU_RELEASE_ADDR secondary_boot_func #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL /* * DDR controller use 0 as the base address for binding. @@ -82,6 +82,7 @@ #define CONFIG_SYS_DP_DDR_BASE_PHY 0 #define CONFIG_DP_DDR_CTRL 2 #define CONFIG_DP_DDR_NUM_CTRLS 1 +#endif /* Generic Timer Definitions */ /* @@ -199,7 +200,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ -#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" +#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" #define CONFIG_SYS_PCI_64BIT diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2080a_emu.h similarity index 94% rename from include/configs/ls2085a_emu.h rename to include/configs/ls2080a_emu.h index 2d68e1b..6400f4f 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -7,10 +7,10 @@ #ifndef __LS2_EMU_H #define __LS2_EMU_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" -#define CONFIG_IDENT_STRING " LS2085A-EMU" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" +#define CONFIG_IDENT_STRING " LS2080A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU" #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 @@ -27,7 +27,9 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif #define CONFIG_FSL_DDR_SYNC_REFRESH diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2080a_simu.h similarity index 96% rename from include/configs/ls2085a_simu.h rename to include/configs/ls2080a_simu.h index bd15b3d..666df80 100644 --- a/include/configs/ls2085a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -7,10 +7,10 @@ #ifndef __LS2_SIMU_H #define __LS2_SIMU_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" -#define CONFIG_IDENT_STRING " LS2085A-SIMU" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" +#define CONFIG_IDENT_STRING " LS2080A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU" #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 @@ -20,7 +20,9 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif /* SMSC 91C111 ethernet configuration */ #define CONFIG_SMC91111 diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2080aqds.h similarity index 99% rename from include/configs/ls2085aqds.h rename to include/configs/ls2080aqds.h index f7f3870..90f907c 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2080aqds.h @@ -7,7 +7,7 @@ #ifndef __LS2_QDS_H #define __LS2_QDS_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" #define CONFIG_DISPLAY_BOARDINFO @@ -34,7 +34,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2080ardb.h similarity index 99% rename from include/configs/ls2085ardb.h rename to include/configs/ls2080ardb.h index a190bc7..1c6b8dc 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2080ardb.h @@ -7,7 +7,7 @@ #ifndef __LS2_RDB_H #define __LS2_RDB_H -#include "ls2085a_common.h" +#include "ls2080a_common.h" #undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 2 @@ -36,7 +36,9 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 +#endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 0d00b7d..ec5625d 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -166,7 +166,7 @@ #define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */ struct fsl_esdhc_cfg { -#ifdef CONFIG_LS2085A +#ifdef CONFIG_LS2080A u64 esdhc_base; #else u32 esdhc_base; diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 602a413..80b7718 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -54,9 +54,9 @@ struct fsl_xhci { #if defined(CONFIG_LS102XA) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 -#elif defined(CONFIG_LS2085A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR +#elif defined(CONFIG_LS2080A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR #endif #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ -- 1.9.1

3 5

[U-Boot] __kernel_size_t vs size_t which to use
by Tyler 03 Nov '15

03 Nov '15

hey folks, busy list! Quick question. I'm trying to build on ! linux and I'm just wondering about the consistency of use of __kernel_size_t vs size_t use in the code base what is 'correct'? I end up with the a little bit of fallout when I build. CC arch/arm/cpu/armv7/am33xx/board.o In file included from ../include/linux/compat.h:4:0, from ../include/dm/device.h:17, from ../include/dm.h:10, from ../arch/arm/cpu/armv7/am33xx/board.c:12: ../include/malloc.h:364:7: error: conflicting types for 'memset' void* memset(void*, int, size_t); ^ In file included from ../include/common.h:22:0, from ../arch/arm/cpu/armv7/am33xx/board.c:11: ../include/linux/string.h:78:15: note: previous declaration of 'memset' was here extern void * memset(void *,int,__kernel_size_t); Quick examination shows we probably want to change the prototype in include/malloc.h to be __kernel_size_t since the various machines posix_types.h appear to be defining the correct width type to that definition (most of the time anyway). Is this the right thing to do? Thanks!

1 0

[U-Boot] [PATCH v4 01/16] include: Add log2 header from the kernel
by Fabio Estevam 03 Nov '15

03 Nov '15

Use the log2 header files from the kernel. Imported from kernel 4.2.3. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> Reviewed-by: Tom Rini <trini(a)konsulko.com> Reviewed-by: Heiko Schocher <hs(a)denx.de> --- Changes since v3: - None include/linux/log2.h | 205 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 include/linux/log2.h diff --git a/include/linux/log2.h b/include/linux/log2.h new file mode 100644 index 0000000..aa1de63 --- /dev/null +++ b/include/linux/log2.h @@ -0,0 +1,205 @@ +/* Integer base 2 logarithm calculation + * + * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells(a)redhat.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _LINUX_LOG2_H +#define _LINUX_LOG2_H + +#include <linux/types.h> +#include <linux/bitops.h> + +/* + * deal with unrepresentable constant logarithms + */ +extern __attribute__((const, noreturn)) +int ____ilog2_NaN(void); + +/* + * non-constant log of base 2 calculators + * - the arch may override these in asm/bitops.h if they can be implemented + * more efficiently than using fls() and fls64() + * - the arch is not required to handle n==0 if implementing the fallback + */ +#ifndef CONFIG_ARCH_HAS_ILOG2_U32 +static inline __attribute__((const)) +int __ilog2_u32(u32 n) +{ + return fls(n) - 1; +} +#endif + +#ifndef CONFIG_ARCH_HAS_ILOG2_U64 +static inline __attribute__((const)) +int __ilog2_u64(u64 n) +{ + return fls64(n) - 1; +} +#endif + +/* + * Determine whether some value is a power of two, where zero is + * *not* considered a power of two. + */ + +static inline __attribute__((const)) +bool is_power_of_2(unsigned long n) +{ + return (n != 0 && ((n & (n - 1)) == 0)); +} + +/* + * round up to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __roundup_pow_of_two(unsigned long n) +{ + return 1UL << fls_long(n - 1); +} + +/* + * round down to nearest power of two + */ +static inline __attribute__((const)) +unsigned long __rounddown_pow_of_two(unsigned long n) +{ + return 1UL << (fls_long(n) - 1); +} + +/** + * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value + * @n - parameter + * + * constant-capable log of base 2 calculation + * - this can be used to initialise global variables from constant data, hence + * the massive ternary operator construction + * + * selects the appropriately-sized optimised version depending on sizeof(n) + */ +#define ilog2(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n) < 1 ? ____ilog2_NaN() : \ + (n) & (1ULL << 63) ? 63 : \ + (n) & (1ULL << 62) ? 62 : \ + (n) & (1ULL << 61) ? 61 : \ + (n) & (1ULL << 60) ? 60 : \ + (n) & (1ULL << 59) ? 59 : \ + (n) & (1ULL << 58) ? 58 : \ + (n) & (1ULL << 57) ? 57 : \ + (n) & (1ULL << 56) ? 56 : \ + (n) & (1ULL << 55) ? 55 : \ + (n) & (1ULL << 54) ? 54 : \ + (n) & (1ULL << 53) ? 53 : \ + (n) & (1ULL << 52) ? 52 : \ + (n) & (1ULL << 51) ? 51 : \ + (n) & (1ULL << 50) ? 50 : \ + (n) & (1ULL << 49) ? 49 : \ + (n) & (1ULL << 48) ? 48 : \ + (n) & (1ULL << 47) ? 47 : \ + (n) & (1ULL << 46) ? 46 : \ + (n) & (1ULL << 45) ? 45 : \ + (n) & (1ULL << 44) ? 44 : \ + (n) & (1ULL << 43) ? 43 : \ + (n) & (1ULL << 42) ? 42 : \ + (n) & (1ULL << 41) ? 41 : \ + (n) & (1ULL << 40) ? 40 : \ + (n) & (1ULL << 39) ? 39 : \ + (n) & (1ULL << 38) ? 38 : \ + (n) & (1ULL << 37) ? 37 : \ + (n) & (1ULL << 36) ? 36 : \ + (n) & (1ULL << 35) ? 35 : \ + (n) & (1ULL << 34) ? 34 : \ + (n) & (1ULL << 33) ? 33 : \ + (n) & (1ULL << 32) ? 32 : \ + (n) & (1ULL << 31) ? 31 : \ + (n) & (1ULL << 30) ? 30 : \ + (n) & (1ULL << 29) ? 29 : \ + (n) & (1ULL << 28) ? 28 : \ + (n) & (1ULL << 27) ? 27 : \ + (n) & (1ULL << 26) ? 26 : \ + (n) & (1ULL << 25) ? 25 : \ + (n) & (1ULL << 24) ? 24 : \ + (n) & (1ULL << 23) ? 23 : \ + (n) & (1ULL << 22) ? 22 : \ + (n) & (1ULL << 21) ? 21 : \ + (n) & (1ULL << 20) ? 20 : \ + (n) & (1ULL << 19) ? 19 : \ + (n) & (1ULL << 18) ? 18 : \ + (n) & (1ULL << 17) ? 17 : \ + (n) & (1ULL << 16) ? 16 : \ + (n) & (1ULL << 15) ? 15 : \ + (n) & (1ULL << 14) ? 14 : \ + (n) & (1ULL << 13) ? 13 : \ + (n) & (1ULL << 12) ? 12 : \ + (n) & (1ULL << 11) ? 11 : \ + (n) & (1ULL << 10) ? 10 : \ + (n) & (1ULL << 9) ? 9 : \ + (n) & (1ULL << 8) ? 8 : \ + (n) & (1ULL << 7) ? 7 : \ + (n) & (1ULL << 6) ? 6 : \ + (n) & (1ULL << 5) ? 5 : \ + (n) & (1ULL << 4) ? 4 : \ + (n) & (1ULL << 3) ? 3 : \ + (n) & (1ULL << 2) ? 2 : \ + (n) & (1ULL << 1) ? 1 : \ + (n) & (1ULL << 0) ? 0 : \ + ____ilog2_NaN() \ + ) : \ + (sizeof(n) <= 4) ? \ + __ilog2_u32(n) : \ + __ilog2_u64(n) \ + ) + +/** + * roundup_pow_of_two - round the given value up to nearest power of two + * @n - parameter + * + * round the given value up to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define roundup_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (n == 1) ? 1 : \ + (1UL << (ilog2((n) - 1) + 1)) \ + ) : \ + __roundup_pow_of_two(n) \ + ) + +/** + * rounddown_pow_of_two - round the given value down to nearest power of two + * @n - parameter + * + * round the given value down to the nearest power of two + * - the result is undefined when n == 0 + * - this can be used to initialise global variables from constant data + */ +#define rounddown_pow_of_two(n) \ +( \ + __builtin_constant_p(n) ? ( \ + (1UL << ilog2(n))) : \ + __rounddown_pow_of_two(n) \ + ) + +/** + * order_base_2 - calculate the (rounded up) base 2 order of the argument + * @n: parameter + * + * The first few values calculated by this routine: + * ob2(0) = 0 + * ob2(1) = 0 + * ob2(2) = 1 + * ob2(3) = 2 + * ob2(4) = 2 + * ob2(5) = 3 + * ... and so on. + */ + +#define order_base_2(n) ilog2(roundup_pow_of_two(n)) + +#endif /* _LINUX_LOG2_H */ -- 1.9.1

4 36

[U-Boot] [BUG] am335x_evm_defconfig doesn't boot with 2015.10
by Matwey V. Kornilov 03 Nov '15

03 Nov '15

Hi, I am facing the following when trying to boot on beaglebone black: U-Boot SPL 2015.10 (Nov 01 2015 - 17:51:08) bad magic bad magic spl_register_fat_device: fat register err - -1 spl_register_fat_device: fat register err - -1 spl_load_image_fat: error reading image u-boot.img, err - -1 spl: ext4fs_open failed spl: ext4fs_open failed spl_load_image_ext: error reading image uImage, err - -1 U-Boot 2015.10 (Nov 01 2015 - 17:51:08 +0000) Watchdog enabled I2C: ready DRAM: 512 MiB NAND: 0 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 *** Error - No Valid Environment Area found *** Warning - bad CRC, using default environment Net: <ethaddr> not set. Validating first E-fuse MAC cpsw, usb_ether Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device SD/MMC found on device 0 2777 bytes read in 10 ms (270.5 KiB/s) Running bootscript from mmc0 ... ## Executing script at 82000000 switch to partitions #0, OK mmc0 is current device 7316696 bytes read in 444 ms (15.7 MiB/s) 48645094 bytes read in 2814 ms (16.5 MiB/s) 35700 bytes read in 24 ms (1.4 MiB/s) Kernel image @ 0x82000000 [ 0x000000 - 0x6fa4d8 ] data abort pc : [<9ff63ece>] lr : [<9ff63f25>] reloc pc : [<80810ece>] lr : [<80810f25>] sp : 9ef32228 ip : 0000001c fp : 9ef39bf4 r10: 00000003 r9 : 9ef32ed8 r8 : 00000002 r7 : 9ffa421c r6 : 9ffa4220 r5 : 00000003 r4 : 9ffa4184 r3 : 56190527 r2 : 9ffa4184 r1 : 9ef39bf4 r0 : 00000000 Flags: nZcv IRQs off FIQs on Mode SVC_32 Resetting CPU ... resetting ... Last working version was 2015.10-rc4. 2015.10-rc5 does not work. gcc version is 5.2.1 u-boot has been compiled as the following: make -j 1 'CFLAGS=-fmessage-length=0 -grecord-gcc-switches -O2 -Wall -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables' am335x_evm_defconfig make -j 1 'CFLAGS=-fmessage-length=0 -grecord-gcc-switches -O2 -Wall -D_FORTIFY_SOURCE=2 -fstack-protector -funwind-tables -fasynchronous-unwind-tables' USE_PRIVATE_LIBGG=yes

2 1

[U-Boot] [PATCH v2 1/2] fdt: Deprecate "usbethaddr" usage in fdt_fixup_ethernet()
by Bin Meng 03 Nov '15

03 Nov '15

In fdt_fixup_ethernet() only "usbethaddr" is handled to fix up the first usb ethernet port MAC address. Other additional usb ethernet ports are ignored as there is no logic to handle "usbeth%daddr". It is suggested we should use "ethaddr" for all ethernet devices. Hence deprecate "usbethaddr" usage in fdt_fixup_ethernet(). Note this actually reverts commit b1f49ab. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - New patch to deprecate "usbethaddr" usage in fdt_fixup_ethernet() common/fdt_support.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index a7ff2df..ec72b86 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -490,18 +490,8 @@ void fdt_fixup_ethernet(void *fdt) if (node < 0) return; - if (!getenv("ethaddr")) { - if (getenv("usbethaddr")) { - strcpy(mac, "usbethaddr"); - } else { - debug("No ethernet MAC Address defined\n"); - return; - } - } else { - strcpy(mac, "ethaddr"); - } - i = 0; + strcpy(mac, "ethaddr"); while ((tmp = getenv(mac)) != NULL) { sprintf(enet, "ethernet%d", i); path = fdt_getprop(fdt, node, enet, NULL); -- 1.8.2.1

3 4

[U-Boot] Please pull u-boot-mpc85xx master
by York Sun 03 Nov '15

03 Nov '15

Tom, The following changes since commit a61047370d0b73ab886c5863e952695b5ee0d75b: ARM: at91: sama5: change the environment address to 0x6000 (2015-11-01 22:02:16 +0100) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to 96d59e9d6aa74e35c63dc74da10e41f8ba0f6de4: mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1 (2015-11-02 08:51:50 -0800) ---------------------------------------------------------------- Codrin Ciubotariu (1): T104xD4RDB: Fix PHY address for PHY connected to FM1@DTSEC3 Shaohui Xie (1): Powerpc: eSDHC: expand a fix to T4160 Shengzhou Liu (1): mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1 Yangbo Lu (4): mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter Card powerpc/t1040qds: enable adapter card type identification support powerpc/t1040qds: enable peripheral clock for eSDHC mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter Card Zhao Qiang (1): t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdm arch/powerpc/cpu/mpc85xx/fdt.c | 11 +++++++++++ arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- arch/powerpc/include/asm/fsl_fdt.h | 11 +++++++++++ board/freescale/common/qixis.h | 5 +++++ board/freescale/t104xrdb/cpld.h | 1 + board/freescale/t104xrdb/t104xrdb.c | 10 ++++++++++ drivers/mmc/fsl_esdhc.c | 9 ++++++++- include/configs/T1040QDS.h | 2 ++ include/configs/T104xRDB.h | 4 +++- 9 files changed, 53 insertions(+), 3 deletions(-) create mode 100644 arch/powerpc/include/asm/fsl_fdt.h Thanks. York

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[U-Boot] [PATCH 1/3] net: zynq: Extend register description with offsets
by Michal Simek 02 Nov '15

02 Nov '15

Extend comments with register offset to help with debuggging. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/zynq_gem.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 72f1332c8008..d98c229f4330 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -108,28 +108,28 @@ /* Device registers */ struct zynq_gem_regs { - u32 nwctrl; /* Network Control reg */ - u32 nwcfg; /* Network Config reg */ - u32 nwsr; /* Network Status reg */ + u32 nwctrl; /* 0x0 - Network Control reg */ + u32 nwcfg; /* 0x4 - Network Config reg */ + u32 nwsr; /* 0x8 - Network Status reg */ u32 reserved1; - u32 dmacr; /* DMA Control reg */ - u32 txsr; /* TX Status reg */ - u32 rxqbase; /* RX Q Base address reg */ - u32 txqbase; /* TX Q Base address reg */ - u32 rxsr; /* RX Status reg */ + u32 dmacr; /* 0x10 - DMA Control reg */ + u32 txsr; /* 0x14 - TX Status reg */ + u32 rxqbase; /* 0x18 - RX Q Base address reg */ + u32 txqbase; /* 0x1c - TX Q Base address reg */ + u32 rxsr; /* 0x20 - RX Status reg */ u32 reserved2[2]; - u32 idr; /* Interrupt Disable reg */ + u32 idr; /* 0x2c - Interrupt Disable reg */ u32 reserved3; - u32 phymntnc; /* Phy Maintaince reg */ + u32 phymntnc; /* 0x34 - Phy Maintaince reg */ u32 reserved4[18]; - u32 hashl; /* Hash Low address reg */ - u32 hashh; /* Hash High address reg */ + u32 hashl; /* 0x80 - Hash Low address reg */ + u32 hashh; /* 0x84 - Hash High address reg */ #define LADDR_LOW 0 #define LADDR_HIGH 1 - u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ - u32 match[4]; /* Type ID1 Match reg */ + u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ + u32 match[4]; /* 0xa8 - Type ID1 Match reg */ u32 reserved6[18]; - u32 stat[44]; /* Octects transmitted Low reg - stat start */ + u32 stat[44]; /* 0x100 - Octects transmitted Low reg - stat start */ }; /* BD descriptors */ -- 2.5.0

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[U-Boot] [PATCH 1/2] net: zynq: Add debug message to phyread/phywrite
by Michal Simek 02 Nov '15

02 Nov '15

Add debug messages to phyread/write to help with PHY debug. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/zynq_gem.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 9175d2cae8f7..3d21ad617359 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -208,12 +208,23 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) { - return phy_setup_op(dev, phy_addr, regnum, + u32 ret; + + ret = phy_setup_op(dev, phy_addr, regnum, ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); + + if (!ret) + debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, + phy_addr, regnum, *val); + + return ret; } static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) { + debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, + regnum, data); + return phy_setup_op(dev, phy_addr, regnum, ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); } -- 2.5.0

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[U-Boot] [PATCH] mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1
by Shengzhou Liu 02 Nov '15

02 Nov '15

T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing for ratio. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 79202bb..a48e743 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -127,7 +127,8 @@ void get_sys_info(sys_info_t *sys_info) * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) + defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \ + defined(CONFIG_PPC_T2081) svr = get_svr(); switch (SVR_SOC_VER(svr)) { case SVR_T4240: -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] T104xD4RDB: Fix PHY address for PHY connected to FM1@DTSEC3
by Codrin Ciubotariu 02 Nov '15

02 Nov '15

On T1040D4RDB board, u-boot fails to connect port FM1@DTSEC3 to the Ethernet PHY because the wrong PHY address is used. Also, T1040D4RDB supports SGMII on one port only. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu(a)freescale.com> --- include/configs/T104xRDB.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5b61b56..e872507 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -742,7 +742,9 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 -#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB) +#elif defined(CONFIG_T1040D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 +#elif defined(CONFIG_T1042D4RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 -- 1.9.3

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