November 2015 - U-Boot

[U-Boot] [PATCH 00/10] dm: timer: x86: 64-bit counter support and tsc timer dm conversion
by Bin Meng 10 Nov '15

10 Nov '15

This series enhances timer uclass driver to support 64-bit counter value, and convert tsc timer to driver model to be used by all x86 boards. As a result of dm conversion, the TSC_CALIBRATION_BYPASS Kconfig option is no longer needed, and the TSC frequency can be specified in the board device tree. Bin Meng (10): dm: timer: Fix several nits dm: timer: Implement pre_probe() timer: altera: Remove the codes to get clock frequency dm: timer: Support 64-bit counter x86: Reomve MIN_PORT80_KCLOCKS_DELAY x86: tsc: Use notrace from <linux/compiler.h> x86: tsc: Add driver model timer support x86: Convert to use driver model timer x86: tsc: Remove legacy timer codes x86: tsc: Move tsc_timer.c to drivers/timer arch/x86/Kconfig | 20 ------ arch/x86/cpu/baytrail/valleyview.c | 3 - arch/x86/cpu/coreboot/timestamp.c | 22 ------ arch/x86/cpu/cpu.c | 18 ----- arch/x86/cpu/efi/efi.c | 4 -- arch/x86/cpu/ivybridge/cpu.c | 1 - arch/x86/cpu/qemu/Kconfig | 1 - arch/x86/cpu/qemu/qemu.c | 3 - arch/x86/cpu/quark/Kconfig | 5 -- arch/x86/cpu/quark/quark.c | 3 - arch/x86/cpu/queensbay/tnc.c | 3 - arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/broadwell_som-6896.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/crownbay.dts | 1 + arch/x86/dts/efi.dts | 5 ++ arch/x86/dts/galileo.dts | 5 ++ arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 5 ++ arch/x86/dts/qemu-x86_q35.dts | 5 ++ arch/x86/dts/tsc_timer.dtsi | 7 ++ arch/x86/include/asm/global_data.h | 3 - arch/x86/lib/Makefile | 1 - configs/bayleybay_defconfig | 1 + configs/chromebook_link_defconfig | 2 +- configs/chromebox_panther_defconfig | 2 +- configs/coreboot-x86_defconfig | 3 +- configs/crownbay_defconfig | 1 + configs/efi-x86_defconfig | 2 +- configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/qemu-x86_defconfig | 1 + drivers/timer/Kconfig | 17 +++-- drivers/timer/Makefile | 1 + drivers/timer/altera_timer.c | 8 +-- drivers/timer/timer-uclass.c | 43 ++++++++++-- {arch/x86/lib => drivers/timer}/tsc_timer.c | 104 ++++++++++++++++------------ include/configs/x86-common.h | 2 - include/timer.h | 17 +++-- lib/time.c | 9 ++- 41 files changed, 168 insertions(+), 167 deletions(-) create mode 100644 arch/x86/dts/tsc_timer.dtsi rename {arch/x86/lib => drivers/timer}/tsc_timer.c (87%) -- 1.8.2.1

3 28

[U-Boot] [PATCH v4 00/20] Bring up rk3036 uboot
by Lin Huang 10 Nov '15

10 Nov '15

This series patch bring up rk3036 uboot, since rk3036 only 4K size SRAM for SPL, so in SPL stage only support timer, uart, sdram driver, and back to bootrom when finish ddr initial, and boot up second stage from bootrom.You can boot to command line(mmc info etc) for now use this patchset. Jeffy Chen (2): rockchip: Add max init size & chip tag configs rockchip: Add support for rk's second level loader Lin Huang (18): rockchip: add timer driver rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig rockchip: rename board-spl.c to rk3288-board-spl.c rockchip: add config decide whether to build common.c dm: core: Add SPL Kconfig for REGMAP and SYSCON rockchip: serial driver support rk3036 rockchip: Bring in RK3036 device tree file includes and bindings rockchip: rk3036: Add clock driver rockchip: rk3036: Add header files for GRF rockchip: rk3036: Add Soc reset driver rockchip: rk3036: Add a simple syscon driver rockchip: rk3036: Add pinctrl driver rockchip: Add an rk3036 MMC driver rockchip: add early uart driver rockchip: add rk3036 sdram driver rockchip: rk3036: Add core Soc start-up code rockchip: Add basic support for evb-rk3036 board rockchip: doc: show packet rk3036 uboot image arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++ arch/arm/dts/rk3036.dtsi | 427 +++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 +++++++++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 ++++++++++ arch/arm/include/asm/arch-rockchip/timer.h | 22 + arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ arch/arm/mach-rockchip/Kconfig | 13 +- arch/arm/mach-rockchip/Makefile | 10 +- arch/arm/mach-rockchip/board-spl.c | 294 --------- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 53 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 17 + arch/arm/mach-rockchip/rk3036/Makefile | 13 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/save_boot_param.S | 34 + arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 737 ++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + arch/arm/mach-rockchip/rk3288-board-spl.c | 277 ++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 3 + arch/arm/mach-rockchip/rk_early_print.c | 56 ++ arch/arm/mach-rockchip/rk_timer.c | 48 ++ board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 48 ++ configs/chromebook_jerry_defconfig | 2 + configs/evb-rk3036_defconfig | 25 + configs/firefly-rk3288_defconfig | 2 + configs/sandbox_defconfig | 2 + doc/README.rockchip | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 414 ++++++++++++ drivers/core/Kconfig | 19 + drivers/core/Makefile | 4 +- drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_3036_dw_mmc.c | 485 ++++++++++++++ drivers/pinctrl/Kconfig | 18 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 ++++++++ drivers/serial/serial_rockchip.c | 1 + include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 103 +++ include/configs/rk3288_common.h | 9 +- include/dt-bindings/clock/rk3036-cru.h | 186 ++++++ tools/Makefile | 6 + tools/rkcommon.c | 26 +- tools/rkcommon.h | 4 +- tools/rkimage.c | 2 +- tools/rksd.c | 6 +- tools/rkspi.c | 6 +- 53 files changed, 4534 insertions(+), 329 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/include/asm/arch-rockchip/uart.h delete mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 arch/arm/mach-rockchip/rk3036/sdram_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk_early_print.c create mode 100644 arch/arm/mach-rockchip/rk_timer.c create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 drivers/clk/clk_rk3036.c create mode 100644 drivers/mmc/rockchip_3036_dw_mmc.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c create mode 100644 include/configs/evb_rk3036.h create mode 100644 include/configs/rk3036_common.h create mode 100644 include/dt-bindings/clock/rk3036-cru.h -- 1.9.1

3 42

[U-Boot] [UBOOT PATCH v2 1/2] zynqmp: nand: Add Nand driver support for zynqmp
by Siva Durga Prasad Paladugu 10 Nov '15

10 Nov '15

Add nand driver support for zynqmp. The Nand controller used in ZynqMP is Arasan Nand Flash controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- Changes from v1: - Newly added in series --- arch/arm/cpu/armv8/zynqmp/Kconfig | 3 +++ arch/arm/include/asm/arch-zynqmp/hardware.h | 2 ++ configs/xilinx_zynqmp_ep_defconfig | 1 + include/configs/xilinx_zynqmp.h | 9 +++++++++ 4 files changed, 15 insertions(+) diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index e5a4fdd..161954f 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -27,4 +27,7 @@ config SECURE_IOU config ZYNQMP_USB bool "Configure ZynqMP USB" +config NAND_ARASAN + bool "Configure Arasan Nand" + endif diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 0f03c24..3c9f08c 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -25,6 +25,8 @@ #define ZYNQ_SDHCI_BASEADDR0 0xFF160000 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000 +#define ARASAN_NAND_BASEADDR 0xFF100000 + #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 79304c1..43a24a7 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_ZYNQMP_USB=y +CONFIG_NAND_ARASAN=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" CONFIG_SYS_PROMPT="ZynqMP> " diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 36c1100..1f17adb 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -101,6 +101,15 @@ # define CONFIG_CMD_EXT4_WRITE #endif +#ifdef CONFIG_NAND_ARASAN +# define CONFIG_CMD_NAND +# define CONFIG_CMD_NAND_LOCK_UNLOCK +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_SELF_INIT +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_MTD_DEVICE +#endif + /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR 0x8000000 -- 2.1.1

2 4

[U-Boot] [PATCH v4 1/7] ARM: OMAP4/5: Centralize early clock initialization
by Steve Kipisz 10 Nov '15

10 Nov '15

Early clock initialization is currently done in two stages for OMAP4/5 SoCs. The first stage is the initialization of console clocks and then we initialize basic clocks for functionality necessary for SoC initialization and basic board functionality. By splitting up prcm_init and centralizing this clock initialization, we setup the code for follow on patches that can do board specific initialization such as board detection which will depend on these basic clocks. As part of this change, since the early clock initialization is centralized, we no longer need to expose the console clock initialization. NOTE: we change the sequence slightly by initializing console clocks timer after the io settings are complete, but this is not expected to have any functioanlity impact since we setup the basic IO drive strength initialization as part of do_io_settings. Signed-off-by: Steve Kipisz <s-kipisz2(a)ti.com> Reviewed-by: Tom Rini <trini(a)konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- Changes in v4 (since v3): - Picked up Reviewed-by v3: https://patchwork.ozlabs.org/patch/540193/ v2: http://marc.info/?t=144655363000001&r=1&w=2 (mailing list squashed original submission) v1: Did not exist arch/arm/cpu/armv7/omap-common/clocks-common.c | 21 +++++++++++++++++++-- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 3 +-- arch/arm/include/asm/arch-omap4/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap5/sys_proto.h | 2 +- 4 files changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index e28b79568d1d..367d224361be 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -769,7 +769,7 @@ void lock_dpll(u32 const base) wait_for_lock(base); } -void setup_clocks_for_console(void) +static void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, @@ -853,14 +853,31 @@ void do_disable_clocks(u32 const *clk_domains, disable_clock_domain(clk_domains[i]); } -void prcm_init(void) +/** + * setup_early_clocks() - Setup early clocks needed for SoC + * + * Setup clocks for console, SPL basic initialization clocks and initialize + * the timer. This is invoked prior prcm_init. + */ +void setup_early_clocks(void) { switch (omap_hw_init_context()) { case OMAP_INIT_CONTEXT_SPL: case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + setup_clocks_for_console(); enable_basic_clocks(); timer_init(); + /* Fall through */ + } +} + +void prcm_init(void) +{ + switch (omap_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: scale_vcores(*omap_vcores); setup_dplls(); setup_warmreset_time(); diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 80794f9c611a..91f2dead364b 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -125,10 +125,9 @@ void s_init(void) set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD srcomp_enable(); - setup_clocks_for_console(); - do_io_settings(); #endif + setup_early_clocks(); prcm_init(); } diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index f30f86539130..71e3d776aa0d 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); -void setup_clocks_for_console(void); +void setup_early_clocks(void); void prcm_init(void); void bypass_dpll(u32 const base); void freq_update_core(void); diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 7fcb78389403..b9e09e7c52a8 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -48,7 +48,7 @@ void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); -void setup_clocks_for_console(void); +void setup_early_clocks(void); void prcm_init(void); void bypass_dpll(u32 const base); void freq_update_core(void); -- 1.9.1

5 18

[U-Boot] [PATCH] ARM: zynq: Choose boot image based on OF_SEPARATE macro
by Michal Simek 09 Nov '15

09 Nov '15

OF_CONTROL is enabled by default for all Zynq boards. The difference between two boot images is done by OF_SEPARATE or OF_EMBED macros. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/zynq-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index f98101fc2730..9f32d6f16268 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -332,7 +332,7 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#ifdef CONFIG_OF_CONTROL +#ifdef CONFIG_OF_SEPARATE # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" #else # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -- 2.5.0

2 1

[U-Boot] [PATCH] serial: serial_x86: add ns16550a compatible ids
by Thomas Chou 09 Nov '15

09 Nov '15

Add ns16550a compatible ids, so that other arch may use this standard driver. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- drivers/serial/serial_x86.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c index 4bf6062..f378eee 100644 --- a/drivers/serial/serial_x86.c +++ b/drivers/serial/serial_x86.c @@ -14,6 +14,8 @@ DECLARE_GLOBAL_DATA_PTR; static const struct udevice_id x86_serial_ids[] = { { .compatible = "x86-uart" }, + { .compatible = "ns16550a" }, + { .compatible = "ns16550" }, { } }; -- 2.5.0

3 4

[U-Boot] [PATCH 0/4] ARM: tegra: GPU WPR region support
by Alexandre Courbot 09 Nov '15

09 Nov '15

This series makes U-boot program the write-protected (WPR) region of T210 chips, allowing the kernel to perform GPU secure firmware loading. Tegra 210's GPU requires its firmware to be loaded though a write-protected region. An area of physical memory is carved-out, programmed into the corresponding memory controller registers, and locked such as only the GPU can write into it. This area needs to be set up by the bootloader since it cannot be re-claimed for normal use after being locked. The first 3 patches of this series are cleanup patches. Patch 2 implements a suggestion made by Stephen, patch 3 renames GPU-related functions to sound less generic. The last patch adds support for the GPU WPR region. The top 256KB of memory are removed from the available memory, and the corresponding MC registers are programmed to point to it, which allows the kernel to initiate secure firmware loading. Alexandre Courbot (4): ARM: tegra: remove vpr_configured() function ARM: tegra: simplify GPU setup ARM: tegra: rename GPU functions ARM: tegra210: gpu: configure WPR region arch/arm/include/asm/arch-tegra/gpu.h | 14 +++------ arch/arm/include/asm/arch-tegra210/mc.h | 12 ++++++++ arch/arm/mach-tegra/board.c | 4 +++ arch/arm/mach-tegra/board2.c | 22 +++++++++++++- arch/arm/mach-tegra/gpu.c | 52 +++++++++++++++++++++++++++++---- board/nvidia/jetson-tk1/jetson-tk1.c | 8 ----- board/nvidia/p2571/p2571.c | 7 ----- board/nvidia/venice2/venice2.c | 8 ----- include/configs/jetson-tk1.h | 2 -- include/configs/p2571.h | 2 -- include/configs/tegra-common.h | 2 ++ include/configs/venice2.h | 2 -- 12 files changed, 89 insertions(+), 46 deletions(-) -- 2.6.1

5 16

[U-Boot] [PATCH v2] usb:ci_udc: Remove ULPI setting for i.MX OTG controller
by Ye.Li 09 Nov '15

09 Nov '15

All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI interface. Set to ULPI is not correct, even the controller will reject this setting in PORTSC register. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes since v1: - Add error handling for udc probe drivers/usb/gadget/ci_udc.c | 14 +++----------- 1 files changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 1ba5054..d93cba5 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -1018,18 +1018,10 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) return ret; ret = ci_udc_probe(); -#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS) - /* - * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all - * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection - */ - if (!ret) { - struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; - - /* select ULPI phy */ - writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); + if (ret) { + DBG("udc probe failed, returned %d\n", ret); + return ret; } -#endif ret = driver->bind(&controller.gadget); if (ret) { -- 1.7.4.1

3 2

[U-Boot] eth_send, eth_rx
by Milan Joshi 09 Nov '15

09 Nov '15

Hi Team, I want to implement eth client like application in the form of some command. I am going through the TFTP protocol implementation so that I can understand the flow. I want to make sure about following.. After sending packet using eth_send or NetSendUdpPacket, eth_rx function is polled inside NetLoop and on reception of packet NetReceive function will be called by eth_rx. eth_rx function must be called continuously i.e. polling. Is this correct understanding? is polling eth_rx the only solution? Regards, mj

1 0

[U-Boot] [PATCH] nios2: add 10m50 devboard support
by Thomas Chou 09 Nov '15

09 Nov '15

Add 10m50 devboard support. It is based on the Golden Hardware Reference Design (GHRD), available at, http://rocketboards.org/foswiki/view/Documentation/ AlteraMAX1010M50RevCDevelopmentKitLinuxSetup Though we supported only one nios2-generic board in the past. Now, with the removal of the nios2-generic board dir, adding new nios2 boards to u-boot is easier than before. It should be helpful to add those boards supported in Linux mainline. There are only two such nios2 boards, the 3c120 devboard and 10m50 devboard. The nios2-generic is actually 3c120, and should restore the name. The 10m50 is this one. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/dts/10m50_devboard.dts | 259 ++++++++++++++++++++++++++++++++++++++ configs/10m50_defconfig | 23 ++++ include/configs/10m50_devboard.h | 98 +++++++++++++++ 3 files changed, 380 insertions(+) create mode 100644 arch/nios2/dts/10m50_devboard.dts create mode 100644 configs/10m50_defconfig create mode 100644 include/configs/10m50_devboard.h diff --git a/arch/nios2/dts/10m50_devboard.dts b/arch/nios2/dts/10m50_devboard.dts new file mode 100644 index 0000000..8f22318 --- /dev/null +++ b/arch/nios2/dts/10m50_devboard.dts @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * This file is generated by sopc2dts. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/ { + model = "Altera NiosII Max10"; + compatible = "altr,niosii-max10"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "altr,nios2-1.1"; + reg = <0x00000000>; + interrupt-controller; + #interrupt-cells = <1>; + altr,exception-addr = <0xc8000120>; + altr,fast-tlb-miss-addr = <0xc0000100>; + altr,has-div = <1>; + altr,has-initda = <1>; + altr,has-mmu = <1>; + altr,has-mul = <1>; + altr,implementation = "fast"; + altr,pid-num-bits = <8>; + altr,reset-addr = <0xd4000000>; + altr,tlb-num-entries = <256>; + altr,tlb-num-ways = <16>; + altr,tlb-ptr-sz = <8>; + clock-frequency = <75000000>; + dcache-line-size = <32>; + dcache-size = <32768>; + icache-line-size = <32>; + icache-size = <32768>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x08000000 0x08000000>, + <0x00000000 0x00000400>; + }; + + sopc0: sopc@0 { + device_type = "soc"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + compatible = "altr,avalon", "simple-bus"; + bus-frequency = <75000000>; + + jtag_uart: serial@18001530 { + compatible = "altr,juart-1.0"; + reg = <0x18001530 0x00000008>; + interrupt-parent = <&cpu>; + interrupts = <7>; + }; + + a_16550_uart_0: serial@18001600 { + compatible = "altr,16550-FIFO32", "ns16550a"; + reg = <0x18001600 0x00000200>; + interrupt-parent = <&cpu>; + interrupts = <1>; + auto-flow-control = <1>; + clock-frequency = <50000000>; + fifo-size = <32>; + reg-io-width = <4>; + reg-shift = <2>; + }; + + ext_flash: quadspi@0x180014a0 { + compatible = "altr,quadspi-1.0"; + reg = <0x180014a0 0x00000020>, + <0x14000000 0x04000000>; + reg-names = "avl_csr", "avl_mem"; + interrupt-parent = <&cpu>; + interrupts = <4>; + }; + + sysid: sysid@18001528 { + compatible = "altr,sysid-1.0"; + reg = <0x18001528 0x00000008>; + }; + + rgmii_0_eth_tse_0: ethernet@400 { + compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0"; + reg = <0x00000400 0x00000400>, + <0x00000820 0x00000020>, + <0x00000800 0x00000020>, + <0x000008c0 0x00000008>, + <0x00000840 0x00000020>, + <0x00000860 0x00000020>; + reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; + interrupt-parent = <&cpu>; + interrupts = <2 3>; + interrupt-names = "rx_irq", "tx_irq"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + address-bits = <48>; + max-frame-size = <1518>; + local-mac-address = [00 00 00 00 00 00]; + altr,has-supplementary-unicast; + altr,enable-sup-addr = <1>; + altr,has-hash-multicast-filter; + altr,enable-hash = <1>; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + rgmii_0_eth_tse_0_mdio: mdio { + compatible = "altr,tse-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; + }; + }; + + enet_pll: clock@0 { + compatible = "altr,pll-1.0"; + #clock-cells = <1>; + + enet_pll_c0: enet_pll_c0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "enet_pll-c0"; + }; + + enet_pll_c1: enet_pll_c1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "enet_pll-c1"; + }; + + enet_pll_c2: enet_pll_c2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2500000>; + clock-output-names = "enet_pll-c2"; + }; + }; + + sys_pll: clock@1 { + compatible = "altr,pll-1.0"; + #clock-cells = <1>; + + sys_pll_c0: sys_pll_c0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sys_pll-c0"; + }; + + sys_pll_c1: sys_pll_c1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sys_pll-c1"; + }; + + sys_pll_c2: sys_pll_c2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <75000000>; + clock-output-names = "sys_pll-c2"; + }; + }; + + sys_clk_timer: timer@18001440 { + compatible = "altr,timer-1.0"; + reg = <0x18001440 0x00000020>; + interrupt-parent = <&cpu>; + interrupts = <0>; + clock-frequency = <75000000>; + }; + + led_pio: gpio@180014d0 { + compatible = "altr,pio-1.0"; + reg = <0x180014d0 0x00000010>; + altr,gpio-bank-width = <4>; + resetvalue = <15>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "led"; + }; + + uart_0: serial@0x18001420 { + compatible = "altr,uart-1.0"; + reg = <0x18001420 0x00000020>; + interrupt-parent = <&cpu>; + interrupts = <1>; + clock-frequency = <75000000>; + current-speed = <115200>; + }; + + button_pio: gpio@180014c0 { + compatible = "altr,pio-1.0"; + reg = <0x180014c0 0x00000010>; + interrupt-parent = <&cpu>; + interrupts = <6>; + altr,gpio-bank-width = <3>; + altr,interrupt-type = <2>; + edge_type = <1>; + level_trigger = <0>; + resetvalue = <0>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "button"; + }; + + sys_clk_timer_1: timer@880 { + compatible = "altr,timer-1.0"; + reg = <0x00000880 0x00000020>; + interrupt-parent = <&cpu>; + interrupts = <5>; + clock-frequency = <75000000>; + }; + + fpga_leds: leds { + compatible = "gpio-leds"; + + led_fpga0: fpga0 { + label = "fpga_led0"; + gpios = <&led_pio 0 1>; + }; + + led_fpga1: fpga1 { + label = "fpga_led1"; + gpios = <&led_pio 1 1>; + }; + + led_fpga2: fpga2 { + label = "fpga_led2"; + gpios = <&led_pio 2 1>; + }; + + led_fpga3: fpga3 { + label = "fpga_led3"; + gpios = <&led_pio 3 1>; + }; + }; + }; + + chosen { + bootargs = "debug console=ttyS0,115200"; + stdout-path = &uart_0; + }; +}; diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig new file mode 100644 index 0000000..fa5ffd7 --- /dev/null +++ b/configs/10m50_defconfig @@ -0,0 +1,23 @@ +CONFIG_NIOS2=y +CONFIG_SYS_CONFIG_NAME="10m50_devboard" +CONFIG_DM_SERIAL=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ALTERA_PIO=y +CONFIG_MISC=y +CONFIG_ALTERA_SYSID=y +CONFIG_ALTERA_UART=y +CONFIG_TIMER=y +CONFIG_ALTERA_TIMER=y diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h new file mode 100644 index 0000000..4140f2d --- /dev/null +++ b/include/configs/10m50_devboard.h @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * BOARD/CPU + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * SERIAL + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ + +/* + * CFI Flash + */ +#define CONFIG_SYS_NO_FLASH + +/* + * MII/PHY + */ +#define CONFIG_CMD_MII 1 +#define CONFIG_PHY_GIGE 1 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 +#define CONFIG_PHY_MARVELL 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * FDT options + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_LMB + +/* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ + +/* + * MEMORY ORGANIZATION + * -Monitor at top of sdram. + * -The heap is placed below the monitor + * -The stack is placed below the heap (&grows down). + */ +#define CONFIG_SYS_SDRAM_BASE 0xc8000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x20000) +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - \ + CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_INIT_SP CONFIG_SYS_MALLOC_BASE + +/* + * MISC + */ +#define CONFIG_SYS_LONGHELP /* Provide extended help */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ +#define CONFIG_SYS_MAXARGS 16 /* Max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) /* Print buf size */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - 0x20000) +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_GPIO + +#endif /* __CONFIG_H */ -- 2.1.4

2 7