November 2015 - U-Boot

[U-Boot] [PATCH v7 0/5] Add support for Thumb-1 builds
by Albert ARIBAUD 10 Nov '15

10 Nov '15

This series implements essential changes for thumb-1 support and activates thumb-1 build for openrd and tricorder as a proof of concept as well as a fix to bring the image sizes of openrd and tricorder targets back under an acceptable limit. For other targets, some additional files might need to be forced to ARM building, notably architecture-specific instances of lowlevel_init.S or of cpu.c. This should be handled on a case-by-case basis. This series has two unfixed checkpatch diagnostics: warning: arch/arm/mach-kirkwood/Kconfig,7: please write a paragraph that describes the config symbol fully (no option in this Kconfig has help info) check: board/Marvell/openrd/openrd.c,42: Avoid CamelCase: <MPP6_SYSRST_OUTn> (this is actually not an OpenRD problem and will be fixed in another patch) IMPORTANT NOTE: The whole set has been build-tested across all ARM targets and no build regression was detected -- actually, the series does fix the x600 board which otherwise fails assembling an mcr instruction. Patch 1 has been confirmed to be binary-invariant. Patch 2 has been build- and run-tested on ED Mini V2 (switched temporarily to Thumb build) and confirmed to be binary-invariant for non-thumb target Wireless Space. Patches 3 through 6 have been build-tested BUT HAVE NOT BEEN RUN-TESTED so far. I will test on OpenRD (client) before the end of the merge window, but: ********************************************************* Open-RD and Tricorder owners, PLEASE run-test this series and report on the mailing list whether the target works. ********************************************************* Changes in v7: - remove openrd lines from doc/README.scrapyard Changes in v6: - revive OpenRD targets and assume maintainership - switch OpenRD to generic board and Thumb - fix checkpatch warning and checks Changes in v5: - switched tricorder[_flash] to Thumb-1 build Changes in v4: - Made stm32f429-discovery explicitly state that it builds for Thumb Changes in v3: - added arch/arm/lib/mem{set,cpy}.S to the list of modules which should always be built in ARM state. - Selected HAS_THUMB2 for CPU_V7M. - Fixed invalidate_l2_cache() when building for Thumb-1. Changes in v2: - fixed a typo in the commit message - added file arch/arm/thumb1/include/asm/proc-armv/system.h, which overrides arch/arm/include/asm/proc-armv/system.h when building for Thumb-1 and provides non-functional but Thumb-compilable IRQ and FIQ related macros and functions. Albert ARIBAUD (5): stm32f429-discovery: add CONFIG_SYS_THUMB_BUILD arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD tricorder: switch to CONFIG_SYS_THUMB_BUILD kirkwood: support CONFIG_SYS_THUMB_BUILD Revive OpenRD targets Makefile | 2 + arch/arm/Kconfig | 5 + arch/arm/cpu/arm926ejs/Makefile | 11 ++ arch/arm/cpu/arm926ejs/cache.c | 5 + arch/arm/include/asm/cache.h | 4 + arch/arm/lib/Makefile | 24 ++++ arch/arm/lib/cache.c | 11 ++ arch/arm/lib/memcpy.S | 4 +- arch/arm/lib/memset.S | 2 +- arch/arm/mach-kirkwood/Kconfig | 4 + arch/arm/mach-kirkwood/Makefile | 6 + arch/arm/mach-orion5x/Makefile | 10 ++ arch/arm/thumb1/include/asm/proc-armv/system.h | 69 +++++++++++ board/Marvell/openrd/Kconfig | 12 ++ board/Marvell/openrd/MAINTAINERS | 12 ++ board/Marvell/openrd/Makefile | 14 +++ board/Marvell/openrd/kwbimage.cfg | 152 +++++++++++++++++++++++ board/Marvell/openrd/openrd.c | 160 +++++++++++++++++++++++++ board/Marvell/openrd/openrd.h | 30 +++++ configs/openrd_base_defconfig | 7 ++ configs/openrd_client_defconfig | 7 ++ configs/openrd_ultimate_defconfig | 7 ++ doc/README.scrapyard | 3 - examples/standalone/Makefile | 10 ++ include/configs/openrd.h | 140 ++++++++++++++++++++++ include/configs/stm32f429-discovery.h | 1 + include/configs/tricorder.h | 1 + 27 files changed, 707 insertions(+), 6 deletions(-) create mode 100644 arch/arm/thumb1/include/asm/proc-armv/system.h create mode 100644 board/Marvell/openrd/Kconfig create mode 100644 board/Marvell/openrd/MAINTAINERS create mode 100644 board/Marvell/openrd/Makefile create mode 100644 board/Marvell/openrd/kwbimage.cfg create mode 100644 board/Marvell/openrd/openrd.c create mode 100644 board/Marvell/openrd/openrd.h create mode 100644 configs/openrd_base_defconfig create mode 100644 configs/openrd_client_defconfig create mode 100644 configs/openrd_ultimate_defconfig create mode 100644 include/configs/openrd.h -- 2.1.4

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[U-Boot] [PATCH v3 1/2] arm: add support for semihosting for ARMv7M targets
by Vadzim Dambrouski 10 Nov '15

10 Nov '15

If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile error looking like this: arch/arm/lib/semihosting.c: In function 'smh_read': {standard input}: Assembler messages: {standard input}:34: Error: invalid swi expression {standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0 scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed The source of the problem is "svc #0x123456" instruction. This instruction can not be encoded using Thumb2 instruction set used by ARMv7M CPUs. ARM documentation suggests using "bkpt #0xAB" instruction instead [1]. This patch fixes compile errors and adds support for semihosting for STM32F429 or any other ARMv7M target. This change was sested on STM32F429-DISCOVERY board using OpenOCD and "smhload" u-boot command. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhi… Signed-off-by: Vadzim Dambrouski <pftbest(a)gmail.com> --- arch/arm/lib/semihosting.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index c3e964e..ed5e8e4 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) register long result asm("r0"); #if defined(CONFIG_ARM64) asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr)); +#elif defined(CONFIG_CPU_V7M) + asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr)); #else /* Note - untested placeholder */ asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr)); -- 2.6.1

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[U-Boot] [PATCH v2] net: phy: Add support for Texas Instruments DP83867
by Michal Simek 10 Nov '15

10 Nov '15

From: "Edgar E. Iglesias" <edgar.iglesias(a)xilinx.com> Code is taken from Linux kernel driver. Signed-off-by: Edgar E. Iglesias <edgar.iglesias(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Add missing function declaration to phy.h - Remove BIT macro and fix macro indentation - Remove comment about moving code to generic location - Fix typo register -> registers drivers/net/phy/Makefile | 1 + drivers/net/phy/phy.c | 3 + drivers/net/phy/ti.c | 200 +++++++++++++++++++++++++++++++++++++++++++++++ include/phy.h | 1 + 4 files changed, 205 insertions(+) create mode 100644 drivers/net/phy/ti.c diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index d096db87a276..9e4d4927e676 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -24,4 +24,5 @@ obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o +obj-$(CONFIG_PHY_TI) += ti.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index d7364ffc34f2..5633ec2402b0 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -484,6 +484,9 @@ int phy_init(void) #ifdef CONFIG_PHY_TERANETICS phy_teranetics_init(); #endif +#ifdef CONFIG_PHY_TI + phy_ti_init(); +#endif #ifdef CONFIG_PHY_VITESSE phy_vitesse_init(); #endif diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c new file mode 100644 index 000000000000..541a57f98028 --- /dev/null +++ b/drivers/net/phy/ti.c @@ -0,0 +1,200 @@ +/* + * TI PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ +#include <common.h> +#include <phy.h> + +/* TI DP83867 */ +#define DP83867_DEVADDR 0x1f + +#define MII_DP83867_PHYCTRL 0x10 +#define MII_DP83867_MICR 0x12 +#define DP83867_CTRL 0x1f + +/* Extended Registers */ +#define DP83867_RGMIICTL 0x0032 +#define DP83867_RGMIIDCTL 0x0086 + +#define DP83867_SW_RESET BIT(15) +#define DP83867_SW_RESTART BIT(14) + +/* MICR Interrupt bits */ +#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) +#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) +#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) +#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) +#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) +#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) +#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) +#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) +#define MII_DP83867_MICR_WOL_INT_EN BIT(3) +#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) +#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) +#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) + +/* RGMIICTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) +#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 + +/* RGMIIDCTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 + +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ + +/* MMD Access Control register fields */ +#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ +#define MII_MMD_CTRL_ADDR 0x0000 /* Address */ +#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ +#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ +#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ + +/** + * phy_read_mmd_indirect - reads data from the MMD registers + * @phydev: The PHY device bus + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * + * Description: it reads data from the MMD registers (clause 22 to access to + * clause 45) of the specified phy address. + * To read these registers we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Read reg 14 // Read MMD data + */ +int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr) +{ + int value = -1; + + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Read the content of the MMD's selected register */ + value = phy_read(phydev, addr, MII_MMD_DATA); + return value; +} + +/** + * phy_write_mmd_indirect - writes data to the MMD registers + * @phydev: The PHY device + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * @data: data to write in the MMD register + * + * Description: Write data from the MMD registers of the specified + * phy address. + * To write these registers we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Write reg 14 // Write MMD data + */ +void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr, u32 data) +{ + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Write the data into MMD's selected register */ + phy_write(phydev, addr, MII_MMD_DATA, data); +} + +/** + * phy_interface_is_rgmii - Convenience function for testing if a PHY interface + * is RGMII (all variants) + * @phydev: the phy_device struct + */ +static inline bool phy_interface_is_rgmii(struct phy_device *phydev) +{ + return phydev->interface >= PHY_INTERFACE_MODE_RGMII && + phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; +} + +/* User setting - can be taken from DTS */ +#define RX_ID_DELAY 8 +#define TX_ID_DELAY 0xa +#define FIFO_DEPTH 1 + +static int dp83867_config(struct phy_device *phydev) +{ + unsigned int val, delay; + int ret; + + /* Restart the PHY. */ + val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); + phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, + val | DP83867_SW_RESTART); + + if (phy_interface_is_rgmii(phydev)) { + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, + (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + if (ret) + return ret; + } + + if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && + (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { + val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83867_RGMII_TX_CLK_DELAY_EN | + DP83867_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83867_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83867_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr, val); + + delay = (RX_ID_DELAY | + (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + + phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, + DP83867_DEVADDR, phydev->addr, delay); + } + + genphy_config_aneg(phydev); + return 0; +} + +static struct phy_driver DP83867_driver = { + .name = "TI DP83867", + .uid = 0x2000a231, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &dp83867_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_ti_init(void) +{ + phy_register(&DP83867_driver); + return 0; +} diff --git a/include/phy.h b/include/phy.h index 3f826b66f71f..66cf61bdfb93 100644 --- a/include/phy.h +++ b/include/phy.h @@ -251,6 +251,7 @@ int phy_natsemi_init(void); int phy_realtek_init(void); int phy_smsc_init(void); int phy_teranetics_init(void); +int phy_ti_init(void); int phy_vitesse_init(void); int board_phy_config(struct phy_device *phydev); -- 2.5.0

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[U-Boot] ARM configurations with no MAINTAINERS file entries
by Albert ARIBAUD 10 Nov '15

10 Nov '15

Hello, An all-ARM buildman on current ARM or mainline ToT (commit 7bdf75ca) causes the following warnings: WARNING: no status info for 'am335x_gp_evm' WARNING: no maintainers for 'am335x_gp_evm' WARNING: no status info for 'dra74_evm' WARNING: no maintainers for 'dra74_evm' WARNING: no status info for 'am437x_sk_evm' WARNING: no maintainers for 'am437x_sk_evm' WARNING: no status info for 'am57xx_evm' WARNING: no maintainers for 'am57xx_evm' WARNING: no status info for 'dra72_evm' WARNING: no maintainers for 'dra72_evm' WARNING: no status info for 'ls1043ardb_sdcard' WARNING: no maintainers for 'ls1043ardb_sdcard' WARNING: no status info for 'hikey' WARNING: no maintainers for 'hikey' WARNING: no status info for 'nios2-generic' WARNING: no maintainers for 'nios2-generic' WARNING: no status info for 'am437x_gp_evm' WARNING: no maintainers for 'am437x_gp_evm' WARNING: no status info for 'ls1043ardb_nand' WARNING: no maintainers for 'ls1043ardb_nand' These boards have configs but no MAINTAINERS file entries. Cc:ing people most probably able to locate and if necessary create the adequate MAINTAINERS file. Amicalement, -- Albert.

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[U-Boot] Secure memory
by York Sun 10 Nov '15

10 Nov '15

Albert, I am trying to separate secure memory and non-secure memory for ARMv8. Before I go too far, I'd like to check with you to see if there is already some code implemented. Basically what I am trying to do is to mark most DDR memory non-secure because we have some non-secure masters such as SDHC DMA. I also want to reserve some memory for TrustZone application. In order to do that, I need to put the MMU tables in secure memory. I will need to modify common/board_f.c to process reserve_mmu() differently for secure and non-secure mode. Please let me know if running u-boot in non-secure mode is a bad idea. York

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[U-Boot] [PATCH 0/4] Add support for RapidIO boot
by jacquiot.aurelien＠gmail.com 10 Nov '15

10 Nov '15

From: Aurelien Jacquiot <a-jacquiot(a)ti.com> RapidIO is a high-performance packet-switched interconnect technology (www.rapidio.org) that can be used for messaging or memory transfers like Ethernet or PCIe. This feature adds the RapidIO boot functionality for slave mode (i.e. U-Boot does not fetch the images, images are pushed by a peer device/board). A new 'rio' command group allows to initialize and perform basic RapidIO operations. In addition the 'mem' group command has been enhanced in order to wait a given value in memory (to be notified that images have been pushed by peer). This feature has been firstly designed for TI KeyStone architecture and patches includes the RapidIO controller device driver for KeyStone architecture but it can used by any device/architecture that has hardware RapidIO support with DirectI/O. There just to add the corresponding RapidIO controller device driver. For more information, read the doc/README.rapidio documentation. Aurelien Jacquiot (4): cmd_mem.c: add a memory wait (mwait) command rapidio: add support for RapidIO boot rapidio: add documentation for RapidIO boot rapidio: add driver for TI KeyStone RapidIO Makefile | 1 + common/Kconfig | 7 +- common/Makefile | 1 + common/cmd_mem.c | 69 ++ common/cmd_rio.c | 260 ++++++++ configs/k2hk_evm_defconfig | 2 + doc/README.rapidio | 158 +++++ drivers/Kconfig | 2 + drivers/rapidio/Kconfig | 5 + drivers/rapidio/Makefile | 8 + drivers/rapidio/keystone_rio.c | 1374 ++++++++++++++++++++++++++++++++++++++++ drivers/rapidio/keystone_rio.h | 650 +++++++++++++++++++ include/rio.h | 382 +++++++++++ 13 files changed, 2918 insertions(+), 1 deletions(-) create mode 100644 common/cmd_rio.c create mode 100644 doc/README.rapidio create mode 100644 drivers/rapidio/Kconfig create mode 100644 drivers/rapidio/Makefile create mode 100644 drivers/rapidio/keystone_rio.c create mode 100644 drivers/rapidio/keystone_rio.h create mode 100644 include/rio.h

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[U-Boot] [PATCH] armv8: fsl-layerscape: added XFI protocol support for fsl_lsch3
by shh.xie＠gmail.com 10 Nov '15

10 Nov '15

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> This needed to init dpmac. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 2ab8da6..67c3a45 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -120,6 +120,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, lane_prtcl <= SGMII16) wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl); + if (lane_prtcl >= XFI1 && + lane_prtcl <= XFI8) + wriop_init_dpmac(sd, lane + 1, + (int)lane_prtcl); break; } #endif -- 2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v2] sh: Add SH7269 device and RSK2+SH7269 board
by giuliano.to＠qem.it 10 Nov '15

10 Nov '15

Hi, I want to ask you if there is a robust nommu-linux distribution for sh7269. Thanks Giuliano --------------------------------------------------------------------- Giuliano Tognon tel: +39-0444-440061 Software department fax: +39-0444-440229 Quality in Electronic Manufacturing srl e-mail: giuliano.to(a)qem.it Mail: SS11, Localitá Signolo web: www.qem.it 36054 Montebello Vic.no (VI) ITALY ---------------------------------------------------------------------

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[U-Boot] [PATCH] ARM64: zynqmp: Enable TI phy by default
by Michal Simek 10 Nov '15

10 Nov '15

Enable TI phy for Xilinx ZynqMP platform. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/xilinx_zynqmp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 36c11009fc3d..574f788500bf 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -182,6 +182,7 @@ # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHYLIB # define CONFIG_PHY_MARVELL +# define CONFIG_PHY_TI #endif /* I2C */ -- 2.5.0

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[U-Boot] [PATCH] net: phy: Add support for Texas Instruments DP83867
by Michal Simek 10 Nov '15

10 Nov '15

From: "Edgar E. Iglesias" <edgar.iglesias(a)xilinx.com> Code is taken from Linux kernel driver. Signed-off-by: Edgar E. Iglesias <edgar.iglesias(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/phy/Makefile | 1 + drivers/net/phy/phy.c | 3 + drivers/net/phy/ti.c | 205 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 209 insertions(+) create mode 100644 drivers/net/phy/ti.c diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index d096db87a276..9e4d4927e676 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -24,4 +24,5 @@ obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o +obj-$(CONFIG_PHY_TI) += ti.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index a6023f1033ec..c6046e4abc4e 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -484,6 +484,9 @@ int phy_init(void) #ifdef CONFIG_PHY_TERANETICS phy_teranetics_init(); #endif +#ifdef CONFIG_PHY_TI + phy_ti_init(); +#endif #ifdef CONFIG_PHY_VITESSE phy_vitesse_init(); #endif diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c new file mode 100644 index 000000000000..bb30450d7531 --- /dev/null +++ b/drivers/net/phy/ti.c @@ -0,0 +1,205 @@ +/* + * TI PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ +#include <common.h> +#include <phy.h> + +/* TI DP83867 */ +#define DP83867_DEVADDR 0x1f + +#define MII_DP83867_PHYCTRL 0x10 +#define MII_DP83867_MICR 0x12 +#define DP83867_CTRL 0x1f + +/* Extended Registers */ +#define DP83867_RGMIICTL 0x0032 +#define DP83867_RGMIIDCTL 0x0086 + +/* FIXME this is consolidated in the latest U-Boot version */ +#define BIT(x) (1UL << (x)) + +#define DP83867_SW_RESET (1 << 15) +#define DP83867_SW_RESTART (1 << 14) + +/* MICR Interrupt bits */ +#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) +#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) +#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) +#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) +#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) +#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) +#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) +#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) +#define MII_DP83867_MICR_WOL_INT_EN BIT(3) +#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) +#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) +#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) + +/* RGMIICTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) +#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 + +/* RGMIIDCTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 + +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ + +/* MMD Access Control register fields */ +#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ +#define MII_MMD_CTRL_ADDR 0x0000 /* Address */ +#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ +#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ +#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ + +/* FIXME: These indirect PHY writes should go into common code. */ + +/** + * phy_read_mmd_indirect - reads data from the MMD registers + * @phydev: The PHY device bus + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * + * Description: it reads data from the MMD registers (clause 22 to access to + * clause 45) of the specified phy address. + * To read these register we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Read reg 14 // Read MMD data + */ +int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr) +{ + int value = -1; + + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Read the content of the MMD's selected register */ + value = phy_read(phydev, addr, MII_MMD_DATA); + return value; +} + +/** + * phy_write_mmd_indirect - writes data to the MMD registers + * @phydev: The PHY device + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * @data: data to write in the MMD register + * + * Description: Write data from the MMD registers of the specified + * phy address. + * To write these register we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Write reg 14 // Write MMD data + */ +void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr, u32 data) +{ + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Write the data into MMD's selected register */ + phy_write(phydev, addr, MII_MMD_DATA, data); +} + +/** + * phy_interface_is_rgmii - Convenience function for testing if a PHY interface + * is RGMII (all variants) + * @phydev: the phy_device struct + */ +static inline bool phy_interface_is_rgmii(struct phy_device *phydev) +{ + return phydev->interface >= PHY_INTERFACE_MODE_RGMII && + phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; +} + +/* User setting - can be taken from DTS */ +#define RX_ID_DELAY 8 +#define TX_ID_DELAY 0xa +#define FIFO_DEPTH 1 + +static int dp83867_config(struct phy_device *phydev) +{ + unsigned int val, delay; + int ret; + + /* Restart the PHY. */ + val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); + phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, + val | DP83867_SW_RESTART); + + if (phy_interface_is_rgmii(phydev)) { + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, + (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + if (ret) + return ret; + } + + if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && + (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { + val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83867_RGMII_TX_CLK_DELAY_EN | + DP83867_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83867_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83867_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr, val); + + delay = (RX_ID_DELAY | + (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + + phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, + DP83867_DEVADDR, phydev->addr, delay); + } + + genphy_config_aneg(phydev); + return 0; +} + +static struct phy_driver DP83867_driver = { + .name = "TI DP83867", + .uid = 0x2000a231, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &dp83867_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_ti_init(void) +{ + phy_register(&DP83867_driver); + return 0; +} -- 2.5.0

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