November 2015 - U-Boot

[U-Boot] [PATCH 0/8] dm: pci: tegra: Convert Tegra PCI to driver model
by Simon Glass 12 Nov '15

12 Nov '15

This series converts all Tegra boards to use driver model for PCI. The net effect should be no change in functionality. A few additional features are added to make this possible: - Helper functions to support accessing 8- and 16-bit values within a 32-bit word - Fixing a build error for CONFIG_CMD_PCI_ENUM - Decoding the PCI ranges property such that configuration ranges are ignored - Supporting bus-master devices on boards where RAM does not start at 0 This series is tested on beaver. It is available at u-boot-dm/tegra-working. Simon Glass (8): dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig dm: pci: Avoid a driver model build error with CONFIG_CMD_PCI_ENUM RFC: dm: pci: Set up the SDRAM mapping correctly dm: pci: Support decoding ranges with duplicate entries dm: pci: Add functions to emulate 8- and 16-bit access dm: pci: Add a function to get the controller for a bus dm: pci: Add a function to find the regions for a PCI bus dm: tegra: pci: Convert tegra boards to driver model for PCI arch/arm/mach-tegra/Kconfig | 1 + common/cmd_pci.c | 4 + configs/apalis_t30_defconfig | 1 + configs/beaver_defconfig | 1 + configs/cardhu_defconfig | 1 + configs/jetson-tk1_defconfig | 1 + configs/trimslice_defconfig | 1 + drivers/pci/Kconfig | 10 ++ drivers/pci/pci-uclass.c | 99 ++++++++++- drivers/pci/pci_tegra.c | 402 +++++++++++++++---------------------------- include/configs/apalis_t30.h | 1 - include/configs/beaver.h | 1 - include/configs/cardhu.h | 1 - include/configs/jetson-tk1.h | 1 - include/configs/trimslice.h | 1 - include/fdtdec.h | 3 - include/pci.h | 51 ++++++ lib/fdtdec.c | 3 - 18 files changed, 305 insertions(+), 278 deletions(-) -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH] ARM: tegra: note that p2371-2180 is Jetson TX1
by Stephen Warren 12 Nov '15

12 Nov '15

From: Stephen Warren <swarren(a)nvidia.com> p2371-2180 is the engineering board name for the Jetson TX1 developer kit. Update Kconfig description and help text to make this obvious to everyone. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/mach-tegra/tegra210/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index b07363a4c38c..055fb124d8b7 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -19,12 +19,12 @@ config TARGET_P2371_0000 a GPIO expansion header, and an analog audio jack. config TARGET_P2371_2180 - bool "NVIDIA Tegra210 P2371-2180 board" + bool "NVIDIA Tegra210 P2371-2180 (Jetson TX1) board" help - P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The - combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB - micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and - two GPIO expansion headers. + P2371-2180 (Jetson TX1 developer kit) is a P2180 CPU board married + to a P2597 I/O board. The combination contains SoC, DRAM, eMMC, SD + card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host + port, SATA, PCIe, and two GPIO expansion headers. config TARGET_P2571 bool "NVIDIA Tegra210 P2571 base board" -- 1.9.1

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[U-Boot] Pull request: u-boot-blackfin
by Sonic Zhang 12 Nov '15

12 Nov '15

Hi Tom, Please pull the following patches for Blackfin from u-boot-blackfin into your tree. Thanks Sonic Zhang The following changes since commit 83bf005710a1e01341de5e2f44a3ce082717e313: arm: at91: reworked meesc board support (2015-11-03 14:21:32 +0100) are available in the git repository at: git://git.denx.de/u-boot-blackfin.git next for you to fetch changes up to e6779f8d5ac5ae77b4e8fd135a930403bbcb43c1: blackfin: Disable CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED in some cases (2015-11-04 16:43:01 +0800) ---------------------------------------------------------------- Tom Rini (1): blackfin: Disable CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED in some cases configs/bct-brettl2_defconfig | 1 - configs/bf526-ezbrd_defconfig | 1 - configs/bf527-ezkit-v2_defconfig | 1 - configs/bf527-ezkit_defconfig | 1 - configs/bf537-stamp_defconfig | 1 - configs/bf538f-ezkit_defconfig | 1 - 6 files changed, 6 deletions(-)

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[U-Boot] [PATCH v2 1/2] board_init: Change the logic to setup malloc_base
by Fabio Estevam 12 Nov '15

12 Nov '15

Prior to commit 5ba534d247d418 ("arm: Switch 32-bit ARM to using generic global_data setup") we used to have assembly code that configured the malloc_base address. Since this commit we use the board_init_f_mem() function in C to setup malloc_base address. In board_init_f_mem() there was a deliberate choice to support only early malloc() or full malloc() in SPL, but not both. Adapt this logic to allow both to be used, one after the other, in SPL. This issue has been observed in a Congatec board, where we need to retrieve the manufacturing information from the SPI NOR (the SPI API calls malloc) prior to configuring the DRAM. In this case as malloc_base was not configured we always see malloc to fail. With this change we are able to use malloc in SPL prior to DRAM gets initialized. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - Improve commit log (Simon) common/init/board_init.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/common/init/board_init.c b/common/init/board_init.c index e74b63b..1c6126d 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -50,8 +50,7 @@ ulong board_init_f_mem(ulong top) #endif arch_setup_gd(gd_ptr); -#if defined(CONFIG_SYS_MALLOC_F) && \ - (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYS_SPL_MALLOC_START)) +#if defined(CONFIG_SYS_MALLOC_F) top -= CONFIG_SYS_MALLOC_F_LEN; gd->malloc_base = top; #endif -- 1.9.1

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[U-Boot] [PATCH] dm: core: Kconfig: set OF_TRANSLATE default value to n
by Mugunthan V N 12 Nov '15

12 Nov '15

Based on the OF_TRANSLATE Kconfig description, this is required only on platforms with complex "ranges" in the DT nodes. For simpler platforms using SIMPLE_BUS should be sufficient. Since this a set to default y, simple bus is never used in any platform. So make the default value as "n" and enable OF_TRANSLATE only on required platform. Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> --- Tested this patch on TI DRA72 platform. --- drivers/core/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 15681df..74e0caf 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -123,7 +123,7 @@ config SPL_SIMPLE_BUS config OF_TRANSLATE bool "Translate addresses using fdt_translate_address" depends on DM && OF_CONTROL - default y + default n help If this option is enabled, the reg property will be translated using the fdt_translate_address() function. This is necessary -- 2.6.2.280.g74301d6

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[U-Boot] aarch64-linux-gnu-objdump gives all zeros in init_sequence_f[]
by Shawn Guo 12 Nov '15

12 Nov '15

Hi, I need some help to understand aarch64-linux-gnu-objdump output in .data section as below. It's part of the dump of u-boot image with command 'aarch64-linux-gnu-objdump -D -z u-boot'. Disassembly of section .data: 0000000035039898 <reserved_list>: <snip> 0000000035039948 <init_sequence_f>: 35039948: 00000000 .word 0x00000000 3503994c: 00000000 .word 0x00000000 35039950: 00000000 .word 0x00000000 35039954: 00000000 .word 0x00000000 35039958: 00000000 .word 0x00000000 3503995c: 00000000 .word 0x00000000 35039960: 00000000 .word 0x00000000 35039964: 00000000 .word 0x00000000 35039968: 00000000 .word 0x00000000 3503996c: 00000000 .word 0x00000000 35039970: 00000000 .word 0x00000000 35039974: 00000000 .word 0x00000000 35039978: 00000000 .word 0x00000000 3503997c: 00000000 .word 0x00000000 35039980: 00000000 .word 0x00000000 35039984: 00000000 .word 0x00000000 35039988: 00000000 .word 0x00000000 3503998c: 00000000 .word 0x00000000 35039990: 00000000 .word 0x00000000 35039994: 00000000 .word 0x00000000 35039998: 00000000 .word 0x00000000 3503999c: 00000000 .word 0x00000000 350399a0: 00000000 .word 0x00000000 350399a4: 00000000 .word 0x00000000 350399a8: 00000000 .word 0x00000000 350399ac: 00000000 .word 0x00000000 350399b0: 00000000 .word 0x00000000 350399b4: 00000000 .word 0x00000000 350399b8: 00000000 .word 0x00000000 350399bc: 00000000 .word 0x00000000 350399c0: 00000000 .word 0x00000000 350399c4: 00000000 .word 0x00000000 350399c8: 00000000 .word 0x00000000 350399cc: 00000000 .word 0x00000000 350399d0: 00000000 .word 0x00000000 350399d4: 00000000 .word 0x00000000 350399d8: 00000000 .word 0x00000000 350399dc: 00000000 .word 0x00000000 350399e0: 00000000 .word 0x00000000 350399e4: 00000000 .word 0x00000000 350399e8: 00000000 .word 0x00000000 350399ec: 00000000 .word 0x00000000 350399f0: 00000000 .word 0x00000000 350399f4: 00000000 .word 0x00000000 350399f8: 00000000 .word 0x00000000 350399fc: 00000000 .word 0x00000000 35039a00: 00000000 .word 0x00000000 35039a04: 00000000 .word 0x00000000 35039a08: 00000000 .word 0x00000000 35039a0c: 00000000 .word 0x00000000 35039a10: 00000000 .word 0x00000000 35039a14: 00000000 .word 0x00000000 35039a18: 00000000 .word 0x00000000 35039a1c: 00000000 .word 0x00000000 35039a20: 00000000 .word 0x00000000 35039a24: 00000000 .word 0x00000000 35039a28: 00000000 .word 0x00000000 35039a2c: 00000000 .word 0x00000000 35039a30: 00000000 .word 0x00000000 35039a34: 00000000 .word 0x00000000 35039a38: 00000000 .word 0x00000000 35039a3c: 00000000 .word 0x00000000 35039a40: 00000000 .word 0x00000000 35039a44: 00000000 .word 0x00000000 35039a48: 00000000 .word 0x00000000 35039a4c: 00000000 .word 0x00000000 The init_sequence_f[] is an array defined in U-Boot v2015.04 source common/board_f.c, which holds a bunch of pointers to critical initialization functions that have to be called during boot. Obviously, the array cannot be all zeros like what objdump tells. And I confirmed that by printing the pointers at run-time as below. init_sequence_f[0]: 0000000035004280 init_sequence_f[1]: 00000000350042a8 init_sequence_f[2]: 0000000035004380 init_sequence_f[3]: 00000000350042a0 init_sequence_f[4]: 00000000350044b8 init_sequence_f[5]: 0000000035004388 init_sequence_f[6]: 0000000035029538 init_sequence_f[7]: 000000003500675c init_sequence_f[8]: 000000003500447c init_sequence_f[9]: 000000003501d864 init_sequence_f[10]: 0000000035013778 init_sequence_f[11]: 0000000035004398 init_sequence_f[12]: 0000000035028ab8 init_sequence_f[13]: 0000000035004278 init_sequence_f[14]: 0000000035004270 init_sequence_f[15]: 000000003500445c init_sequence_f[16]: 0000000035001f20 init_sequence_f[17]: 0000000035004574 init_sequence_f[18]: 00000000350042b0 init_sequence_f[19]: 00000000350042c4 init_sequence_f[20]: 00000000350042cc init_sequence_f[21]: 00000000350042f8 init_sequence_f[22]: 00000000350044d4 init_sequence_f[23]: 000000003500430c init_sequence_f[24]: 0000000035004314 init_sequence_f[25]: 0000000035004330 init_sequence_f[26]: 0000000035004390 init_sequence_f[27]: 00000000350045bc init_sequence_f[28]: 0000000035004550 init_sequence_f[29]: 0000000035004518 init_sequence_f[30]: 0000000035004378 init_sequence_f[31]: 0000000035004428 init_sequence_f[32]: 00000000350043f0 Dumping an u-boot image built for 32-bit platform with arm-linux-gnueabi-objdump gives correct pointer values for the same array. 17853c7c <init_sequence_f>: 17853c7c: 17805600 strne r5, [r0, r0, lsl #12] 17853c80: 17805620 strne r5, [r0, r0, lsr #12] 17853c84: 1780574c strne r5, [r0, ip, asr #14] 17853c88: 178007ec strne r0, [r0, ip, ror #15] 17853c8c: 1780583c ; <UNDEFINED> instruction: 0x1780583c 17853c90: 17805834 ; <UNDEFINED> instruction: 0x17805834 17853c94: 1780315c ; <UNDEFINED> instruction: 0x1780315c 17853c98: 178015f4 ; <UNDEFINED> instruction: 0x178015f4 17853c9c: 17800890 ; <UNDEFINED> instruction: 0x17800890 17853ca0: 17801c0c strne r1, [r0, ip, lsl #24] 17853ca4: 178078f8 ; <UNDEFINED> instruction: 0x178078f8 17853ca8: 17805808 strne r5, [r0, r8, lsl #16] 17853cac: 17829564 strne r9, [r2, r4, ror #10] 17853cb0: 17816104 strne r6, [r1, r4, lsl #2] 17853cb4: 1783dea4 strne sp, [r3, r4, lsr #29] 17853cb8: 178055f8 ; <UNDEFINED> instruction: 0x178055f8 17853cbc: 17801a54 ; <UNDEFINED> instruction: 0x17801a54 17853cc0: 17805b4c strne r5, [r0, ip, asr #22] 17853cc4: 178057e0 strne r5, [r0, r0, ror #15] 17853cc8: 178057c8 strne r5, [r0, r8, asr #15] 17853ccc: 17802e20 strne r2, [r0, r0, lsr #28] 17853cd0: 17805910 usada8ne r0, r0, r9, r5 17853cd4: 17805628 strne r5, [r0, r8, lsr #12] 17853cd8: 17805640 strne r5, [r0, r0, asr #12] 17853cdc: 17805678 ; <UNDEFINED> instruction: 0x17805678 17853ce0: 17805680 strne r5, [r0, r0, lsl #13] 17853ce4: 178056b0 ; <UNDEFINED> instruction: 0x178056b0 17853ce8: 17805850 ; <UNDEFINED> instruction: 0x17805850 17853cec: 178056c8 strne r5, [r0, r8, asr #13] 17853cf0: 178056dc ; <UNDEFINED> instruction: 0x178056dc 17853cf4: 178056f8 ; <UNDEFINED> instruction: 0x178056f8 17853cf8: 17805768 strne r5, [r0, r8, ror #14] 17853cfc: 17805950 ; <UNDEFINED> instruction: 0x17805950 17853d00: 178058ec strne r5, [r0, ip, ror #17] 17853d04: 17805894 ; <UNDEFINED> instruction: 0x17805894 17853d08: 17805744 strne r5, [r0, r4, asr #14] 17853d0c: 17805798 ; <UNDEFINED> instruction: 0x17805798 17853d10: 17805770 ; <UNDEFINED> instruction: 0x17805770 17853d14: 00000000 andeq r0, r0, r0 Here are my questions: - Is this only because that ARM 64-bit toolchain doesn't show the real value of the pointers, or there are some linking or run-time magics to get these pointers correct when the binary is actually running? - Is this different behavior between ARM 32-bit and 64-bit toolchain expected? Or did I miss anything on 64-bit toolchain usage? Any hints or comments are much appreciated. Thanks, Shawn

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[U-Boot] [RFC PATCH v3 0/2] Make most DDR non-secure in MMU while keep a small block secure
by York Sun 12 Nov '15

12 Nov '15

This set is to change MMU tables so DDR is in non-secure mode that non-secure master such as SDHC DMA can access the data. To mix secure and non-secure MMU entries, the MMU tables themselves have to be in secure memory. A small portion memory is reserved at the end of DDR (before debug server and MC) to host secure application and the MMU tables. This is different from existing armv7 secure_ram_addr() solution. U-boot can run in the middle of memory if the memory is large. Having security memory at the very end simplifies MMU setup. This is RFC patch, verified on LS2085AQDS only. Changes in v3: Put ifdef around secure_ram Move defining CONFIG_SYS_MEM_RESERVE_SECURE to patch 2/2 Replace CONFIG_FSL_PPA_RESERVED_DRAM_SIZE with CONFIG_SYS_MEM_RESERVE_SECURE Sanity check gd->secure_ram before using Define CONFIG_SYS_MEM_RESERVE_SECURE in SoC header file Include ls1043ardb Modified commit message. Changes in v2: Do not use CONFIG_SYS_MEM_TOP_HIDE mechanism Move gd->arch.secure_ram to gd->secure_ram. Change the calculation of gd->secure_ram accordingly. Chnage commit message slightly accordingly. Changes in v1: Initial patch. Depends on http://patchwork.ozlabs.org/patch/540248/ York Sun (2): Reserve secure memory armv8: fsl-layerscape: Make DDR non secure in MMU tables README | 8 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 146 +++++++++++++++++++-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 + arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 +- board/freescale/ls1043ardb/ddr.c | 4 + board/freescale/ls2085a/ddr.c | 15 +++ board/freescale/ls2085aqds/ddr.c | 15 +++ board/freescale/ls2085ardb/ddr.c | 15 +++ common/board_f.c | 9 ++ common/cmd_bdinfo.c | 4 + include/asm-generic/global_data.h | 13 ++ 11 files changed, 233 insertions(+), 14 deletions(-) -- 1.7.9.5

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[U-Boot] [PULL] Please pull u-boot-nios/master
by Thomas Chou 12 Nov '15

12 Nov '15

Hi Tom, Please pull, The following changes since commit b375219e732f044e7f48b676fa4e36e7c29d81e1: ARM: uniphier: drop UniPhier specific SMP code (2015-11-11 23:35:35 +0900) are available in the git repository at: git://git.denx.de/u-boot-nios.git master for you to fetch changes up to 038be18fd95aa6283eafb85ceabc0b880976424b: nios2: add 3c120 and 10m50 devboards MAINTAINERS (2015-11-12 08:26:59 +0800) ---------------------------------------------------------------- Thomas Chou (15): dm: implement a MTD uclass cfi_flash: convert to driver model nios2: use cfi flash driver model nios2: add memcpy_fromio and memcpy_toio mtd: add altera quadspi driver nios2: nios2-generic: do not allocate rx buf in net.c net: zap altera_tse_initialize prototypes net: altera_tse: factor out stop mac func net: altera_tse: wait sgdma in altera_tse_recv net: altera_tse: add priv ops to prepare msgdma support net: altera_tse: add mSG-DMA support nios2: add 10m50 devboard support nios2: rename board nios2-generic to 3c120_devboard nios2: change README.nios2 to use 10m50 as template nios2: add 3c120 and 10m50 devboards MAINTAINERS arch/nios2/dts/10m50_devboard.dts | 267 ++++++++++++++++++++ arch/nios2/include/asm/io.h | 4 + board/altera/nios2/MAINTAINERS | 13 + configs/10m50_defconfig | 26 ++ .../{nios2-generic_defconfig => 3c120_defconfig} | 4 +- doc/README.nios2 | 14 +- doc/device-tree-bindings/mtd/altera_qspi.txt | 35 +++ doc/device-tree-bindings/mtd/mtd-physmap.txt | 88 +++++++ drivers/mtd/Kconfig | 32 +++ drivers/mtd/Makefile | 2 + drivers/mtd/altera_qspi.c | 273 +++++++++++++++++++++ drivers/mtd/cfi_flash.c | 78 ++++++ drivers/mtd/mtd-uclass.c | 21 ++ drivers/net/altera_tse.c | 237 +++++++++++++++--- drivers/net/altera_tse.h | 80 +++++- include/configs/10m50_devboard.h | 103 ++++++++ .../configs/{nios2-generic.h => 3c120_devboard.h} | 6 +- include/dm/uclass-id.h | 1 + include/flash.h | 3 + include/linux/mtd/mtd.h | 2 + include/mtd.h | 23 ++ include/netdev.h | 3 - 22 files changed, 1269 insertions(+), 46 deletions(-) create mode 100644 arch/nios2/dts/10m50_devboard.dts create mode 100644 board/altera/nios2/MAINTAINERS create mode 100644 configs/10m50_defconfig rename configs/{nios2-generic_defconfig => 3c120_defconfig} (88%) create mode 100644 doc/device-tree-bindings/mtd/altera_qspi.txt create mode 100644 doc/device-tree-bindings/mtd/mtd-physmap.txt create mode 100644 drivers/mtd/altera_qspi.c create mode 100644 drivers/mtd/mtd-uclass.c create mode 100644 include/configs/10m50_devboard.h rename include/configs/{nios2-generic.h => 3c120_devboard.h} (96%) create mode 100644 include/mtd.h

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[U-Boot] Enabling semantic parsers for host tools
by Michal Simek 12 Nov '15

12 Nov '15

Hi Masahiro, I just find out that u-boot doesn't call sparse for tools. Do you have any plan to support it? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [PATCH 1/2] board_init: Fix the logic to setup malloc_base
by Fabio Estevam 11 Nov '15

11 Nov '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Prior to commit 5ba534d247d418 ("arm: Switch 32-bit ARM to using generic global_data setup") we used to have assembly code that configured the malloc_base address. After this commit we use the board_init_f_mem() function in C to setup malloc_base address. However the ifdef logic has a problem that prevents malloc_base to be configured in the SPL case. This issue has been observed in a Congatec board, where we need to retrieve the manufacturing information from the SPI NOR (the SPI API calls malloc) prior to configuring the DRAM. In this case as malloc_base was not configured we always see malloc to fail. Adjust the ifdef logic so that malloc_base is always configured when CONFIG_SYS_MALLOC_F is set. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- common/init/board_init.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/common/init/board_init.c b/common/init/board_init.c index e74b63b..1c6126d 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -50,8 +50,7 @@ ulong board_init_f_mem(ulong top) #endif arch_setup_gd(gd_ptr); -#if defined(CONFIG_SYS_MALLOC_F) && \ - (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYS_SPL_MALLOC_START)) +#if defined(CONFIG_SYS_MALLOC_F) top -= CONFIG_SYS_MALLOC_F_LEN; gd->malloc_base = top; #endif -- 1.9.1

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