November 2015 - U-Boot

[U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
by Hans de Goede 23 Nov '15

23 Nov '15

According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads. Suggested-by: Chen-Yu Tsai <wens(a)csie.org> Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 09337a1..5c76275 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -220,11 +220,7 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31) -#if defined CONFIG_MACH_SUN8I_H3 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ -#else -#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */ -#endif #define AXI_GATE_OFFSET_DRAM 0 -- 2.5.0

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[U-Boot] [PATCH v2 00/13] dm: pci: Support native driver model calls
by Simon Glass 23 Nov '15

23 Nov '15

At present driver model supports PCI, but most of the code in U-Boot still uses the old API. This series changes the 'pci' command so that the new API is used. The old API is placed behind a 'compatibility' option. The overall goal is to deprecate the old API and remove all use of it. The auto-config and device finding will be the subject of future patches. Changes in v2: - Squash in the patch to fix pci_field_width() for 32-bit values - Rename '_byte' to class in pci_header_show() - Fix 'autoconfiguration' typo - Fix merge error in pciauto_setup_device() which removed needed code - Add a new patch to update the function comments - Add back the leading 0 in the printf() statements - Use 'return 0' instead of 'break' after the 's' command - Make pciinfo() static - Drop patch: pci: Move 'pci scan' code in with other commands - Move dm_pciauto_config_device() out of CONFIG_DM_PCI_COMPAT Simon Glass (13): pci: Use a common return in command processing pci: Use a separate variable for the bus number pci: Refactor the pciinfo() function dm: pci: Add a comment about how to find struct pci_controller dm: pci: Rename pci_auto.c to pci_auto_old.c dm: pci: Move common auto-config functions to a common file dm: pci: Reorder functions in cmd_pci.c pci: Tidy up function comments in cmd_pci.c pci: Use common functions to read/write config pci: Use a separate 'dev' variable for the PCI device pci: Move PCI header output code into its own function dm: pci: Convert 'pci' command to driver model dm: pci: Disable PCI compatibility functions by default arch/arm/mach-tegra/Kconfig | 1 + arch/x86/Kconfig | 3 + common/cmd_pci.c | 616 ++++++++++++++++++----------- configs/sandbox_defconfig | 1 + drivers/pci/Kconfig | 9 + drivers/pci/Makefile | 5 +- drivers/pci/pci_auto_common.c | 128 ++++++ drivers/pci/{pci_auto.c => pci_auto_old.c} | 116 ------ include/common.h | 1 - include/pci.h | 32 +- 10 files changed, 565 insertions(+), 347 deletions(-) create mode 100644 drivers/pci/pci_auto_common.c rename drivers/pci/{pci_auto.c => pci_auto_old.c} (81%) -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] MIPS: relocate_code global offset
by Kaushal Parikh 22 Nov '15

22 Nov '15

Hello, MIPS relocate_code function changes the global offset register (gp) with relocation offset. (from arch/mips/cpu/start.S) 221 PTR_ADD gp, s1 # adjust gp But further in same function C function 'flush_cache' is called. This function modifies gp, so the earlier modification to gp is undone. Furthermore, 'in_ram' is called from 'relocate_code'. In 'in_ram', there are references to gp 306 PTR_LA t1, __bss_start # t1 <-- __bss_start 307 PTR_LA t2, __bss_end # t2 <-- __bss_end 316 PTR_LA t9, board_init_r Because of gp modification by 'flush_cache', these will give older address (before relocation). Shouldn't these result in relocated addresses? Thanks Kaushal

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[U-Boot] Please pull u-boot-sunxi master
by Hans de Goede 22 Nov '15

22 Nov '15

Hi Tom, The main feature of this pull-req is support for the H3 SoC, technically the patches for this were posted just outside the merge window. But they have been available off-list for a while longer and they do not make any changes to existing code-paths, so they do not carry much risk for regressions. Given the popularity of H3 boards I believe that it is important to get basic support in place now. Esp. to keep the contributions from various people working on H3 support flowing. I'm very happy to see that various people are contributing to this and I do not want to discourage them by taking for-ever to merge this :) Hence I'm "sneaking" in the H3 support in this pull-req. Besides the H3 support there are 2 patches to enable DFU support and the addition of a new board. The following changes since commit 1d149eddcc0661b683002f76a8240491eba00dbb: dm: Add timeline and guide for porting serial drivers (2015-11-20 13:59:54 -0500) are available in the git repository at: http://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to aa56cb374de8ae83f3280fdd6c280724228b86d7: sunxi: Add support for the Lamobo R1 board (2015-11-22 11:43:58 +0100) ---------------------------------------------------------------- Hans de Goede (2): sunxi: Add H3 dts[i] files sunxi: Add support for Orangepi Plus and Orangepi PC boards Jelle de Jong (1): sunxi: Add support for the Lamobo R1 board Jens Kuske (2): sunxi: Add basic H3 support sunxi: Add H3 DRAM initialization support Siarhei Siamashka (3): sunxi: Enable DFU for RAM sunxi: musb: Implement dfu_usb_get_reset() sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3 arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/board.c | 4 + arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 +- arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 + arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c | 469 +++++++++++++++++++ arch/arm/dts/Makefile | 4 + arch/arm/dts/sun7i-a20-lamobo-r1.dts | 297 ++++++++++++ arch/arm/dts/sun8i-h3-orangepi-pc.dts | 106 +++++ arch/arm/dts/sun8i-h3-orangepi-plus.dts | 121 +++++ arch/arm/dts/sun8i-h3.dtsi | 595 ++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +- arch/arm/include/asm/arch-sunxi/dram.h | 2 + arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 185 ++++++++ arch/arm/include/asm/arch-sunxi/gpio.h | 1 + board/sunxi/Kconfig | 8 +- board/sunxi/MAINTAINERS | 7 + configs/Lamobo_R1_defconfig | 16 + configs/orangepi_pc_defconfig | 15 + configs/orangepi_plus_defconfig | 15 + drivers/power/Kconfig | 5 +- drivers/usb/musb-new/sunxi.c | 12 + include/configs/sun8i.h | 2 + include/configs/sunxi-common.h | 30 +- 23 files changed, 1902 insertions(+), 11 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c create mode 100644 arch/arm/dts/sun7i-a20-lamobo-r1.dts create mode 100644 arch/arm/dts/sun8i-h3-orangepi-pc.dts create mode 100644 arch/arm/dts/sun8i-h3-orangepi-plus.dts create mode 100644 arch/arm/dts/sun8i-h3.dtsi create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h create mode 100644 configs/Lamobo_R1_defconfig create mode 100644 configs/orangepi_pc_defconfig create mode 100644 configs/orangepi_plus_defconfig Regards, Hans

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[U-Boot] [PATCH v2 0/4] vexpress64 fixes and NOR support
by Ryan Harkin 22 Nov '15

22 Nov '15

This series is a rework or repost of a few patches to fix vexpress64 FVP support and to add NOR flash support to the boards that support it, namely, Juno and the FVP AEMv8 models. The FVP Foundation model does not simulate NOR flash, but will fail gracefully with this series. The first patch was originally posted by Linus Walleij, but I took it over with his permission when it needed reworking. [PATCH v2 1/4] vexpress64: compile Juno PCIe conditionally [PATCH v2 2/4] vexpress64: use 2nd DRAM bank only on juno [PATCH v2 3/4] vexpress64: remove #error [PATCH v2 4/4] vexpress64: store env in flash board/armltd/vexpress64/Makefile | 3 ++- board/armltd/vexpress64/pcie.c | 2 -- board/armltd/vexpress64/vexpress64.c | 9 +++++++++ configs/vexpress_aemv8a_dram_defconfig | 1 - configs/vexpress_aemv8a_semi_defconfig | 1 - include/configs/vexpress_aemv8a.h | 54 ++++++++++++++++++++++++++++--------------------------

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[U-Boot] [PATCH] Juno: don't print PCI debug information by default
by Andre Przywara 22 Nov '15

22 Nov '15

On a Juno r1 the PCI controller init routine outputs the rather boring ATR entry information. Do this only with DEBUG defined to avoid cluttering the user's terminal. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- board/armltd/vexpress64/pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 7b999e8..eb23dd5 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -87,7 +87,7 @@ void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH); writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM); - printf("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n", + debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n", src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr, ((u64)1) << window_size, trsl_param); } -- 2.5.1

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[U-Boot] [PATCH 01/17] tricorder: rewrite tricordereeprom command
by Marek Vasut 22 Nov '15

22 Nov '15

From: Andreas Bießmann <andreas.devel(a)googlemail.com> This rewrite uses lately promoted eeprom_init(int) function to choose the right I2C bus when writing data to the EEPROM. Signed-off-by: Andreas Bießmann <andreas.devel(a)googlemail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: Heiko Schocher <hs(a)denx.de> --- board/corscience/tricorder/tricorder-eeprom.c | 36 +++++++-------------------- 1 file changed, 9 insertions(+), 27 deletions(-) diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c index 1c74a0f..340a009 100644 --- a/board/corscience/tricorder/tricorder-eeprom.c +++ b/board/corscience/tricorder/tricorder-eeprom.c @@ -77,17 +77,13 @@ static int handle_eeprom_v1(struct tricorder_eeprom *eeprom) int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom) { -#ifdef CONFIG_SYS_EEPROM_BUS_NUM unsigned int bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif memset(eeprom, 0, TRICORDER_EEPROM_SIZE); i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE); -#ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); -#endif if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) { warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC, @@ -138,9 +134,6 @@ int tricorder_eeprom_write(unsigned devaddr, const char *name, int ret; unsigned char *p; int i; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - unsigned int bus; -#endif memset(eeprom, 0, TRICORDER_EEPROM_SIZE); memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE); @@ -172,33 +165,23 @@ int tricorder_eeprom_write(unsigned devaddr, const char *name, print_buffer(0, &eeprom, 1, sizeof(eeprom), 16); #endif -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif + eeprom_init(CONFIG_SYS_EEPROM_BUS_NUM); - /* do page write to the eeprom */ - for (i = 0, p = (unsigned char *)&eeprom; - i < sizeof(eeprom); - i += 32, p += 32) { - ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - p, min(sizeof(eeprom) - i, 32)); - if (ret) - break; - udelay(5000); /* 5ms write cycle timing */ - } + ret = eeprom_write(devaddr, 0, (unsigned char *)&eeprom, + TRICORDER_EEPROM_SIZE); + if (ret) + printf("Tricorder: Could not write EEPROM content!\n"); - ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify, + ret = eeprom_read(devaddr, 0, (unsigned char *)&eeprom_verify, TRICORDER_EEPROM_SIZE); + if (ret) + printf("Tricorder: Could not read EEPROM content!\n"); if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) { printf("Tricorder: Could not verify EEPROM content!\n"); ret = 1; } -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - i2c_set_bus_num(bus); -#endif return ret; } @@ -206,7 +189,7 @@ int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc == 3) { ulong dev_addr = simple_strtoul(argv[2], NULL, 16); - eeprom_init(); + if (strcmp(argv[1], "read") == 0) { int rcode; @@ -220,7 +203,6 @@ int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *version = argv[4]; char *serial = argv[5]; char *interface = NULL; - eeprom_init(); if (argc == 7) interface = argv[6]; -- 2.1.4

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[U-Boot] [PATCH] ARM: keystone2: configs: Correct burn_uboot_sp erase size
by Franklin S Cooper Jr 22 Nov '15

22 Nov '15

The NOR flash on Keystone 2 evms has a u-boot-spl partition size of 0x80000. Currently burn_uboot_spi will erase 0x100000 from the spi NOR which will cause a partial erase of the misc partition. Fix this by correcting the erase size. Signed-off-by: Franklin S Cooper Jr <fcooper(a)ti.com> --- include/configs/ti_armv7_keystone2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 2b2c060..b4f365b 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -252,7 +252,7 @@ "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ - "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ + "burn_uboot_spi=sf probe; sf erase 0 0x80000; " \ "sf write ${loadaddr} 0 ${filesize}\0" \ "burn_uboot_nand=nand erase 0 0x100000; " \ "nand write ${loadaddr} 0 ${filesize}\0" \ -- 2.6.2

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[U-Boot] [PATCH] ARM: dra7x/am57x: Remove pin input/output config from WAKEUP pins
by Franklin S Cooper Jr 22 Nov '15

22 Nov '15

The WAKEUP_X pins are always an input no matter the pinmux mode. However, the 18th bit that typical configures a pin as an input is considered reserved for the WAKEUP_X pins. Therefore, for any WAKEUP pin remove any configuration that sets that pin as an input. Since those pins are only inputs remove any output configuration from those pins. Signed-off-by: Franklin S Cooper Jr <fcooper(a)ti.com> --- board/ti/am57xx/mux_data.h | 8 ++++---- board/ti/dra7xx/mux_data.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index 23f22a0..3c007b7 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -255,10 +255,10 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ - {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */ - {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */ - {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */ - {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */ + {WAKEUP0, (M0 | PULL_UP)}, /* Wakeup0.Wakeup0 */ + {WAKEUP1, (M0)}, /* Wakeup1.Wakeup1 */ + {WAKEUP2, (M0)}, /* Wakeup2.Wakeup2 */ + {WAKEUP3, (M0 | PULL_UP)}, /* Wakeup3.Wakeup3 */ {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */ {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */ diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index bf40144..1bfb362 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -372,7 +372,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */ {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */ {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */ - {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */ + {WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */ }; #ifdef CONFIG_IODELAY_RECALIBRATION -- 2.6.2

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[U-Boot] Coldfire toolchains
by Angelo Dureghello 22 Nov '15

22 Nov '15

Dear all, for who could be interested, here you can find two working toolchains, for i686 and x86_64 hosts. http://www.denx.de/wiki/U-Boot/ColdFireNotes In my case, compiling for mcf5307, none of the official kernel.org toolchains was producing correct code, so i did some adjustments over them. I also set up here locally the kernel.org "buildall" script, so in case i can produce some additional versions. Best regards, Angelo Dureghello

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