October 2015 - U-Boot

[U-Boot] [PATCH v1 00/12] Bring up rk3036 uboot
by Lin Huang 27 Oct '15

27 Oct '15

This series patch bring up rk3036 uboot, since rk3036 only 8K size SRAM, not enough space to add ddr driver, so you should use rockchip bootmerge script to merge ddr.bin and u-boot-dtb.bin. Lin Huang (12): rockchip: define SUPPORT_SPL and SPL config in RK3288 config rockchip: implement rockchip timer init function rockchip: serial driver support rk3036 rockchip: Bring in RK3036 device tree file includes and bindings rockchip: rk3036: Add clock driver rockchip: rk3036: Add header files for GRF rockchip: rk3036: Add Soc reset driver rockchip: rk3036: Add a simple syscon driver rockchip: rk3036: Add pinctrl driver rockchip: Add an rk3036 MMC driver rockchip: rk3036: Add core Soc start-up code rockchip: Add basic support for evb-rk3036 board arch/arm/Kconfig | 2 - arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 +++ arch/arm/dts/rk3036.dtsi | 427 +++++++++++++++++++ arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 53 +++ arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 491 ++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/hardware.h | 2 +- arch/arm/include/asm/arch-rockchip/timer.h | 18 + arch/arm/mach-rockchip/Kconfig | 12 +- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/board.c | 19 +- arch/arm/mach-rockchip/common.c | 11 + arch/arm/mach-rockchip/rk3036/Kconfig | 11 + arch/arm/mach-rockchip/rk3036/Makefile | 8 + arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + board/evb_rk3036/evb_rk3036/Kconfig | 15 + board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 + board/evb_rk3036/evb_rk3036/evb_rk3036.c | 7 + configs/evb-rk3036_defconfig | 41 ++ drivers/clk/Makefile | 1 + drivers/clk/clk_rk3036.c | 522 ++++++++++++++++++++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_3036_dw_mmc.c | 479 ++++++++++++++++++++++ drivers/pinctrl/Kconfig | 18 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3036.c | 276 +++++++++++++ drivers/serial/serial_rockchip.c | 2 +- include/configs/evb_rk3036.h | 12 + include/configs/rk3036_common.h | 116 ++++++ include/configs/rk3288_common.h | 3 +- include/dt-bindings/clock/rk3036-cru.h | 186 +++++++++ 34 files changed, 2858 insertions(+), 8 deletions(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 arch/arm/dts/rk3036.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3036.h create mode 100644 arch/arm/include/asm/arch-rockchip/timer.h create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/Makefile create mode 100644 arch/arm/mach-rockchip/rk3036/reset_rk3036.c create mode 100644 arch/arm/mach-rockchip/rk3036/syscon_rk3036.c create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 drivers/clk/clk_rk3036.c create mode 100644 drivers/mmc/rockchip_3036_dw_mmc.c create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c create mode 100644 include/configs/evb_rk3036.h create mode 100644 include/configs/rk3036_common.h create mode 100644 include/dt-bindings/clock/rk3036-cru.h -- 1.9.1

4 41

[U-Boot] [PATCH v5 00/14] sf: Tunning spi-flash layer
by Jagan Teki 27 Oct '15

27 Oct '15

The main intension of these patches is to separate the core flash code and flash-to-spi drivers interface code. This gives proper enhancement for adding new features like MTD Core, SPI NOR framework. sf_ops: Core spi-flash handling (non-dm, becuase sharing code) sf_probe: flash-to-spi driver interface (dm driven) Changes for v5, v4: - Rebase to master Jagan Teki (14): sf: spi_flash_validate_params => spi_flash_scan sf: Move spi_flash_scan code to sf_ops sf: Move read_id code to sf_ops sf: probe: Code cleanup sf: Use static for file-scope functions sf: Fix Makefile sf: Use simple name for register access functions sf: Use flash function pointers in dm_spi_flash_ops sf: Flash power up read-only based on idcode0 sf: Use static for file-scope functions sf: Remove unneeded header includes sf: probe: Use spi_flash_scan in dm-spi-flash sf: Re-factorize spi_flash_probe_tail code dm-sf: Re-factorize spi_flash_std_probe code drivers/mtd/spi/Makefile | 6 +- drivers/mtd/spi/sf_internal.h | 52 ++--- drivers/mtd/spi/sf_ops.c | 380 ++++++++++++++++++++++++++++++++-- drivers/mtd/spi/sf_probe.c | 459 ++++++------------------------------------ include/spi_flash.h | 13 -- 5 files changed, 436 insertions(+), 474 deletions(-) -- 1.9.1

1 0

[U-Boot] [PATCH 0/3] arm: mvebu: a38x: Cleanup serdes/DDR training
by Kevin Smith 27 Oct '15

27 Oct '15

The a38x serdes init and DDR training code was imported more or less as-is from Marvell's code with formatting cleanup changes. This is a first pass at cleaning up the code itself. The topology data for several boards that are not supported by mainline U-Boot are removed. Also removed is a mechanism in the drivers themselves for changing the board-specified configuration based on values loaded from an on-board EEPROM. This belongs in the board file instead of the driver, and is not needed for the db-88f6820-gp development board, so is completely removed. Kevin Smith (3): arm: mvebu: a38x: Remove unsupported topologies arm: mvebu: a38x: Add const to some function calls arm: mvebu: a38x: serdes specification cleanup arch/arm/mach-mvebu/serdes/a38x/Makefile | 1 - arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 13 +- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 2 +- .../serdes/a38x/high_speed_env_spec-38x.c | 1 - .../mach-mvebu/serdes/a38x/high_speed_env_spec.c | 103 +- .../mach-mvebu/serdes/a38x/high_speed_env_spec.h | 8 +- .../serdes/a38x/high_speed_topology_spec-38x.c | 1009 -------------------- .../serdes/a38x/high_speed_topology_spec.h | 124 --- arch/arm/mach-mvebu/serdes/a38x/seq_exec.c | 1 - arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 151 --- arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 2 - board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 17 + drivers/ddr/marvell/a38x/ddr3_a38x.h | 5 - drivers/ddr/marvell/a38x/ddr3_init.c | 72 -- 14 files changed, 65 insertions(+), 1444 deletions(-) delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec-38x.c delete mode 100644 arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec.h -- 2.4.6

3 5

[U-Boot] [PATCH] zynq: sdhci: Define max clock by macro
by Michal Simek 27 Oct '15

27 Oct '15

zc1571 with silicon can operate on 200MHz maximum frequency. Setup this frequency by default and fix setting for ep108. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/mmc/zynq_sdhci.c | 2 +- include/configs/xilinx_zynqmp.h | 3 +++ include/configs/xilinx_zynqmp_ep.h | 1 + include/configs/zynq-common.h | 1 + 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index c69f5d4e2d44..e169b774932a 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -29,7 +29,7 @@ int zynq_sdhci_init(phys_addr_t regbase) SDHCI_QUIRK_BROKEN_R1B; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - add_sdhci(host, 52000000, 52000000 >> 9); + add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 52000000 >> 9); return 0; } diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 32ee0fc149ff..921a3d48c045 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -96,6 +96,9 @@ # define CONFIG_SDHCI # define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC +# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ +# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000 +# endif #endif #if defined(CONFIG_ZYNQ_SDHCI) diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index e476eb1b496d..78e7a9dbaa3e 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -20,6 +20,7 @@ #define CONFIG_ZYNQ_SERIAL_UART0 #define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #define CONFIG_ZYNQ_I2C0 #define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQ_EEPROM diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 66b1e699c80b..d67df7b2131c 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -95,6 +95,7 @@ # define CONFIG_SDHCI # define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC +# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #endif #ifdef CONFIG_ZYNQ_USB -- 2.5.0

1 0

[U-Boot] [PATCH 1/4] taihu: Remove
by Tom Rini 27 Oct '15

27 Oct '15

This board has not compiled for me for quite some time due to size constraints, remove. Cc: John Otken <jotken(a)softadvances.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- board/amcc/taihu/Kconfig | 16 - board/amcc/taihu/MAINTAINERS | 6 - board/amcc/taihu/Makefile | 8 - board/amcc/taihu/flash.c | 1063 ------------------------------------------ board/amcc/taihu/lcd.c | 237 ---------- board/amcc/taihu/taihu.c | 180 ------- board/amcc/taihu/update.c | 116 ----- configs/taihu_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/taihu.h | 307 ------------ 10 files changed, 1 insertion(+), 1936 deletions(-) delete mode 100644 board/amcc/taihu/Kconfig delete mode 100644 board/amcc/taihu/MAINTAINERS delete mode 100644 board/amcc/taihu/Makefile delete mode 100644 board/amcc/taihu/flash.c delete mode 100644 board/amcc/taihu/lcd.c delete mode 100644 board/amcc/taihu/taihu.c delete mode 100644 board/amcc/taihu/update.c delete mode 100644 configs/taihu_defconfig delete mode 100644 include/configs/taihu.h diff --git a/board/amcc/taihu/Kconfig b/board/amcc/taihu/Kconfig deleted file mode 100644 index faafb08..0000000 --- a/board/amcc/taihu/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -if TARGET_TAIHU - -config SYS_BOARD - default "taihu" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "taihu" - -config DISPLAY_BOARDINFO - bool - default y - -endif diff --git a/board/amcc/taihu/MAINTAINERS b/board/amcc/taihu/MAINTAINERS deleted file mode 100644 index 2efc254..0000000 --- a/board/amcc/taihu/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TAIHU BOARD -M: John Otken <jotken(a)softadvances.com> -S: Maintained -F: board/amcc/taihu/ -F: include/configs/taihu.h -F: configs/taihu_defconfig diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile deleted file mode 100644 index 65606fe..0000000 --- a/board/amcc/taihu/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = taihu.o flash.o lcd.o update.o diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c deleted file mode 100644 index 0780488..0000000 --- a/board/amcc/taihu/flash.c +++ /dev/null @@ -1,1063 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh(a)net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define CONFIG_SYS_FLASH_CHAR_SIZE unsigned char -#define CONFIG_SYS_FLASH_CHAR_ADDR0 (0x0aaa) -#define CONFIG_SYS_FLASH_CHAR_ADDR1 (0x0555) -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef FLASH_BASE1_PRELIM -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1=0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - if (size_b0) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - /* Also protect sector containing initial power-up instruction */ - /* (flash_protect() checks address range - other call ignored) */ - (void)flash_protect(FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); - - flash_info[0].size = size_b0; - } -#ifdef FLASH_BASE1_PRELIM - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2; - - if (flash_info[1].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", - size_b1, size_b1 << 20); - } - - if (size_b1) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]); - flash_info[1].size = size_b1; - } -#endif - return (size_b0 + size_b1); -} - -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000*2); - } - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000*2); - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMLV128U: - printf("AM29LV128U (128 Mbit * 2, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - case FLASH_S29GL128N: - printf ("S29GL128N (256 Mbit, uniform sector size)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef FLASH_BASE1_PRELIM -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - if ((ulong)addr == FLASH_BASE1_PRELIM) { - return flash_get_size_2(addr, info); - } else { - return flash_get_size_1(addr, info); - } -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return 0; /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000 * 2); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return info->size; -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef FLASH_BASE1_PRELIM -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return rc; - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return rc; - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return 0; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef FLASH_BASE1_PRELIM -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return 2; - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - } - - return 0; -} - -#ifdef FLASH_BASE1_PRELIM - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - CONFIG_SYS_FLASH_CHAR_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - udelay(1000); - - value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_CHAR_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_CHAR_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return 0; /* no or unknown flash */ - } - - value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[2]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_MIRROR: - if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_2 - && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) { - info->flash_id += FLASH_AMLV128U; - info->sector_count = 256; - info->size = 0x01000000; - } else if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_2 - && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) { - info->flash_id += FLASH_S29GL128N; - info->sector_count = 128; - info->size = 0x01000000; - } - else - info->flash_id = FLASH_UNKNOWN; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00020000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[4] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; - return info->size; -} - -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while (((CONFIG_SYS_FLASH_WORD_SIZE)addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x50505050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return 2; - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA0A0A0A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - } - - return 0; -} - -#endif /* FLASH_BASE1_PRELIM */ diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c deleted file mode 100644 index c7c7fa4..0000000 --- a/board/amcc/taihu/lcd.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#define LCD_CMD_ADDR 0x50100002 -#define LCD_DATA_ADDR 0x50100003 -#define LCD_BLK_CTRL CPLD_REG1_ADDR - -static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT"; -static int addr_flag = 0x80; - -static void lcd_bl_ctrl(char val) -{ - out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val); -} - -static void lcd_putc(int val) -{ - int i = 100; - char addr; - - while (i--) { - if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ - udelay(50); - break; - } - udelay(50); - } - - if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { - printf("LCD is busy\n"); - return; - } - - addr = in_8((u8 *) LCD_CMD_ADDR); - udelay(50); - if ((addr != 0) && (addr % 0x10 == 0)) { - addr_flag ^= 0x40; - out_8((u8 *) LCD_CMD_ADDR, addr_flag); - } - - udelay(50); - out_8((u8 *) LCD_DATA_ADDR, val); - udelay(50); -} - -static void lcd_puts(char *s) -{ - char *p = s; - int i = 100; - - while (i--) { - if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ - udelay(50); - break; - } - udelay(50); - } - - if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { - printf("LCD is busy\n"); - return; - } - - while (*p) - lcd_putc(*p++); -} - -static void lcd_put_logo(void) -{ - int i = 100; - char *p = amcc_logo; - - while (i--) { - if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ - udelay(50); - break; - } - udelay(50); - } - - if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { - printf("LCD is busy\n"); - return; - } - - out_8((u8 *) LCD_CMD_ADDR, 0x80); - while (*p) - lcd_putc(*p++); -} - -int lcd_init(void) -{ - puts("LCD: "); - out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */ - udelay(50); - out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */ - udelay(50); - out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */ - udelay(2000); - out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */ - udelay(50); - lcd_bl_ctrl(0x02); /* set backlight on */ - lcd_put_logo(); - puts("ready\n"); - - return 0; -} - -static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - out_8((u8 *) LCD_CMD_ADDR, 0x01); - udelay(2000); - - return 0; -} - -static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_puts(argv[1]); - - return 0; -} - -static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_putc((char)argv[1][0]); - - return 0; -} - -static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong count; - ulong dir; - char cur_addr; - - if (argc < 3) - return cmd_usage(cmdtp); - - count = simple_strtoul(argv[1], NULL, 16); - if (count > 31) { - printf("unable to shift > 0x20\n"); - count = 0; - } - - dir = simple_strtoul(argv[2], NULL, 16); - cur_addr = in_8((u8 *) LCD_CMD_ADDR); - udelay(50); - - if (dir == 0x0) { - if (addr_flag == 0x80) { - if (count >= (cur_addr & 0xf)) { - out_8((u8 *) LCD_CMD_ADDR, 0x80); - udelay(50); - count = 0; - } - } else { - if (count >= ((cur_addr & 0x0f) + 0x0f)) { - out_8((u8 *) LCD_CMD_ADDR, 0x80); - addr_flag = 0x80; - udelay(50); - count = 0x0; - } else if (count >= ( cur_addr & 0xf)) { - count -= cur_addr & 0xf ; - out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf); - addr_flag = 0x80; - udelay(50); - } - } - } else { - if (addr_flag == 0x80) { - if (count >= (0x1f - (cur_addr & 0xf))) { - count = 0x0; - addr_flag = 0xc0; - out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf); - udelay(50); - } else if ((count + (cur_addr & 0xf ))>= 0x0f) { - count = count + (cur_addr & 0xf) - 0x0f; - addr_flag = 0xc0; - out_8((u8 *) LCD_CMD_ADDR, 0xc0); - udelay(50); - } - } else if ((count + (cur_addr & 0xf )) >= 0x0f) { - count = 0x0; - out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F); - udelay(50); - } - } - while (count--) { - if (dir == 0) - out_8((u8 *) LCD_CMD_ADDR, 0x10); - else - out_8((u8 *) LCD_CMD_ADDR, 0x14); - udelay(50); - } - - return 0; -} - -U_BOOT_CMD( - lcd_cls, 1, 1, do_lcd_clear, - "lcd clear display", - "" -); - -U_BOOT_CMD( - lcd_puts, 2, 1, do_lcd_puts, - "display string on lcd", - "<string> - <string> to be displayed" -); - -U_BOOT_CMD( - lcd_putc, 2, 1, do_lcd_putc, - "display char on lcd", - "<char> - <char> to be displayed" -); - -U_BOOT_CMD( - lcd_cur, 3, 1, do_lcd_cur, - "shift cursor on lcd", - "<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n" - " <count> - 0..31\n" - " <dir> - 0=backward 1=forward" -); diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c deleted file mode 100644 index fcb8936..0000000 --- a/board/amcc/taihu/taihu.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * (C) Copyright 2005-2007 - * Beijing UD Technology Co., Ltd., taihusupport(a)amcc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <spi.h> -#include <netdev.h> -#include <asm/ppc4xx-gpio.h> - -extern int lcd_init(void); - -/* - * board_early_init_f - */ -int board_early_init_f(void) -{ - lcd_init(); - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); - mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ - mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - - mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ - mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); - - /* - * Configure CPC0_PCI to enable PerWE as output - * and enable the internal PCI arbiter - */ - mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Taihu - AMCC PPC405EP Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[]) -{ - char stat; - int i; - - stat = in_8((u8 *) CPLD_REG0_ADDR); - printf("SW2 status: "); - for (i=0; i<4; i++) /* 4-position */ - printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off"); - printf("\n"); - return 0; -} - -U_BOOT_CMD ( - sw2_stat, 1, 1, do_sw_stat, - "show status of switch 2", - "" -); - -static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[]) -{ - int led_no; - - if (argc != 3) - return cmd_usage(cmd_tp); - - led_no = simple_strtoul(argv[1], NULL, 16); - if (led_no != 1 && led_no != 2) - return cmd_usage(cmd_tp); - - if (strcmp(argv[2],"off") == 0x0) { - if (led_no == 1) - gpio_write_bit(30, 1); - else - gpio_write_bit(31, 1); - } else if (strcmp(argv[2],"on") == 0x0) { - if (led_no == 1) - gpio_write_bit(30, 0); - else - gpio_write_bit(31, 0); - } else { - return cmd_usage(cmd_tp); - } - - return 0; -} - -U_BOOT_CMD ( - led_ctl, 3, 1, do_led_ctl, - "make led 1 or 2 on or off", - "<led_no> <on/off> - make led <led_no> on/off,\n" - "\tled_no is 1 or 2" -); - -#define SPI_CS_GPIO0 0 -#define SPI_SCLK_GPIO14 14 -#define SPI_DIN_GPIO15 15 -#define SPI_DOUT_GPIO16 16 - -void spi_scl(int bit) -{ - gpio_write_bit(SPI_SCLK_GPIO14, bit); -} - -void spi_sda(int bit) -{ - gpio_write_bit(SPI_DOUT_GPIO16, bit); -} - -unsigned char spi_read(void) -{ - return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio_write_bit(SPI_CS_GPIO0, 1); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio_write_bit(SPI_CS_GPIO0, 0); -} - -#ifdef CONFIG_PCI -static unsigned char int_lines[32] = { - 29, 30, 27, 28, 29, 30, 25, 27, - 29, 30, 27, 28, 29, 30, 27, 28, - 29, 30, 27, 28, 29, 30, 27, 28, - 29, 30, 27, 28, 29, 30, 27, 28}; - -static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = int_lines[PCI_DEV(dev) & 31]; - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -} - -int pci_pre_init(struct pci_controller *hose) -{ - hose->fixup_irq = taihu_pci_fixup_irq; - return 1; -} -#endif /* CONFIG_PCI */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c deleted file mode 100644 index ace217d..0000000 --- a/board/amcc/taihu/update.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <i2c.h> - -#define PCI_M66EN 0x10 - -static uchar buf_33[] = -{ - 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ - 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ - 0x00, - 0x00, - 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ - 0x00, - 0x00, - 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ - 0x14, - 0x00, /* 0x0f~0x10:device id 0x0000*/ - 0x00, - 0x00, /* 0x11:revision 0x00 */ - 0x00, /* 0x12~0x14:class 0x000000 */ - 0x00, - 0x00, - 0x10, /* 0x15~0x16:subsystem vendor id */ - 0xe8, - 0x00, /* 0x17~0x18:subsystem device id */ - 0x00, - 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ - 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ - 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ - 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ - 0xbe, /* 0x1d: tun[24-31]=0xbe */ - 0x00, - 0x00 -}; - -static uchar buf_66[] = -{ - 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ - 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ - 0x00, - 0x00, - 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ - 0x00, - 0x00, - 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ - 0x14, - 0x00, /* 0x0f~0x10:device id 0x0000*/ - 0x00, - 0x00, /* 0x11:revision 0x00 */ - 0x00, /* 0x12~0x14:class 0x000000 */ - 0x00, - 0x00, - 0x10, /* 0x15~0x16:subsystem vendor id */ - 0xe8, - 0x00, /* 0x17~0x18:subsystem device id */ - 0x00, - 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ - 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ - 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ - 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ - 0xbe, /* 0x1d: tun[24-31]=0xbe */ - 0x00, - 0x00 -}; - -static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[]) -{ - ulong len = 0x20; - uchar chip = CONFIG_SYS_I2C_EEPROM_ADDR; - uchar *pbuf; - uchar base; - int i; - - if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) { - pbuf = buf_33; - base = 0x00; - } else { - pbuf = buf_66; - base = 0x40; - } - - for (i = 0; i< len; i++, base++) { - if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) { - printf("i2c_write fail\n"); - return 1; - } - udelay(11000); - } - - return 0; -} - -U_BOOT_CMD ( - update_boot_eeprom, 1, 1, update_boot_eeprom, - "update boot eeprom content", - "" -); diff --git a/configs/taihu_defconfig b/configs/taihu_defconfig deleted file mode 100644 index ac83725..0000000 --- a/configs/taihu_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_TAIHU=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2760f60..5ef6c4e 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +taihu powerpc ppc4xx - - John Otken <jotken(a)softadvances.com> lcd4_lwmon5 powerpc ppc4xx b6b5e394 2015-10-02 Stefan Roese <sr(a)denx.de> da830evm arm arm926ejs d7e8b2b9 2015-09-12 Nick Thompson <nick.thompson(a)gefanuc.com> wireless_space arm arm926ejs b352182a 2015-09-12 Albert ARIBAUD <albert.u.boot(a)aribaud.net> diff --git a/include/configs/taihu.h b/include/configs/taihu.h deleted file mode 100644 index 5c0ce7a2..0000000 --- a/include/configs/taihu.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * (C) Copyright 2005-2007 - * Beijing UD Technology Co., Ltd., taihusupport(a)amcc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - - -#define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_TAIHU 1 /* on a taihu board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME taihu -#include "amcc-common.h" - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_NO_SERIAL_EEPROM - -/*----------------------------------------------------------------------------*/ -#ifdef CONFIG_NO_SERIAL_EEPROM - -/* -!------------------------------------------------------------------------------- -! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI, -! assuming a 33MHz input clock to the 405EP from the C9531. -!------------------------------------------------------------------------------- -*/ -#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_3) -#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) -#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_1) -#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -#define PLLMR0_DEFAULT PLLMR0_333_111_55_37 -#define PLLMR1_DEFAULT PLLMR1_333_111_55_37 -#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111 -#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111 - -#endif -/*----------------------------------------------------------------------------*/ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_PPC \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ - "kernel_addr=FC000000\0" \ - "ramdisk_addr=FC180000\0" \ - "" - -#define CONFIG_PHY_ADDR 0x14 /* PHY address */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ -#define CONFIG_PHY_RESET 1 - -/* - * Commands additional to the ones defined in amcc-common.h - */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SPI - -#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */ -#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ -#define CONFIG_SYS_SDRAM_BANKS 2 - -/* - * SDRAM configuration (please see cpu/ppc/sdram.[ch]) - */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ -#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ - -/* SDRAM timings used in datasheet */ -#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ -#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ -#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ -#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ -#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ - -/* - * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. - * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. - * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. - * The Linux BASE_BAUD define should match this configuration. - * baseBaud = cpuClock/(uartDivisor*16) - * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, - * set Linux BASE_BAUD to 403200. - */ -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/*----------------------------------------------------------------------- - * I2C stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 - -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - -#define CONFIG_SOFT_SPI -#define SPI_SCL spi_scl -#define SPI_SDA spi_sda -#define SPI_READ spi_read() -#define SPI_DELAY udelay(2) -#ifndef __ASSEMBLY__ -void spi_scl(int); -void spi_sda(int); -unsigned char spi_read(void); -#endif - -/* standard dtt sensor configuration */ -#define CONFIG_DTT_DS1775 1 -#define CONFIG_DTT_SENSORS { 0 } -#define CONFIG_SYS_I2C_DTT_ADDR 0x49 - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#define CONFIG_EEPRO100 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - */ -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_ADDR0 0x555 -#define CONFIG_SYS_FLASH_ADDR1 0x2aa -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ - -#ifdef CONFIG_ENV_IS_IN_NVRAM -#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/ -#endif - -/*----------------------------------------------------------------------- - * PPC405 GPIO Configuration - */ -#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ -{ \ -/* GPIO Core 0 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \ -{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ -{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \ -{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \ -} \ -} - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory (OCM) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash/SRAM) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x03815600 -#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (NVRAM/RTC) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x05815600 -#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (USB device) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x03016600 -#define CONFIG_SYS_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (LCM and D-flip-flop) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x158FF600 -#define CONFIG_SYS_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (not install) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x158FF600 -#define CONFIG_SYS_EBC_PB4CR 0x5021A000 - -#define CPLD_REG0_ADDR 0x50100000 -#define CPLD_REG1_ADDR 0x50100001 - -#endif /* __CONFIG_H */ -- 1.7.9.5

3 8

[U-Boot] [PATCH] cfi_flash: use specific width types for cword
by Ryan Harkin 27 Oct '15

27 Oct '15

This patch changes the cword union to use specific length types that are architecture indepented. This patch also renames the members of the cword union to represent their usage, i.e.: c -> w8 s -> w16 l -> w32 ll -> w64 Where "w" stands for "width" in bits. I discovered this problem when enabling CFI flash on vexpress64. cword.l was an unsigned long int, but it was intended to be 32 bits wide. Unfortunately, it's 64-bits wide on a 64-bit system, meaning that a 64-bit system fails when attempting to use 32-bit wide CFI flash parts. Similar problems also existed with the other cword sizes. Signed-off-by: Ryan Harkin <ryan.harkin(a)linaro.org> --- drivers/mtd/cfi_flash.c | 82 ++++++++++++++++++++++++------------------------- include/mtd/cfi_flash.h | 8 ++--- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 50983b8..fc7a878 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -335,34 +335,34 @@ void flash_write_cmd (flash_info_t * info, flash_sect_t sect, switch (info->portwidth) { case FLASH_CFI_8BIT: debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, - cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); - flash_write8(cword.c, addr); + cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + flash_write8(cword.w8, addr); break; case FLASH_CFI_16BIT: debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, - cmd, cword.w, + cmd, cword.w16, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); - flash_write16(cword.w, addr); + flash_write16(cword.w16, addr); break; case FLASH_CFI_32BIT: - debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr, - cmd, cword.l, + debug ("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr, + cmd, cword.w32, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); - flash_write32(cword.l, addr); + flash_write32(cword.w32, addr); break; case FLASH_CFI_64BIT: #ifdef DEBUG { char str[20]; - print_longlong (str, cword.ll); + print_longlong (str, cword.w64); debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", addr, cmd, str, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); } #endif - flash_write64(cword.ll, addr); + flash_write64(cword.w64, addr); break; } @@ -393,16 +393,16 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); switch (info->portwidth) { case FLASH_CFI_8BIT: - debug ("is= %x %x\n", flash_read8(addr), cword.c); - retval = (flash_read8(addr) == cword.c); + debug ("is= %x %x\n", flash_read8(addr), cword.w8); + retval = (flash_read8(addr) == cword.w8); break; case FLASH_CFI_16BIT: - debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); - retval = (flash_read16(addr) == cword.w); + debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16); + retval = (flash_read16(addr) == cword.w16); break; case FLASH_CFI_32BIT: - debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l); - retval = (flash_read32(addr) == cword.l); + debug ("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32); + retval = (flash_read32(addr) == cword.w32); break; case FLASH_CFI_64BIT: #ifdef DEBUG @@ -411,11 +411,11 @@ static int flash_isequal (flash_info_t * info, flash_sect_t sect, char str2[20]; print_longlong (str1, flash_read64(addr)); - print_longlong (str2, cword.ll); + print_longlong (str2, cword.w64); debug ("is= %s %s\n", str1, str2); } #endif - retval = (flash_read64(addr) == cword.ll); + retval = (flash_read64(addr) == cword.w64); break; default: retval = 0; @@ -439,16 +439,16 @@ static int flash_isset (flash_info_t * info, flash_sect_t sect, flash_make_cmd (info, cmd, &cword); switch (info->portwidth) { case FLASH_CFI_8BIT: - retval = ((flash_read8(addr) & cword.c) == cword.c); + retval = ((flash_read8(addr) & cword.w8) == cword.w8); break; case FLASH_CFI_16BIT: - retval = ((flash_read16(addr) & cword.w) == cword.w); + retval = ((flash_read16(addr) & cword.w16) == cword.w16); break; case FLASH_CFI_32BIT: - retval = ((flash_read32(addr) & cword.l) == cword.l); + retval = ((flash_read32(addr) & cword.w32) == cword.w32); break; case FLASH_CFI_64BIT: - retval = ((flash_read64(addr) & cword.ll) == cword.ll); + retval = ((flash_read64(addr) & cword.w64) == cword.w64); break; default: retval = 0; @@ -680,33 +680,33 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) switch (info->portwidth) { case FLASH_CFI_8BIT: - cword->c = c; + cword->w8 = c; break; case FLASH_CFI_16BIT: #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) w = c; w <<= 8; - cword->w = (cword->w >> 8) | w; + cword->w16 = (cword->w16 >> 8) | w; #else - cword->w = (cword->w << 8) | c; + cword->w16 = (cword->w16 << 8) | c; #endif break; case FLASH_CFI_32BIT: #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) l = c; l <<= 24; - cword->l = (cword->l >> 8) | l; + cword->w32 = (cword->w32 >> 8) | l; #else - cword->l = (cword->l << 8) | c; + cword->w32 = (cword->w32 << 8) | c; #endif break; case FLASH_CFI_64BIT: #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) ll = c; ll <<= 56; - cword->ll = (cword->ll >> 8) | ll; + cword->w64 = (cword->w64 >> 8) | ll; #else - cword->ll = (cword->ll << 8) | c; + cword->w64 = (cword->w64 << 8) | c; #endif break; } @@ -753,16 +753,16 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, /* Check if Flash is (sufficiently) erased */ switch (info->portwidth) { case FLASH_CFI_8BIT: - flag = ((flash_read8(dstaddr) & cword.c) == cword.c); + flag = ((flash_read8(dstaddr) & cword.w8) == cword.w8); break; case FLASH_CFI_16BIT: - flag = ((flash_read16(dstaddr) & cword.w) == cword.w); + flag = ((flash_read16(dstaddr) & cword.w16) == cword.w16); break; case FLASH_CFI_32BIT: - flag = ((flash_read32(dstaddr) & cword.l) == cword.l); + flag = ((flash_read32(dstaddr) & cword.w32) == cword.w32); break; case FLASH_CFI_64BIT: - flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll); + flag = ((flash_read64(dstaddr) & cword.w64) == cword.w64); break; default: flag = 0; @@ -800,16 +800,16 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, switch (info->portwidth) { case FLASH_CFI_8BIT: - flash_write8(cword.c, dstaddr); + flash_write8(cword.w8, dstaddr); break; case FLASH_CFI_16BIT: - flash_write16(cword.w, dstaddr); + flash_write16(cword.w16, dstaddr); break; case FLASH_CFI_32BIT: - flash_write32(cword.l, dstaddr); + flash_write32(cword.w32, dstaddr); break; case FLASH_CFI_64BIT: - flash_write64(cword.ll, dstaddr); + flash_write64(cword.w64, dstaddr); break; } @@ -1115,7 +1115,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) if (use_flash_status_poll(info)) { cfiword_t cword; void *dest; - cword.ll = 0xffffffffffffffffULL; + cword.w64 = 0xffffffffffffffffULL; dest = flash_map(info, sect, 0); st = flash_status_poll(info, &cword, dest, info->erase_blk_tout, "erase"); @@ -1305,7 +1305,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /* handle unaligned start */ if ((aln = addr - wp) != 0) { - cword.l = 0; + cword.w32 = 0; p = (uchar *)wp; for (i = 0; i < aln; ++i) flash_add_byte (info, &cword, flash_read8(p + i)); @@ -1332,7 +1332,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) while (cnt >= info->portwidth) { /* prohibit buffer write when buffer_size is 1 */ if (info->buffer_size == 1) { - cword.l = 0; + cword.w32 = 0; for (i = 0; i < info->portwidth; i++) flash_add_byte (info, &cword, *src++); if ((rc = flash_write_cfiword (info, wp, cword)) != 0) @@ -1359,7 +1359,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) } #else while (cnt >= info->portwidth) { - cword.l = 0; + cword.w32 = 0; for (i = 0; i < info->portwidth; i++) { flash_add_byte (info, &cword, *src++); } @@ -1381,7 +1381,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /* * handle unaligned tail bytes */ - cword.l = 0; + cword.w32 = 0; p = (uchar *)wp; for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { flash_add_byte (info, &cword, *src++); diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 048b477..52572b9 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -105,10 +105,10 @@ #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ typedef union { - unsigned char c; - unsigned short w; - unsigned long l; - unsigned long long ll; + u8 w8; + u16 w16; + u32 w32; + u64 w64; } cfiword_t; /* CFI standard query structure */ -- 2.1.4

3 2

[U-Boot] [PATCH v2 1/3] part:efi: add GUID for linux file system data
by Patrick Delaunay 27 Oct '15

27 Oct '15

Previously, Linux used the same GUID for the data partitions as Windows (Basic data partition: EBD0A0A2-B9E5-4433-87C0-68B6B72699C7). This created problems when dual-booting Linux and Windows in UEFI-GPT Setup, so a new GUID (Linux filesystem data: 0FC63DAF-8483-4772-8E79-3D69D8477DE4) was defined jointly by GPT fdisk and GNU Parted developers. Signed-off-by: Patrick Delaunay <patrick.delaunay73(a)gmail.com> --- see https://en.wikipedia.org/wiki/GUID_Partition_Table#Partition_type_GUIDs and nota 9 Changes in v2: - None include/part_efi.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/part_efi.h b/include/part_efi.h index 3012b91..c8fc873 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -43,6 +43,9 @@ #define PARTITION_BASIC_DATA_GUID \ EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \ 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7) +#define PARTITION_LINUX_FILE_SYSTEM_DATA_GUID \ + EFI_GUID(0x0FC63DAF, 0x8483, 0x4772, \ + 0x8E, 0x79, 0x3D, 0x69, 0xD8, 0x47, 0x7D, 0xE4) #define PARTITION_LINUX_RAID_GUID \ EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \ 0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e) -- 1.9.1

3 7

[U-Boot] fdt_fixup_ethernet() and "usbethaddr" env
by Bin Meng 27 Oct '15

27 Oct '15

Hi, It looks to me that current implementation in fdt_fixup_ethernet() is somewhat cripple to handle usb ethernet mac address fix up. It only handles "usbethaddr", but does not handle "usbeth1addr", "usbeth2addr", etc. I also checked all the device tree source files in the kernel tree, and found only "ethernet%d" is used under the "/aliases" node. But the loop in fdt_fixup_ethernet() only checks "usb%daddr" env, but no "usbeth%daddr". By checking git log I found commit b1f49ab added the "usbethaddr" handle codes in fdt_fixup_ethernet(). What if we have a board that has both a USB ethernet port and a normal ethernet port? Can we just use "eth%daddr" for all ethernet interfaces? Background: I was trying to refactor the codes in fdt_fixup_ethernet() and found this "usbethaddr" issue. Regards, Bin

1 1

[U-Boot] [PATCH v2] arm: atmel: Add SAMA5D2 Xplained board
by Wenyou Yang 27 Oct '15

27 Oct '15

The board supports following features: - Boot media support: SD card/e.MMC/SPI flash, - Support LCD display (optional, disabled by default), - Support ethernet, - Support USB mass storage. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- The patch is based on the following patches sent in mailing list. [PATCH] gpio: atmel: Add the PIO4 driver support [PATCH] arm: at91: Change the Chip ID registers' addresses [PATCH v3] mmc: atmel: Add atmel sdhci support [PATCH v2] arm: at91: clock: Add the generated clock support Changes in v2: 1./ re-order SAMA5D2 statements alphabetically. 2./ remove redundant "Unknown CPU type". 3./ rework sama5d2's macros. 4./ remove some #ifdef before functions. 5./ move CONFIG_CMD_SF to Kconfig. 6./ remove NAND macros from config file. 7./ CONFIG_BOOTCOMMAND for sf uses defines in at91-sama5_common.h. arch/arm/mach-at91/Kconfig | 5 + arch/arm/mach-at91/armv7/Makefile | 1 + arch/arm/mach-at91/armv7/sama5d2_devices.c | 60 +++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 9 +- arch/arm/mach-at91/include/mach/atmel_usba_udc.h | 3 +- arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/include/mach/sama5d2.h | 224 +++++++++++++++++ board/atmel/sama5d2_xplained/Kconfig | 15 ++ board/atmel/sama5d2_xplained/MAINTAINERS | 7 + board/atmel/sama5d2_xplained/Makefile | 8 + board/atmel/sama5d2_xplained/sama5d2_xplained.c | 282 ++++++++++++++++++++++ configs/sama5d2_xplained_mmc_defconfig | 11 + configs/sama5d2_xplained_spiflash_defconfig | 11 + include/configs/sama5d2_xplained.h | 126 ++++++++++ 14 files changed, 758 insertions(+), 6 deletions(-) create mode 100644 arch/arm/mach-at91/armv7/sama5d2_devices.c create mode 100644 arch/arm/mach-at91/include/mach/sama5d2.h create mode 100644 board/atmel/sama5d2_xplained/Kconfig create mode 100644 board/atmel/sama5d2_xplained/MAINTAINERS create mode 100644 board/atmel/sama5d2_xplained/Makefile create mode 100644 board/atmel/sama5d2_xplained/sama5d2_xplained.c create mode 100644 configs/sama5d2_xplained_mmc_defconfig create mode 100644 configs/sama5d2_xplained_spiflash_defconfig create mode 100644 include/configs/sama5d2_xplained.h diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index fdaf328..c333647 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -71,6 +71,10 @@ config TARGET_AT91SAM9X5EK select CPU_ARM926EJS select SUPPORT_SPL +config TARGET_SAMA5D2_XPLAINED + bool "SAMA5D2 Xplained board" + select CPU_V7 + config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" select CPU_V7 @@ -123,6 +127,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index f4f35a4..9538bc1 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -8,6 +8,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o obj-y += clock.o diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c new file mode 100644 index 0000000..26883fc --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> +#include <asm/arch/sama5d2.h> + +char *get_cpu_name() +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama5d2()) { + switch (extension_id) { + case ARCH_EXID_SAMA5D21CU: + return "SAMA5D21"; + case ARCH_EXID_SAMA5D22CU: + return "SAMA5D22-CU"; + case ARCH_EXID_SAMA5D22CN: + return "SAMA5D22-CN"; + case ARCH_EXID_SAMA5D23CU: + return "SAMA5D23-CU"; + case ARCH_EXID_SAMA5D24CX: + return "SAMA5D24-CX"; + case ARCH_EXID_SAMA5D24CU: + return "SAMA5D24-CU"; + case ARCH_EXID_SAMA5D26CU: + return "SAMA5D26-CU"; + case ARCH_EXID_SAMA5D27CU: + return "SAMA5D27-CU"; + case ARCH_EXID_SAMA5D27CN: + return "SAMA5D27-CN"; + case ARCH_EXID_SAMA5D28CU: + return "SAMA5D28-CU"; + case ARCH_EXID_SAMA5D28CN: + return "SAMA5D28-CN"; + default: + goto err_exit; + } + } + +err_exit: + return "Unknown CPU type"; +} + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 8a3fb94..5adaa30 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -78,7 +78,8 @@ typedef struct at91_pmc { #define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) #define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) #define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ + defined(CONFIG_SAMA5D4) #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18) #else #define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) @@ -97,7 +98,8 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 #define AT91_PMC_MCKR_CSS_MASK 0x00000003 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ +#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ + defined(CONFIG_SAMA5D4) || \ defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_PRES_1 0x00000000 #define AT91_PMC_MCKR_PRES_2 0x00000010 @@ -127,10 +129,7 @@ typedef struct at91_pmc { #else #define AT91_PMC_MCKR_MDIV_1 0x00000000 #define AT91_PMC_MCKR_MDIV_2 0x00000100 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ - defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_MDIV_3 0x00000300 -#endif #define AT91_PMC_MCKR_MDIV_4 0x00000200 #define AT91_PMC_MCKR_MDIV_MASK 0x00000300 #endif diff --git a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h index 38b5012..46a329b 100644 --- a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h +++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h @@ -31,7 +31,8 @@ static struct usba_ep_data usba_udc_ep[] = { EP("ep5", 5, 1024, 3, 1, 1), EP("ep6", 6, 1024, 3, 1, 1), }; -#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#elif defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \ + defined(CONFIG_SAMA5D4) static struct usba_ep_data usba_udc_ep[] = { EP("ep0", 0, 64, 1, 0, 0), EP("ep1", 1, 1024, 3, 1, 0), diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index ff6b71b..38abfda 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -23,6 +23,8 @@ # include <asm/arch/at91sam9g45.h> #elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) # include <asm/arch/at91sam9x5.h> +#elif defined(CONFIG_SAMA5D2) +# include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) # include <asm/arch/sama5d3.h> #elif defined(CONFIG_SAMA5D4) diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h new file mode 100644 index 0000000..200070d --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -0,0 +1,224 @@ +/* + * Chip-specific header file for the SAMA5D2 SoC + * + * Copyright (C) 2015 Atmel + * Wenyou Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SAMA5D2_H +#define __SAMA5D2_H + +/* + * defines to be used in other places + */ +#define CONFIG_AT91FAMILY /* It's a member of AT91 */ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */ +/* 1 */ +#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */ +#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */ +#define ATMEL_ID_WDT 4 /* Watchdog Timer Interrupt */ +#define ATMEL_ID_GMAC 5 /* Ethernet MAC */ +#define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */ +#define ATMEL_ID_XDMAC1 7 /* DMA Controller 1 */ +#define ATMEL_ID_ICM 8 /* Integrity Check Monitor */ +#define ATMEL_ID_AES 9 /* Advanced Encryption Standard */ +#define ATMEL_ID_AESB 10 /* AES bridge */ +#define ATMEL_ID_TDES 11 /* Triple Data Encryption Standard */ +#define ATMEL_ID_SHA 12 /* SHA Signature */ +#define ATMEL_ID_MPDDRC 13 /* MPDDR Controller */ +#define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */ +#define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */ +#define ATMEL_ID_SECUMOD 16 /* Secure Module */ +#define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */ +#define ATMEL_ID_PIOA 18 /* Parallel I/O Controller A */ +#define ATMEL_ID_FLEXCOM0 19 /* FLEXCOM0 */ +#define ATMEL_ID_FLEXCOM1 20 /* FLEXCOM1 */ +#define ATMEL_ID_FLEXCOM2 21 /* FLEXCOM2 */ +#define ATMEL_ID_FLEXCOM3 22 /* FLEXCOM3 */ +#define ATMEL_ID_FLEXCOM4 23 /* FLEXCOM4 */ +#define ATMEL_ID_UART0 24 /* UART0 */ +#define ATMEL_ID_UART1 25 /* UART1 */ +#define ATMEL_ID_UART2 26 /* UART2 */ +#define ATMEL_ID_UART3 27 /* UART3 */ +#define ATMEL_ID_UART4 28 /* UART4 */ +#define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */ +#define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */ +#define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */ +#define ATMEL_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */ +#define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 34 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */ +#define ATMEL_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */ +/* 37 */ +#define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */ +/* 39 */ +#define ATMEL_ID_ADC 40 /* Touch Screen ADC Controller */ +#define ATMEL_ID_UHPHS 41 /* USB Host High Speed */ +#define ATMEL_ID_UDPHS 42 /* USB Device High Speed */ +#define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 44 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_LCDC 45 /* LCD Controller */ +#define ATMEL_ID_ISI 46 /* Image Sensor Controller, for A5D2, named after ISC */ +#define ATMEL_ID_TRNG 47 /* True Random Number Generator */ +#define ATMEL_ID_PDMIC 48 /* PDM Interface Controller */ +#define ATMEL_ID_AIC_IRQ 49 /* IRQ Interrupt ID */ +#define ATMEL_ID_SFC 50 /* Fuse Controller */ +#define ATMEL_ID_SECURAM 51 /* Secure RAM */ +#define ATMEL_ID_QSPI0 52 /* QSPI0 */ +#define ATMEL_ID_QSPI1 53 /* QSPI1 */ +#define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */ +#define ATMEL_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */ +#define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */ +#define ATMEL_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */ +/* 58 */ +#define ATMEL_ID_CLASSD 59 /* Audio Class D Amplifier */ +#define ATMEL_ID_SFR 60 /* Special Function Register */ +#define ATMEL_ID_SAIC 61 /* Secured AIC */ +#define ATMEL_ID_AIC 62 /* Advanced Interrupt Controller */ +#define ATMEL_ID_L2CC 63 /* L2 Cache Controller */ +#define ATMEL_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */ +#define ATMEL_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */ +#define ATMEL_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */ +#define ATMEL_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */ +#define ATMEL_ID_PIOB 68 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 69 /* Parallel I/O Controller C */ +#define ATMEL_ID_PIOD 70 /* Parallel I/O Controller D */ +#define ATMEL_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 (TIMER) */ +#define ATMEL_ID_SDMMC1_TIMER 72 /* Secure Data Memory Card Controller 1 (TIMER) */ +/* 73 */ +#define ATMEL_ID_SYS 74 /* System Controller Interrupt */ +#define ATMEL_ID_ACC 75 /* Analog Comparator */ +#define ATMEL_ID_RXLP 76 /* UART Low-Power */ +#define ATMEL_ID_SFRBU 77 /* Special Function Register BackUp */ +#define ATMEL_ID_CHIPID 78 /* Chip ID */ + +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_LCDC 0xf0000000 +#define ATMEL_BASE_XDMAC1 0xf0004000 +#define ATMEL_BASE_MPDDRC 0xf000c000 +#define ATMEL_BASE_XDMAC0 0xf0010000 +#define ATMEL_BASE_PMC 0xf0014000 +#define ATMEL_BASE_QSPI0 0xf0020000 +#define ATMEL_BASE_QSPI1 0xf0024000 +#define ATMEL_BASE_SPI0 0xf8000000 +#define ATMEL_BASE_GMAC 0xf8008000 +#define ATMEL_BASE_TC0 0xf800c000 +#define ATMEL_BASE_TC1 0xf8010000 +#define ATMEL_BASE_HSMC 0xf8014000 +#define ATMEL_BASE_UART0 0xf801c000 +#define ATMEL_BASE_UART1 0xf8020000 +#define ATMEL_BASE_UART2 0xf8024000 +#define ATMEL_BASE_TWI0 0xf8028000 +#define ATMEL_BASE_SYSC 0xf8048000 +#define ATMEL_BASE_SPI1 0xfc000000 +#define ATMEL_BASE_UART3 0xfc008000 +#define ATMEL_BASE_UART4 0xfc00c000 +#define ATMEL_BASE_TWI1 0xfc028000 +#define ATMEL_BASE_UDPHS 0xfc02c000 + +#define ATMEL_BASE_PIOA 0xfc038000 + +#define ATMEL_CHIPID_CIDR 0xfc069000 +#define ATMEL_CHIPID_EXID 0xfc069004 + +/* + * Address Memory Space + */ +#define ATMEL_BASE_DDRCS 0x20000000 +#define ATMEL_BASE_QSPI0_AES_MEM 0x90000000 +#define ATMEL_BASE_QSPI1_AES_MEM 0x98000000 +#define ATMEL_BASE_SDMMC0 0xa0000000 +#define ATMEL_BASE_SDMMC1 0xb0000000 +#define ATMEL_BASE_QSPI0_MEM 0xd0000000 +#define ATMEL_BASE_QSPI1_MEM 0xd8000000 + +/* + * Internal Memories + */ +#define ATMEL_BASE_UDPHS_FIFO 0x00300000 /* USB Device HS controller */ +#define ATMEL_BASE_OHCI 0x00400000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00500000 /* USB Host controller (EHCI) */ + +/* Other misc defines */ +#define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) +#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) + +#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) +#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) +#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) + +/* SYSC spawns */ +#define ATMEL_BASE_RSTC ATMEL_BASE_SYSC +#define ATMEL_BASE_SHDWC (ATMEL_BASE_SYSC + 0x10) +#define ATMEL_BASE_PIT (ATMEL_BASE_SYSC + 0x30) +#define ATMEL_BASE_WDT (ATMEL_BASE_SYSC + 0x40) +#define ATMEL_BASE_SCKC (ATMEL_BASE_SYSC + 0x50) +#define ATMEL_BASE_RTC (ATMEL_BASE_SYSC + 0xb0) + +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 4 +#define CPU_HAS_PCR +#define CPU_HAS_H32MXDIV + +/* SAMA5D2 series chip id definitions */ +#define ARCH_ID_SAMA5D2 0x8a5c08c0 +#define ARCH_EXID_SAMA5D21CU 0x0000005a +#define ARCH_EXID_SAMA5D22CU 0x00000059 +#define ARCH_EXID_SAMA5D22CN 0x00000069 +#define ARCH_EXID_SAMA5D23CU 0x00000058 +#define ARCH_EXID_SAMA5D24CX 0x00000004 +#define ARCH_EXID_SAMA5D24CU 0x00000014 +#define ARCH_EXID_SAMA5D26CU 0x00000012 +#define ARCH_EXID_SAMA5D27CU 0x00000011 +#define ARCH_EXID_SAMA5D27CN 0x00000021 +#define ARCH_EXID_SAMA5D28CU 0x00000010 +#define ARCH_EXID_SAMA5D28CN 0x00000020 + +#define cpu_is_sama5d2() (get_chip_id() == ARCH_ID_SAMA5D2) +#define cpu_is_sama5d21cu() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D21CU)) +#define cpu_is_sama5d22cu() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D22CU)) +#define cpu_is_sama5d22cn() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D22CN)) +#define cpu_is_sama5d23cu() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D23CU)) +#define cpu_is_sama5d24cx() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D24CX)) +#define cpu_is_sama5d24cu() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D24CU)) +#define cpu_is_sama5d26cu() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D26CU)) +#define cpu_is_sama5d27cu() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D27CU)) +#define cpu_is_sama5d27cn() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D27CN)) +#define cpu_is_sama5d28cu() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D28CU)) +#define cpu_is_sama5d28cn() (cpu_is_sama5d2() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA5D28CN)) + +/* PIT Timer(PIT_PIIR) */ +#define CONFIG_SYS_TIMER_COUNTER 0xf804803c + +/* No PMECC Galois table in ROM */ +#define NO_GALOIS_TABLE_IN_ROM + +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +unsigned int has_lcdc(void); +char *get_cpu_name(void); +#endif + +#endif diff --git a/board/atmel/sama5d2_xplained/Kconfig b/board/atmel/sama5d2_xplained/Kconfig new file mode 100644 index 0000000..55712e9 --- /dev/null +++ b/board/atmel/sama5d2_xplained/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D2_XPLAINED + +config SYS_BOARD + default "sama5d2_xplained" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d2_xplained" + +endif diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS new file mode 100644 index 0000000..ff9c86f --- /dev/null +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D2 XPLAINED BOARD +M: Wenyou Yang <wenyou.yang(a)atmel.com> +S: Maintained +F: board/atmel/sama5d2_xplained/ +F: include/configs/sama5d2_xplained.h +F: configs/sama5d2_xplained_mmc_defconfig +F: configs/sama5d2_xplained_spiflash_defconfig diff --git a/board/atmel/sama5d2_xplained/Makefile b/board/atmel/sama5d2_xplained/Makefile new file mode 100644 index 0000000..420870b --- /dev/null +++ b/board/atmel/sama5d2_xplained/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015 Atmel Corporation +# Wenyou Yang <wenyou.yang(a)atmel.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sama5d2_xplained.o diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c new file mode 100644 index 0000000..adac13a --- /dev/null +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <atmel_hlcdc.h> +#include <lcd.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <spi.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_usba_udc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); +} + +static void board_spi0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0); + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0); + + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); + + at91_periph_clk_enable(ATMEL_ID_SPI0); +} + +static void board_usb_hw_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 9, 1); + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); +} + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_bpix = LCD_BPP, + .vl_tft = 1, + .vl_hsync_len = 41, + .vl_left_margin = 2, + .vl_right_margin = 2, + .vl_vsync_len = 11, + .vl_upper_margin = 2, + .vl_lower_margin = 2, + .mmio = ATMEL_BASE_LCDC, +}; + +/* No power up/down pin for the LCD pannel */ +void lcd_enable(void) { /* Empty! */ } +void lcd_disable(void) { /* Empty! */ } + +unsigned int has_lcdc(void) +{ + return 1; +} + +static void board_lcd_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */ + + /* LCDDAT0 */ + /* LCDDAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */ + + /* LCDDAT8 */ + /* LCDDAT9 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */ + + /* LCDD16 */ + /* LCDD17 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */ + + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size; + int i; + char temp[32]; + + lcd_printf("%s\n", U_BOOT_VERSION); + lcd_printf("2015 ATMEL Corp\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + lcd_printf("%ld MB SDRAM\n", dram_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ +#endif /* CONFIG_LCD_INFO */ + +static void board_gmac_hw_init(void) +{ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ + atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ + + at91_periph_clk_enable(ATMEL_ID_GMAC); +} + +static void board_sdhci0_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SDMMC0_CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SDMMC0_CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SDMMC0_DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* SDMMC0_DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* SDMMC0_DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* SDMMC0_DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0); /* SDMMC0_DAT4 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0); /* SDMMC0_DAT5 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0); /* SDMMC0_DAT6 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); + at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0); +} + +static void board_sdhci1_hw_init(void) +{ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0); /* SDMMC1_DAT1 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0); /* SDMMC1_DAT2 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0); /* SDMMC1_DAT3 */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0); /* SDMMC1_CK */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0); /* SDMMC1_RSTN */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0); /* SDMMC1_CMD */ + atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0); /* SDMMC1_CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC1); + at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1); +} + +int board_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_ATMEL_SDHCI0 + atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0); +#endif +#ifdef CONFIG_ATMEL_SDHCI1 + atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1); +#endif + + return 0; +} + +static void board_uart1_hw_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ + + at91_periph_clk_enable(ATMEL_ID_UART1); +} + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + + board_uart1_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_ATMEL_SPI + board_spi0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI +#ifdef CONFIG_ATMEL_SDHCI0 + board_sdhci0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI1 + board_sdhci1_hw_init(); +#endif +#endif +#ifdef CONFIG_MACB + board_gmac_hw_init(); +#endif +#ifdef CONFIG_LCD + board_lcd_hw_init(); +#endif +#ifdef CONFIG_CMD_USB + board_usb_hw_init(); +#endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + usba_udc_probe(&pdata); +#ifdef CONFIG_USB_ETH_RNDIS + usb_eth_initialize(bis); +#endif +#endif + + return rc; +} diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig new file mode 100644 index 0000000..c1dcbef --- /dev/null +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig new file mode 100644 index 0000000..0271e8e --- /dev/null +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_SPI_FLASH=y diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h new file mode 100644 index 0000000..ff9e79c --- /dev/null +++ b/include/configs/sama5d2_xplained.h @@ -0,0 +1,126 @@ +/* + * Configuration file for the SAMA5D2 Xplained Board. + * + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH + +#include "at91-sama5_common.h" + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_UART1 +#define CONFIG_USART_ID ATMEL_ID_UART1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#else +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#undef CONFIG_AT91_GPIO +#define CONFIG_ATMEL_PIO4 + +/* SerialFlash */ +#ifdef CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI +#define CONFIG_ATMEL_SPI0 +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#endif + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_ATMEL_SDHCI +#define CONFIG_ATMEL_SDHCI0 +#define CONFIG_ATMEL_SDHCI1 +#define CONFIG_SUPPORT_EMMC_BOOT +#endif + +/* USB */ +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE +#endif + +/* USB device */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_ATMEL_USBA +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2 XPlained" + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +/* #define CONFIG_LCD */ + +#ifdef CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP 24 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#endif + +#ifdef CONFIG_SYS_USE_MMC + +/* bootstrap + u-boot + env in sd card */ +#undef FAT_ENV_DEVICE_AND_PART +#undef CONFIG_BOOTCOMMAND + +#define FAT_ENV_DEVICE_AND_PART "1" +#define CONFIG_BOOTCOMMAND "fatload mmc 1:1 0x21000000 at91-sama5d2_xplained.dtb; " \ + "fatload mmc 1:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait" + +#endif + +#endif -- 1.7.9.5

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[U-Boot] [PATCH V2 00/14] imx: mx6/7: support lcdif
by Peng Fan 27 Oct '15

27 Oct '15

Changes v2: 1. Rebased on Latest U-Boot 2. Add i.MX7 LCDIF support This patch set is to introduce lcdif support for i.MX6/7. Patchset tested on mx6ul_14x14/9x9_evk and mx7dsabresd boards. 1/14 There are two LCD interface for i.MX6SX and one interface for i.MX6UL, so change the prototype mxs_set_lcdclk to handle different interface. [2,3]/14 I am not sure, but from my understanding, the 'board_' should be discarded. 4/14 mx28 and mx6ul/sx have similar register layout and bit definitions, so move related structure and bit definitions to imx-common. [5,6,7]/14 is to add related CCM macros, clock apis for enable lcdif on i.MX6 8/14 support lcdif for i.MX6UL 14x14/9x9 board 9/14 Introduce lcdif_power_down, to make system stable when reset or boot os [10,11]/14 Need to call lcdif_power_down, before trigger wdog reset or boot os. Or we may met unexpected system hang. [12,13,14]/14 Mainly support LCDIF for i.MX7. Peng Fan (14): mxs: add parameter base_addr for mxs_set_lcdclk sandisk: sfp: correct function name xfi3: correct function name imx: imx-common: move lcdif structure and macro definition to imx-common imx: mx6: fix register address imx: mx6: crm_reg: add LCDIF related macros imx: mx6: add clock api for lcdif imx: mx6ul_14x14_evk: support lcdif display video: mxsfb: introduce lcdif_power_down imx: mx6: implement reset_misc imx: imx-common: power down lcdif before boot os imx: mx7: compile misc.c for mx7 imx: mx7 use the common lcdif register structure imx: mx7dsabresd: support lcdif arch/arm/cpu/arm926ejs/mxs/clock.c | 2 +- arch/arm/cpu/armv7/mx6/clock.c | 239 ++++++++++++++++++++++ arch/arm/cpu/armv7/mx6/soc.c | 8 + arch/arm/imx-common/Makefile | 2 +- arch/arm/imx-common/cpu.c | 3 + arch/arm/include/asm/arch-mx6/clock.h | 2 + arch/arm/include/asm/arch-mx6/crm_regs.h | 34 ++- arch/arm/include/asm/arch-mx6/imx-regs.h | 15 +- arch/arm/include/asm/arch-mx7/imx-regs.h | 96 +-------- arch/arm/include/asm/arch-mxs/clock.h | 2 +- arch/arm/include/asm/arch-mxs/regs-lcdif.h | 201 +----------------- arch/arm/include/asm/imx-common/regs-lcdif.h | 224 ++++++++++++++++++++ arch/arm/include/asm/imx-common/sys_proto.h | 2 + board/creative/xfi3/xfi3.c | 2 +- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 63 ++++++ board/freescale/mx7dsabresd/mx7dsabresd.c | 64 ++++++ board/sandisk/sansa_fuze_plus/sfp.c | 2 +- drivers/video/mxsfb.c | 19 +- include/configs/mx6ul_14x14_evk.h | 18 ++ include/configs/mx7dsabresd.h | 17 ++ 20 files changed, 705 insertions(+), 310 deletions(-) create mode 100644 arch/arm/include/asm/imx-common/regs-lcdif.h -- 1.8.4

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