January 2015 - U-Boot

[U-Boot] usbtty using i.MX6
by Otavio Salvador 15 Jan '15

15 Jan '15

Hello, I'd like to know if someone has succeed in using usbtty with i.MX6. I am interested in using it for one board but been not succed, it seems: /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:553: undefined reference to `udc_init' drivers/serial/built-in.o: In function `usbtty_init_instances': /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:686: undefined reference to `udc_setup_ep' /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:708: undefined reference to `urb_link_init' /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:709: undefined reference to `urb_link_init' /home/otavio/hacking/u-boot/drivers/serial/usbtty.c:710: undefined reference to `urb_link_init ... Does someone got it working? -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750

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[U-Boot] [PATCH] arm: ls102xa: Enable snooping for CCI-400 S0 slave interface
by Alison Wang 15 Jan '15

15 Jan '15

CAAM is connected to CCI-400 S0 slave interface. Disable snooping for S0 will cause CAAM self test failure. This patch is to enable snooping for S0 slave interface. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- board/freescale/ls1021aqds/ls1021aqds.c | 3 +-- board/freescale/ls1021atwr/ls1021atwr.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 4dda5e3..e5dea5d 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -202,10 +202,9 @@ int board_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); /* - * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * Set CCI-400 Slave interface S1, S2 Shareable Override Register * All transactions are treated as non-shareable */ - out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 0629d1c..2c8afc0 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -419,10 +419,9 @@ int board_init(void) struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; /* - * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register + * Set CCI-400 Slave interface S1, S2 Shareable Override Register * All transactions are treated as non-shareable */ - out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(0x1185000, 0x3); -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] Nokia RX-51: Do not call secure PPA routine on non secure devices
by Pali Rohár 15 Jan '15

15 Jan '15

Since commit 41623c91b09a0c865fab41acdaff30f060f29ad6 u-boot running in qemu is crashing in function do_omap3_emu_romcode_call(). RX-51 board uses this function for Cortex-A8 errata 430973 workaround (Set IBE bit in ACR) which is needed only on real secure device and not in qemu. This board patch just disable calling secure PPA routine on non secure devices. Qemu implements GP device and with this patch u-boot is working in qemu again. Signed-off-by: Pali Rohár <pali.rohar(a)gmail.com> --- board/nokia/rx51/rx51.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index b6b8ad6..08fcaf2 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -422,8 +422,12 @@ int misc_init_r(void) /* * Cortex-A8(r1p0..r1p2) errata 430973 workaround * Set IBE bit in Auxiliary Control Register + * + * Call this routine only on real secure device + * Qemu does not implement secure PPA and crash */ - omap3_update_aux_cr_secure_rx51(1 << 6, 0); + if (get_device_type() == HS_DEVICE) + omap3_update_aux_cr_secure_rx51(1 << 6, 0); return 0; } -- 1.7.9.5

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[U-Boot] [PATCH] imx6: disable bandgap self-bias circuit after boot
by Peng Fan 15 Jan '15

15 Jan '15

The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan(a)freescale.com> --- arch/arm/cpu/armv7/mx6/soc.c | 24 ++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/crm_regs.h | 2 ++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5f5f497..36572c6 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -255,6 +255,23 @@ static void clear_mmdc_ch_mask(void) writel(0, &mxc_ccm->ccdr); } +static void init_bandgap(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + /* + * Ensure the bandgap has stabilized. + */ + while (!(readl(&mxc_ccm->ana_misc0) & 0x80)) + ; + /* + * For best noise performance of the analog blocks using the + * outputs of the bandgap, the reftop_selfbiasoff bit should + * be set. + */ + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &mxc_ccm->ana_misc0_set); +} + + #ifdef CONFIG_MX6SL static void set_preclk_from_osc(void) { @@ -275,6 +292,13 @@ int arch_cpu_init(void) clear_mmdc_ch_mask(); /* + * Disable self-bias circuit in the analog bandap. + * The self-bias circuit is used by the bandgap during startup. + * This bit should be set after the bandgap has initialized. + */ + init_bandgap(); + + /* * When low freq boot is enabled, ROM will not set AHB * freq, so we need to ensure AHB freq is 132MHz in such * scenario. diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 39f3c07..0592ce0 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1063,4 +1063,6 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 + #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ -- 1.8.4

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[U-Boot] [PATCH] ls1:config: Add USB support for ls1021atwr
by Ramneek Mehresh 15 Jan '15

15 Jan '15

Add USB EHCI/XHCI support for ls1021atwr platform and making xHCI as default mode Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> --- include/configs/ls1021atwr.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 45b2272..109e58c 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -28,6 +28,34 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* + * USB + */ +/*EHCI Support*/ +/*#define CONFIG_HAS_FSL_DR_USB*/ + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + +/*XHCI Support*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 1 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + +/* * Generic Timer Definitions */ #define GENERIC_TIMER_CLK 12500000 -- 1.8.3.1

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[U-Boot] [PATCH v2] x86: ahci: Make sure interface is not busy after enabling the port
by Bin Meng 15 Jan '15

15 Jan '15

Each time U-Boot boots on Intel Crown Bay board, the displayed hard drive information is wrong. It could be either wrong capacity or just a 'Capacity: not available' message. After enabling the debug switch, we can see the scsi inquiry command did not execute successfully. However, doing a 'scsi scan' in the U-Boot shell does not expose this issue. SCSI: Target spinup took 0 ms. SATA link 1 timeout. AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst scanning bus for devices... ahci_device_data_io: 0 byte transferred. <--- scsi inquiry fails ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. Device 0: (0:0) Vendor: ATA Prod.: Rev: ?8 Type: Hard Disk Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512) Found 1 device(s). So uninitialized contents on the stack were passed to dev_print() to display those wrong information. The symptom were observed on two hard drives (one is Seagate, the other one is Western Digital). The fix is to make sure the AHCI interface is not busy by checking the error and status information from task file register after enabling the port in ahci_port_start() before proceeding other operations like scsi_scan(). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Return error codes in ahci_port_start() when timeout - Use get_timer() instead of plain loop when checking tfdata status drivers/block/ahci.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index c9a3beb..bbc7e7d 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -500,6 +500,20 @@ static void ahci_set_feature(u8 port) } #endif +static int wait_spinup(volatile u8 *port_mmio) +{ + ulong start; + u32 tf_data; + + start = get_timer(0); + do { + tf_data = readl(port_mmio + PORT_TFDATA); + if (!(tf_data & ATA_BUSY)) + return 0; + } while (get_timer(start) < WAIT_MS_SPINUP); + + return -ETIMEDOUT; +} static int ahci_port_start(u8 port) { @@ -566,7 +580,11 @@ static int ahci_port_start(u8 port) debug("Exit start port %d\n", port); - return 0; + /* + * Make sure interface is not busy based on error and status + * information from task file data register before proceeding + */ + return wait_spinup(port_mmio); } -- 1.8.2.1

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[U-Boot] [PATCH] x86: Fix out of bounds irq handlers access
by Sebastien Ronsse 15 Jan '15

15 Jan '15

Using coreboot-x86_defconfig, the following error occurred prior to this modification: CC arch/x86/lib/interrupts arch/x86/lib/interrupts.c: In function ‘do_irqinfo’: arch/x86/lib/interrupts.c:134:24: error: iteration 16u invokes undefined behavior [-Werror=aggressive-loop-optimizations] if (irq_handlers[irq].handler != NULL) { ^ arch/x86/lib/interrupts.c:133:2: note: containing loop for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) { ^ cc1: all warnings being treated as errors scripts/Makefile.build:275: recipe for target 'arch/x86/lib/interrupts.o' failed make[1]: *** [arch/x86/lib/interrupts.o] Error 1 Makefile:1093: recipe for target 'arch/x86/lib' failed make: *** [arch/x86/lib] Error 2 Signed-off-by: Sebastien Ronsse <sronsse(a)gmail.com> --- arch/x86/lib/interrupts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index 6bb22d2..146ad11 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -130,7 +130,7 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Interrupt-Information:\n"); printf("Nr Routine Arg Count\n"); - for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) { + for (irq = 0; irq < CONFIG_SYS_NUM_IRQS; irq++) { if (irq_handlers[irq].handler != NULL) { printf("%02d %08lx %08lx %d\n", irq, -- 2.0.0

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[U-Boot] [PATCH v2 1/3] samsung: board: support eMMC reset using DT
by Joonyoung Shim 15 Jan '15

15 Jan '15

Some exynos boards require special handling of nRESET_OUT line for eMMC memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards. This will support eMMC reset using DT from reset_misc of samsung common board file. Signed-off-by: Joonyoung Shim <jy0922.shim(a)samsung.com> --- board/samsung/common/board.c | 28 ++++++++++++++++++++++++++ board/samsung/odroid/odroid.c | 8 -------- doc/device-tree-bindings/exynos/emmc-reset.txt | 15 ++++++++++++++ 3 files changed, 43 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/exynos/emmc-reset.txt diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 8b4c8e9..da2245f 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -355,3 +355,31 @@ int misc_init_r(void) return 0; } #endif + +void reset_misc(void) +{ + struct gpio_desc gpio = {}; + int node; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, + "samsung,emmc-reset"); + if (node < 0) + return; + + gpio_request_by_name_nodev(gd->fdt_blob, node, "reset-gpio", 0, &gpio, + GPIOD_IS_OUT); + + if (dm_gpio_is_valid(&gpio)) { + /* + * Reset eMMC + * + * FIXME: Need to optimize delay time. Minimum 1usec pulse is + * required by 'JEDEC Standard No.84-A441' (eMMC) + * document but real delay time is expected to greater + * than 1usec. + */ + dm_gpio_set_value(&gpio, 0); + mdelay(10); + dm_gpio_set_value(&gpio, 1); + } +} diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index b7d2381..b648832 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -515,11 +515,3 @@ int board_usb_init(int index, enum usb_init_type init) return s3c_udc_probe(&s5pc210_otg_data); } #endif - -void reset_misc(void) -{ - /* Reset eMMC*/ - gpio_set_value(EXYNOS4X12_GPIO_K12, 0); - mdelay(10); - gpio_set_value(EXYNOS4X12_GPIO_K12, 1); -} diff --git a/doc/device-tree-bindings/exynos/emmc-reset.txt b/doc/device-tree-bindings/exynos/emmc-reset.txt new file mode 100644 index 0000000..5e7ba26 --- /dev/null +++ b/doc/device-tree-bindings/exynos/emmc-reset.txt @@ -0,0 +1,15 @@ +* Samsung eMMC reset + +Some exynos boards require special handling of nRESET_OUT line for eMMC memory +to perform complete reboot. + +Required properties: +- compatible: should be "samsung,emmc-reset" +- reset-gpio: gpio chip for eMMC reset. + +Example: + +emmc-reset { + compatible = "samsung,emmc-reset"; + reset-gpio = <&gpk1 2 0>; +}; -- 1.9.1

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[U-Boot] [PATCH] generic-board: show model name in board_init_f() too
by Masahiro Yamada 15 Jan '15

15 Jan '15

The common/board_r.c has show_model_r() to display the model name if the DTB has a "model" property. It sounds useful to have a similar function in common/board_f.c too because most of the boards show their board name before relocation. Instead of implementing the same function in both common/board_f.c and common/board_r.c, let's split it up into common/show_board_info.c. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- common/Makefile | 2 ++ common/board_f.c | 2 +- common/board_info.c | 34 ++++++++++++++++++++++++++++++++++ common/board_r.c | 18 +----------------- include/common.h | 13 +++++++------ 5 files changed, 45 insertions(+), 24 deletions(-) create mode 100644 common/board_info.c diff --git a/common/Makefile b/common/Makefile index 9c47e20..8de1ac7 100644 --- a/common/Makefile +++ b/common/Makefile @@ -37,6 +37,8 @@ endif # boards obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o # core command obj-y += cmd_boot.o diff --git a/common/board_f.c b/common/board_f.c index 98c9c72..48acc7d 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -886,7 +886,7 @@ static init_fnc_t init_sequence_f[] = { prt_mpc5xxx_clks, #endif /* CONFIG_MPC5xxx */ #if defined(CONFIG_DISPLAY_BOARDINFO) - checkboard, /* display board info */ + show_board_info, #endif INIT_FUNC_WATCHDOG_INIT #if defined(CONFIG_MISC_INIT_F) diff --git a/common/board_info.c b/common/board_info.c new file mode 100644 index 0000000..e0d5cef --- /dev/null +++ b/common/board_info.c @@ -0,0 +1,34 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/compiler.h> + +int __weak checkboard(void) +{ + printf("Board: Unknown\n"); + return 0; +} + +/* + * If the root node of the DTB has a "model" property, show it. + * If CONFIG_OF_CONTROL is disabled or the "model" property is missing, + * fall back to checkboard(). + */ +int show_board_info(void) +{ +#ifdef CONFIG_OF_CONTROL + DECLARE_GLOBAL_DATA_PTR; + const char *model; + + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + + if (model) { + printf("Model: %s\n", model); + return 0; + } +#endif + + return checkboard(); +} diff --git a/common/board_r.c b/common/board_r.c index 19c6427..61fbbc8 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -498,22 +498,6 @@ static int initr_api(void) } #endif -#ifdef CONFIG_DISPLAY_BOARDINFO_LATE -static int show_model_r(void) -{ - /* Put this here so it appears on the LCD, now it is ready */ -# ifdef CONFIG_OF_CONTROL - const char *model; - - model = (char *)fdt_getprop(gd->fdt_blob, 0, "model", NULL); - printf("Model: %s\n", model ? model : "<unknown>"); -# else - checkboard(); -# endif - return 0; -} -#endif - /* enable exceptions */ #ifdef CONFIG_ARM static int initr_enable_interrupts(void) @@ -823,7 +807,7 @@ init_fnc_t init_sequence_r[] = { #endif console_init_r, /* fully init console as a device */ #ifdef CONFIG_DISPLAY_BOARDINFO_LATE - show_model_r, + show_board_info, #endif #ifdef CONFIG_ARCH_MISC_INIT arch_misc_init, /* miscellaneous arch-dependent init */ diff --git a/include/common.h b/include/common.h index f1ab2cf..c82336f 100644 --- a/include/common.h +++ b/include/common.h @@ -231,12 +231,13 @@ int run_command_list(const char *cmd, int len, int flag); extern char console_buffer[]; /* arch/$(ARCH)/lib/board.c */ -void board_init_f(ulong); -void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); -int checkboard (void); -int checkflash (void); -int checkdram (void); -int last_stage_init(void); +void board_init_f(ulong); +void board_init_r(gd_t *, ulong) __attribute__ ((noreturn)); +int checkboard(void); +int show_board_info(void); +int checkflash(void); +int checkdram(void); +int last_stage_init(void); extern ulong monitor_flash_len; int mac_read_from_eeprom(void); extern u8 __dtb_dt_begin[]; /* embedded device tree blob */ -- 1.9.1

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[U-Boot] [PATCH 0/4] Exynos5: Fix warnings and enrich clock_get_periph_rate
by Akshay Saraswat 15 Jan '15

15 Jan '15

This patch series does following changes - 1. Removing compiler warnings for clock_get_periph_rate. 2. Adding and enabling support for Exynos542x in clock_get_periph_rate. 3. Replacing peripheral specific function calls with clock_get_periph_rate. 4. Remove code from clocks file which became useless due to introduction of clock_get_periph_rate. Akshay Saraswat (4): Exynos5: Fix compiler warnings due to clock_get_periph_rate Exynos542x: Add and enable get_periph_rate support Exynos5: Use clock_get_periph_rate generic API Exynos5: Remove dead code for fetching clocks arch/arm/cpu/armv7/exynos/clock.c | 572 ++++++++++++++++----------------- arch/arm/include/asm/arch-exynos/clk.h | 8 + 2 files changed, 278 insertions(+), 302 deletions(-) -- 1.9.1

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