January 2015 - U-Boot

[U-Boot] [PATCH 0/10] x86: Add generic VESA video driver
by Simon Glass 01 Aug '19

01 Aug '19

This series introduces a generic VESA video driver and adjusts the generic PCI ROM support to support it. It also fixes up some problems which prevent this from working on PowerPC at present. It is now possible to use VESA graphics: - On PowerPC, using the x86 emulator - On x86, using either the x86 emulator or native code execution As it turns out, on the only platform I have tested (link), the x86 emulator is only slightly slower that native code execution (200ms difference). Still, we may as well leave this feature in there. VGA ROMs are a very old technology but they are still used by modern platforms, including at least link and some Atom designs. Simon Glass (10): bios_emulator: Fix an #ifdef typo in the header file x86: Correct endianness isues in pci_rom x86: Support ROMs on other archs bios_emulator: Don't display error when emulator terminates bios_emulator: Add some VESA interface debugging x86: pci: Don't stop when we get a vendor/device mismatch x86: Add a VESA video driver x86: Drop the x86_fb driver x86: Access the VGA ROM when needed RFC: Test code for glacier PCI video support arch/x86/include/asm/u-boot-x86.h | 2 + drivers/bios_emulator/atibios.c | 161 +++++++++++++++++++++++---- drivers/bios_emulator/include/x86emu/debug.h | 2 +- drivers/bios_emulator/x86emu/ops.c | 2 +- drivers/pci/pci_auto.c | 28 ++++- drivers/pci/pci_rom.c | 40 ++++--- drivers/video/Makefile | 2 +- drivers/video/vesa_fb.c | 64 +++++++++++ drivers/video/x86_fb.c | 38 ------- include/configs/canyonlands.h | 31 ++++++ include/configs/chromebook_link.h | 2 +- include/pci.h | 9 ++ include/pci_rom.h | 1 - include/vbe.h | 9 +- 14 files changed, 312 insertions(+), 79 deletions(-) create mode 100644 drivers/video/vesa_fb.c delete mode 100644 drivers/video/x86_fb.c -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] Fwd: u-boot.img size limit for spl fat load ?
by Ayoub Zaki 18 Oct '17

18 Oct '17

Hello Albert, First tank you so much for inversting your time for replying. I put some printf in the code and SPL is hanging in spl_load_image_fat function. I also enable the DEBUG messages here the complete log file : http://pastebin.com/raw.php?i=BwUJXDDb So I suspect that SPL is not allocating enough memory to load u-boot.img but I can't find where this size limit is set and where I can change it. Cheers, Ayoub > 2015-01-19 8:08 GMT+01:00 Albert ARIBAUD <albert.u.boot(a)aribaud.net>: > > > Hello Ayoub, > > > > On Fri, 16 Jan 2015 15:42:37 +0100, Ayoub Zaki > > <ayoub.zaki(a)googlemail.com> wrote: > > > Hello list, > > > > > > I'm using u-boot-2014.10 and trying to build it with LCD support for the > > > Beaglebone black to include a Boot logo image. > > > It seems that spl hangs while fat loading a 2.8MB sized u-boot.img ! > > > I reduced the the logo header file and rebuild u-boot, that worked for a > > > 1.6MB sized u-boot.img. > > > Is there any size limit for u-boot ? how to increase the memory allocated > > > by spl ? > > > > There should not be a size limit for SPL fat load. > > > > What may happen is that SPL code is overwritten before it exits, or > > U-Boot itself is corrupted after being loaded. > > > > I assume you've seen the SPL banner and not the U-Boot one; that alone > > does not tell us whether SPL or U-Boot did hang. Can you build U-boot > > with debug enabled? If this results in too big an SPL image, then try > > and at least enable debug for the image chainloading parts, so that you > > can see how far SPL code gets run. > > > > > Thanks you. > > > > No problem. > > > > Amicalement, > > -- > > Albert.

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[U-Boot] [PATCH] tools/fw_env: use fsync to ensure that data is physically stored
by Michael Heimpold 25 Jul '17

25 Jul '17

Closing a file descriptor does not guarantee that the data has been successfully saved to disk, as the kernel might defer the write. Signed-off-by: Michael Heimpold <mhei(a)heimpold.de> --- tools/env/fw_env.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 428e374..0420495 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -1033,7 +1033,19 @@ static int flash_io (int mode) rc = flash_write (fd_current, fd_target, dev_target); + if (fsync (fd_current)) { + fprintf (stderr, + "fsync failed on %s: %s\n", + DEVNAME (dev_current), strerror (errno)); + } + if (HaveRedundEnv) { + if (fsync (fd_target)) { + fprintf (stderr, + "fsync failed on %s: %s\n", + DEVNAME (dev_current), strerror (errno)); + } + if (close (fd_target)) { fprintf (stderr, "I/O error on %s: %s\n", -- 1.7.10.4

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[U-Boot] [PATCH] net: Add mv88e60xx support to the mv88e61xx driver
by Joshua Scott 26 Apr '16

26 Apr '16

The Marvell Link Street mv88e60xx is a series of FastEthernet switch chips, some of which also support Gigabit ports. It is similar to the mv88e61xx series which support Gigabit on all ports. There is already a driver for the mv88e61xx in U-Boot, and this patch updates it to also work with the mv88e60xx. The main change that was required was the size of the port bitmaps. Previously, 8-bit port bitmaps were in use, as the driver had only been used with six-port mv88e61xx devices. This has been changed so that 16-bit port bitmaps are now used, which covers the largest port-counts available for the mv88e60xx / mv88e61xx. Reviewed-by: Chris Packham <chris.packham(a)alliedtelesis.co.nz> Signed-off-by: Joshua Scott <joshua.scott(a)alliedtelesis.co.nz> --- drivers/net/phy/mv88e61xx.c | 29 +++++++++++++++++++++-------- drivers/net/phy/mv88e61xx.h | 2 -- include/netdev.h | 20 +++++++++++++++----- 3 files changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 302abe8..79204f3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -215,17 +215,17 @@ static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) u32 port_mask = swconfig->ports_enabled; /* apply internal vlan config */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + for (prt = 0; prt < swconfig->numports; prt++) { /* only for enabled ports */ if ((1 << prt) & port_mask) { /* take vlan map from swconfig */ - u8 vlanmap = swconfig->vlancfg[prt]; + u16 vlanmap = swconfig->vlancfg[prt]; /* remove disabled ports from vlan map */ vlanmap &= swconfig->ports_enabled; /* apply vlan map to port */ RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_VMAP_REG, &reg); - reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); + reg &= ~((1 << swconfig->numports) - 1); reg |= vlanmap; WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_VMAP_REG, reg); @@ -331,32 +331,44 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) return -1; } - if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { + if (!(swconfig->cpuport & ((1 << 4) | (1 << 5) | (1 << 10)))) { swconfig->cpuport = (1 << 5); printf("Invalid cpu port config, using default port5\n"); } RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, &reg); switch (reg &= 0xfff0) { + case 0x0980: + idstr = "88E6096"; + swconfig->numports = 0x0b; + break; + case 0x0990: + idstr = "88E6097"; + swconfig->numports = 0x0b; + break; case 0x1610: idstr = "88E6161"; + swconfig->numports = 0x06; break; case 0x1650: idstr = "88E6165"; + swconfig->numports = 0x06; break; case 0x1210: idstr = "88E6123"; + swconfig->numports = 0x06; /* ports 2,3,4 not available */ swconfig->ports_enabled &= 0x023; break; default: /* Could not detect switch id */ idstr = "88E61??"; + swconfig->numports = 0x06; break; } /* be sure all ports are disabled */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + for (prt = 0; prt < swconfig->numports; prt++) { RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, &reg); reg &= ~0x3; WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); @@ -405,12 +417,13 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); } - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + for (prt = 0; prt < swconfig->numports; prt++) { /* configure port's PHY */ if (!((1 << prt) & swconfig->cpuport)) { - /* port 4 has phy 6, not 4 */ - int phy = (prt == 4) ? 6 : prt; + /* 88e61xx: port 4 has phy 6, not 4 */ + int phy = (swconfig->numports == 6 && + prt == 4) ? 6 : prt; if (mv88361xx_powerup(swconfig, phy)) return -1; if (mv88361xx_reverse_mdipn(swconfig, phy)) diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h index 9c62e4a..b289f21 100644 --- a/drivers/net/phy/mv88e61xx.h +++ b/drivers/net/phy/mv88e61xx.h @@ -11,8 +11,6 @@ #include <miiphy.h> -#define MV88E61XX_CPU_PORT 0x5 - #define MV88E61XX_PHY_TIMEOUT 100000 /* port dev-addr (= port + 0x10) */ diff --git a/include/netdev.h b/include/netdev.h index 34651ab..cbd0420 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -154,7 +154,9 @@ static inline int pci_eth_init(bd_t *bis) #if defined(CONFIG_MV88E61XX_SWITCH) /* constants for any 88E61xx switch */ -#define MV88E61XX_MAX_PORTS_NUM 6 +/* Allow enough space in the struct to fit 11 ports, as this is + * the number used in the mv88e60xx */ +#define MV88E61XX_MAX_PORTS_NUM 0x0b enum mv88e61xx_cfg_mdip { MV88E61XX_MDIP_NOCHANGE, @@ -180,13 +182,14 @@ enum mv88e61xx_cfg_prtstt { struct mv88e61xx_config { char *name; - u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; + u16 vlancfg[MV88E61XX_MAX_PORTS_NUM]; enum mv88e61xx_cfg_rgmiid rgmii_delay; enum mv88e61xx_cfg_prtstt portstate; enum mv88e61xx_cfg_ledinit led_init; enum mv88e61xx_cfg_mdip mdip; + u32 numports; u32 ports_enabled; - u8 cpuport; + u32 cpuport; }; /* @@ -196,10 +199,17 @@ struct mv88e61xx_config { */ /* Switch mode : routes any port to any port */ -#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } +#define MV88E61XX_VLANCFG_SWITCH { 0x003F, 0x003F, 0x003F, 0x003F, 0x003F, \ + 0x003F, 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000 } /* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ -#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } +#define MV88E61XX_VLANCFG_ROUTER { 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, \ + 0x001F, 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000 } +#define MV88E60XX_VLANCFG_ROUTER { 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, \ + 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, \ + 0x03ff } int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); #endif /* CONFIG_MV88E61XX_SWITCH */ -- 1.9.1

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[U-Boot] [PATCH 01/10] video: Add S3C24xx framebuffer support
by Marek Vasut 22 Feb '16

22 Feb '16

Add basic framebuffer driver for the S3C24xx family of CPUs. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Anatolij Gustschin <agust(a)denx.de> Cc: Kyungmin Park <kyungmin.park(a)samsung.com> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> Cc: Vladimir Zapolskiy <vz(a)mleia.com> V2: Keep the Makefile sorted. --- drivers/video/Makefile | 1 + drivers/video/cfb_console.c | 2 +- drivers/video/s3c-fb.c | 172 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 174 insertions(+), 1 deletion(-) create mode 100644 drivers/video/s3c-fb.c diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 14a6781..0e407d0 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +obj-$(CONFIG_VIDEO_S3C) += s3c-fb.o videomodes.o obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 9231927..98d10e3 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -135,7 +135,7 @@ #endif #endif -#ifdef CONFIG_VIDEO_MXS +#if defined(CONFIG_VIDEO_MXS) || defined(CONFIG_VIDEO_S3C) #define VIDEO_FB_16BPP_WORD_SWAP #endif diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c new file mode 100644 index 0000000..521eb75 --- /dev/null +++ b/drivers/video/s3c-fb.c @@ -0,0 +1,172 @@ +/* + * S3C24x0 LCD driver + * + * NOTE: Only 16/24 bpp operation with TFT LCD is supported. + * + * Copyright (C) 2014 Marek Vasut <marex(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <video_fb.h> + +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> + +#include "videomodes.h" + +static GraphicDevice panel; + +/* S3C requires the FB to be 4MiB aligned. */ +#define S3CFB_ALIGN (4 << 20) + +#define S3CFB_LCDCON1_CLKVAL(x) ((x) << 8) +#define S3CFB_LCDCON1_PNRMODE_TFT (0x3 << 5) +#define S3CFB_LCDCON1_BPPMODE_TFT_16BPP (0xc << 1) +#define S3CFB_LCDCON1_BPPMODE_TFT_24BPP (0xd << 1) + +#define S3CFB_LCDCON2_VBPD(x) ((x) << 24) +#define S3CFB_LCDCON2_LINEVAL(x) ((x) << 14) +#define S3CFB_LCDCON2_VFPD(x) ((x) << 6) +#define S3CFB_LCDCON2_VSPW(x) ((x) << 0) + +#define S3CFB_LCDCON3_HBPD(x) ((x) << 19) +#define S3CFB_LCDCON3_HOZVAL(x) ((x) << 8) +#define S3CFB_LCDCON3_HFPD(x) ((x) << 0) + +#define S3CFB_LCDCON4_HSPW(x) ((x) << 0) + +#define S3CFB_LCDCON5_BPP24BL (1 << 12) +#define S3CFB_LCDCON5_FRM565 (1 << 11) +#define S3CFB_LCDCON5_HWSWP (1 << 0) + +#define PS2KHZ(ps) (1000000000UL / (ps)) + +/* + * Example: + * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\ + * pclk:30066,le:41,ri:89,up:45,lo:12, + * hs:1,vs:1,sync:100663296,vmode:0 + */ +static void s3c_lcd_init(GraphicDevice *panel, + struct ctfb_res_modes *mode, int bpp) +{ + uint32_t clk_divider; + struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd(); + + /* Stop the controller. */ + clrbits_le32(&regs->lcdcon1, 1); + + /* Calculate clock divider. */ + clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000; + clk_divider = DIV_ROUND_UP(clk_divider, 2); + if (clk_divider) + clk_divider -= 1; + + /* Program LCD configuration. */ + switch (bpp) { + case 16: + writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + &regs->lcdcon1); + writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565, + &regs->lcdcon5); + break; + case 24: + writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + &regs->lcdcon1); + writel(S3CFB_LCDCON5_BPP24BL, &regs->lcdcon5); + break; + } + + writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) | + S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) | + S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) | + S3CFB_LCDCON2_VSPW(mode->vsync_len - 1), + &regs->lcdcon2); + + writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) | + S3CFB_LCDCON3_HFPD(mode->left_margin - 1) | + S3CFB_LCDCON3_HOZVAL(mode->xres - 1), + &regs->lcdcon3); + + writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1), + &regs->lcdcon4); + + /* Write FB address. */ + writel(panel->frameAdrs >> 1, &regs->lcdsaddr1); + writel((panel->frameAdrs + + (mode->xres * mode->yres * panel->gdfBytesPP)) >> 1, + &regs->lcdsaddr2); + writel(mode->xres * bpp / 16, &regs->lcdsaddr3); + + /* Start the controller. */ + setbits_le32(&regs->lcdcon1, 1); +} + +void *video_hw_init(void) +{ + int bpp = -1; + char *penv; + void *fb; + struct ctfb_res_modes mode; + + puts("Video: "); + + /* Suck display configuration from "videomode" variable */ + penv = getenv("videomode"); + if (!penv) { + puts("S3CFB: 'videomode' variable not set!\n"); + return NULL; + } + + bpp = video_get_params(&mode, penv); + + /* fill in Graphic device struct */ + sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); + + panel.winSizeX = mode.xres; + panel.winSizeY = mode.yres; + panel.plnSizeX = mode.xres; + panel.plnSizeY = mode.yres; + + switch (bpp) { + case 24: + panel.gdfBytesPP = 4; + panel.gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + panel.gdfBytesPP = 2; + panel.gdfIndex = GDF_16BIT_565RGB; + break; + default: + printf("S3CFB: Invalid BPP specified! (bpp = %i)\n", bpp); + return NULL; + } + + panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; + + /* Allocate framebuffer */ + fb = memalign(S3CFB_ALIGN, roundup(panel.memSize, S3CFB_ALIGN)); + if (!fb) { + printf("S3CFB: Error allocating framebuffer!\n"); + return NULL; + } + + /* Wipe framebuffer */ + memset(fb, 0, panel.memSize); + + panel.frameAdrs = (u32)fb; + + printf("%s\n", panel.modeIdent); + + /* Start framebuffer */ + s3c_lcd_init(&panel, &mode, bpp); + + return (void *)&panel; +} -- 2.1.1

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[U-Boot] [PATCH 0/4 v4] arm: socfpga: Add Cadence QSPI support
by Stefan Roese 14 Jan '16

14 Jan '16

Hi! So this is my 4th posting regarding the Candence SPI driver on SoCFPGA. Again, SPI NOR flash is working. At least on SoCrates and on another custom SoCFPGA based board. The main change in this version is, that the Cadence driver now is a driver model (DM) based driver. And this needs the DT support which I posted just before. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that I have patches to support the Designware SPI master controller also via DM in the queue. I'll post them shortly. Thanks, Stefan Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Pavel Machek <pavel(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com>

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[U-Boot] [RFC PATCH 1/2] common: Add new clk command
by Michal Simek 05 Jan '16

05 Jan '16

Command provides just dump subcommand for showing clock frequencies in a soc. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- README | 1 + common/Makefile | 1 + common/cmd_clk.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++ include/clk.h | 6 ++++++ include/config_cmd_all.h | 1 + 5 files changed, 60 insertions(+) create mode 100644 common/cmd_clk.c create mode 100644 include/clk.h diff --git a/README b/README index aea82be..0087649 100644 --- a/README +++ b/README @@ -887,6 +887,7 @@ The following options need to be configured: CONFIG_CMD_BSP * Board specific commands CONFIG_CMD_BOOTD bootd CONFIG_CMD_CACHE * icache, dcache + CONFIG_CMD_CLK * clock command support CONFIG_CMD_CONSOLE coninfo CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DATE * support for RTC, date/time... diff --git a/common/Makefile b/common/Makefile index d12cba5..a000e7d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o obj-$(CONFIG_CMD_CACHE) += cmd_cache.o obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o +obj-$(CONFIG_CMD_CLK) += cmd_clk.o obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o diff --git a/common/cmd_clk.c b/common/cmd_clk.c new file mode 100644 index 0000000..6d3d46a --- /dev/null +++ b/common/cmd_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <command.h> +#include <clk.h> + +int __weak soc_clk_dump(void) +{ + puts("Not implemented\n"); + return 1; +} + +static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + return soc_clk_dump(); +} + +static cmd_tbl_t cmd_clk_sub[] = { + U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""), +}; + +static int do_clk(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return CMD_RET_USAGE; + + /* Strip off leading 'clk' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_clk_sub[0], ARRAY_SIZE(cmd_clk_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +#ifdef CONFIG_SYS_LONGHELP +static char clk_help_text[] = + "dump - Print clock frequencies"; +#endif + +U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text); diff --git a/include/clk.h b/include/clk.h new file mode 100644 index 0000000..df4570c --- /dev/null +++ b/include/clk.h @@ -0,0 +1,6 @@ +#ifndef _CLK_H_ +#define _CLK_H_ + +int soc_clk_dump(void); + +#endif /* _CLK_H_ */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index d847069..3e8983f 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_BSP /* Board Specific functions */ #define CONFIG_CMD_CACHE /* icache, dcache */ #define CONFIG_CMD_CDP /* Cisco Discovery Protocol */ +#define CONFIG_CMD_CLK /* Clock support */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_DATE /* support for RTC, date/time...*/ #define CONFIG_CMD_DHCP /* DHCP Support */ -- 1.8.2.3

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[U-Boot] [PATCH v2 0/7] mtd/st_smi: Add fixes for smi driver
by Vipin Kumar 14 Dec '15

14 Dec '15

Modifications in v2 (Review comments incorporation) - Use setbits_le32 and clrbits_le32 whereever applicable in patch-set - Define smi_mtd_init() routine irrespective of CONFIG_MTD_DEVICE Modifications in v1 - Add MTD support for smi driver - Write to flash in a tight loop - Alphabetically sort the list of devices - Avoid issuing multiple write enable commands Armando Visconti (1): mtd/st_smi: Add support for Micron N25Q128 Flash Vipin Kumar (6): mtd/st_smi: Clear error flags while initiating a fresh write mtd/st_smi: Rearrange the supported devices in alphabetical order mtd/st_smi: Avoid issuing multiple WE commands mtd/st_smi: Write to flash in a tight loop mtd/st_smi: Use page sizes respective to flash mtd/st_smi: Add mtd support for smi drivers/mtd/st_smi.c | 260 ++++++++++++++++++++++++++++++++++++++------- include/linux/mtd/st_smi.h | 1 - 2 files changed, 223 insertions(+), 38 deletions(-) -- 1.8.0

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[U-Boot] [PATCH] FSL SPI read fix.
by Dale Smith 14 Dec '15

14 Dec '15

The fsl spi engine is non functional when reading from a device. This patch fixes it. Note that none of the other spi interfaces parse through the datastream looking for 0x0b bytes. -Dale diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index a1ebd33..737719b 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -291,17 +291,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, debug("***spi_xfer:...%08x readed\n", tmpdin); } } - if (data_in) { - memcpy(data_in, buffer + 2 * cmd_len, tran_len); - if (*buffer == 0x0b) { - data_in += tran_len; - data_len -= tran_len; - *(int *)buffer += tran_len; - } - } spi_cs_deactivate(slave); } - + if (data_in) + memcpy(data_in, buffer + rx_offset, len); free(buffer); return 0; }

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Re: [U-Boot] [linux-sunxi] Mainline U-Boot, EHCI, usbkbd not working (workaround)
by B.R. Oake 13 Dec '15

13 Dec '15

(This started on the linux-sunxi mailing list but will hopefully be of interest on the U-Boot list) On 04/01/15 13:45, Lars Doelle wrote: > while testing with mainline u-boot, I came over the > problem, that the USB keyboard is not recognized. > > The device is an A20-OLinuXIno-LIME2. I used the > current A20-OLinuXino-Lime2_defconfig for building. > > In my understanding, the issue should be reproducible > with all devices having an EHCI root hub. > > --- > sun7i# usb reset > (Re)start USB... > USB0: USB EHCI 1.00 > scanning bus 0 for devices... cannot reset port 1!? > 1 USB Device(s) found > USB1: USB EHCI 1.00 > scanning bus 1 for devices... 1 USB Device(s) found > scanning usb for storage devices... 0 Storage Device(s) found > sun7i# usb tree > USB device tree: > 1 Hub (480 Mb/s, 0mA) > u-boot EHCI Host Controller > > 2 Hub (480 Mb/s, 0mA) > u-boot EHCI Host Controller > --- > > As a workaround, i plugged an USB hub in between: > [...] I also have this problem. I've tried three different USB keyboards on an A20-Olinuxino-Micro and a Banana Pi, and I always get that error "cannot reset port N!?" where N is whichever USB socket I've plugged it into, and U-Boot cannot see the keyboard. Once Linux has loaded, the keyboard works without any trouble. Can anyone suggest what is causing this? Thank you, B.R. Oake.

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