April 2014 - U-Boot

[U-Boot] [RFC PATCH 0/5] introduce get_maintainer.pl
by Daniel Schwierzeck 22 Apr '14

22 Apr '14

This series imports get_maintainer.pl from kernel and reintroduce the MAINTAINERS file in the according format. Currently one have to manually grep all infos about board maintainers or custodians from various sources like git log, wiki or boards.cfg. get_maintainer.pl makes this task much easier. Also patman is already able to use it for cc-cmd. Furthermore it solves the concerns raised in discussion [1] regarding the introduction of Kconfig. This RFC series adds an additional MAINTAINERS.boards file, which is generated from boards.cfg with the script added in patch 1/5. The get_maintainer.pl script is modified to handle both MAINTAINERS files. The MAINTAINERS file contains all custodians and is hand-written based on infos from wiki [2], u-boot git forks [3]. Thus the source files infos (F:) are not complete yet. Furthermore status (S:) and maintainership (M:) for some custodian trees are probably wrong. Any help in completing and fixing that is appreciated. Each entry in the MAINTAINERS.boards starts with the line 'BOARD $boardname $vendorname'. Status (S:) and maintainership (M:) are taken from boards.cfg. If one of ARCH, CPU or SOC of the board is maintained in a dedicated custodian tree, the Git URL of that tree is added (T:). Source files (F:) are set to board/$boardname (or board/$vendorname/$boardname) and include/configs/$boardname.h. If this series get accepted, both MAINTAINERS files could be merged. The script from patch 1/5 and boards.cfg are obsolete then. [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg134341.html [2] http://www.denx.de/wiki/U-Boot/Custodians [3] http://git.denx.de/?p=u-boot.git;a=forks Daniel Schwierzeck (5): scripts: add script for converting boards.cfg to MAINTAINERS MAINTAINERS: add initial version MAINTAINERS.boards: add initial version get_maintainer.pl: import script from linux 3.14 get_maintainer.pl: adapt to U-Boot tree MAINTAINERS | 338 +++ MAINTAINERS.boards | 4522 ++++++++++++++++++++++++++++++++++++++ scripts/boardscfg2maintainers.sh | 259 +++ scripts/get_maintainer.pl | 2262 +++++++++++++++++++ 4 files changed, 7381 insertions(+) create mode 100644 MAINTAINERS create mode 100644 MAINTAINERS.boards create mode 100755 scripts/boardscfg2maintainers.sh create mode 100755 scripts/get_maintainer.pl -- 1.9.2

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[U-Boot] [PATCH ][v3] powerpc/T4QDS: add two stage boot of nand/sd
by shh.xie＠gmail.com 22 Apr '14

22 Apr '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> Add support of 2 stage NAND/SD boot loader using SPL framework. PBL initialise the internal SRAM and copy SPL, this further initialise DDR using SPD and environment and copy u-boot from NAND/SD to DDR, finally SPL transfer control to u-boot. NOR uses CS1 instead of CS2 when NAND boot, fix it. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- changes for v3: updated env to adapt to new spl. changes for v2: added Secure Boot header(32KB), adjust settings accordingly. board/freescale/t4qds/Makefile | 6 +- board/freescale/t4qds/ddr.c | 6 +- board/freescale/t4qds/spl.c | 141 +++++++++++++++++++++++++++++++++++++++++ board/freescale/t4qds/tlb.c | 8 ++- boards.cfg | 7 +- doc/README.t4240qds | 53 ++++++++++++++++ include/configs/T4240QDS.h | 99 +++++++++++++++++++++++------ include/configs/t4qds.h | 17 ++++- 8 files changed, 310 insertions(+), 27 deletions(-) create mode 100644 board/freescale/t4qds/spl.c diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index 2b1f7aa..4e8e5cb 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T4240QDS) += t4240qds.o obj-$(CONFIG_T4240EMU) += t4240emu.o -obj-y += ddr.o obj-$(CONFIG_T4240QDS)+= eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 7586cc3..7abd38d 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -117,11 +117,15 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c new file mode 100644 index 0000000..0c6156e --- /dev/null +++ b/board/freescale/t4qds/spl.c @@ -0,0 +1,141 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include "../common/qixis.h" +#include "t4240qds_qixis.h" + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + +#ifdef CONFIG_SPL_NAND_BOOT + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index b701e75..1e4d096 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -105,6 +105,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -136,6 +137,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index aac8b10..d1c0e4a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -975,13 +975,14 @@ Active powerpc mpc85xx - freescale t208xrdb Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - Active powerpc mpc85xx - freescale t4qds T4160QDS_SECURE_BOOT T4240QDS:PPC_T4160,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> -Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4160QDS_NAND T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND - +Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD - Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun(a)freescale.com> Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> -Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD - Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf <agraf(a)suse.de> diff --git a/doc/README.t4240qds b/doc/README.t4240qds index a9841fb..ef8c75f 100644 --- a/doc/README.t4240qds +++ b/doc/README.t4240qds @@ -120,3 +120,56 @@ The override voltage takes effect when booting. Note: voltage adjustment needs to be done step by step. Changing voltage too rapidly may cause current surge. The voltage stepping is done by software. Users can set the final voltage directly. + +2-stage NAND/SD boot loader +------------------------------- +PBL initializes the internal SRAM and copy SPL(160K) in SRAM. +SPL further initialise DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T4QDS +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x140000 0x15FFFF u-boot env 128KB +0x160000 0x17FFFF FMAN Ucode 128KB + +Micro SD Card memory Map on T4QDS +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0128 FMAN ucode 64KB + +Switch Settings: (ON is 1, OFF is 0) +=============== +NAND boot SW setting: +SW1[1:8] = 10000010 +SW2[1.1] = 0 +SW6[1:4] = 1001 + +SD boot SW setting: +SW1[1:8] = 00100000 +SW2[1.1] = 0 diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 1b98cfd..e4eb30f 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -19,11 +19,64 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg +#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#else +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + #endif +#endif /* CONFIG_RAMBOOT_PBL */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ @@ -64,12 +117,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -244,8 +297,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 @@ -261,6 +322,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK @@ -270,14 +339,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -379,14 +440,14 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index f8de439..36bc529 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -68,7 +68,16 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -96,7 +105,11 @@ #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R -- 1.8.0

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[U-Boot] [PATCH] powerpc/85xx: add T4080 SoC support
by Shengzhou Liu 22 Apr '14

22 Apr '14

The T4080 SoC is a low-power version of the T4240/T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- based on 'next' branch of u-boot-mpc85xx. arch/powerpc/cpu/mpc85xx/Makefile | 2 ++ arch/powerpc/cpu/mpc85xx/cpu.c | 21 +++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 5 ++++- arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 16 +++++++++++----- arch/powerpc/include/asm/fsl_errata.h | 2 ++ arch/powerpc/include/asm/immap_85xx.h | 6 ++++-- arch/powerpc/include/asm/processor.h | 1 + drivers/net/fm/Makefile | 1 + 11 files changed, 50 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4094785..ad26b43 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o obj-$(CONFIG_PPC_P5040) += p5040_ids.o obj-$(CONFIG_PPC_T4240) += t4240_ids.o obj-$(CONFIG_PPC_T4160) += t4240_ids.o +obj-$(CONFIG_PPC_T4080) += t4240_ids.o obj-$(CONFIG_PPC_B4420) += b4860_ids.o obj-$(CONFIG_PPC_B4860) += b4860_ids.o obj-$(CONFIG_PPC_T1040) += t1040_ids.o @@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o obj-$(CONFIG_PPC_P5040) += p5040_serdes.o obj-$(CONFIG_PPC_T4240) += t4240_serdes.o obj-$(CONFIG_PPC_T4160) += t4240_serdes.o +obj-$(CONFIG_PPC_T4080) += t4240_serdes.o obj-$(CONFIG_PPC_B4420) += b4860_serdes.o obj-$(CONFIG_PPC_B4860) += b4860_serdes.o obj-$(CONFIG_BSC9132) += bsc9132_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 12e8e10..55df8cb 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -77,6 +77,27 @@ int checkcpu (void) major = SVR_MAJ(svr); minor = SVR_MIN(svr); +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + if (SVR_SOC_VER(svr) == SVR_T4080) { + ccsr_rcpm_t *rcpm = + (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + + setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || + FSL_CORENET_DEVDISR2_DTSEC1_9); + setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); + setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); + + for (i = 4; i < 8; i++) + cpu_disable(i); + + /* request core4~7 into PH20 state */ + setbits_be32(&rcpm->pcph20setr, 0xf0); + + /* put the 2nd cluster into PCL10 state */ + setbits_be32(&rcpm->clpcl10setr, 1 << 1); + } +#endif + if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index ea41ffc..dcc4bff 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -462,10 +462,13 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); int enable_cluster_l2(void) { int i = 0; - u32 cluster; + u32 cluster, svr = get_svr(); ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache; + if (SVR_SOC_VER(svr) == SVR_T4080) + return 0; + cluster = in_be32(&gur->tp_cluster[i].lower); if (cluster & TP_CLUSTER_EOC) return 0; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 2d6c668..33441c9 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -123,7 +123,8 @@ void get_sys_info(sys_info_t *sys_info) * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) if (SVR_MAJ(get_svr()) >= 2) mem_pll_rat *= 2; #endif diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index ff55e3c..1f99a0a 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -172,7 +172,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 35795c4..dfedc53 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -62,6 +62,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T4240, T4240, 0), CPU_TYPE_ENTRY(T4120, T4120, 0), CPU_TYPE_ENTRY(T4160, T4160, 0), + CPU_TYPE_ENTRY(T4080, T4080, 4), CPU_TYPE_ENTRY(B4860, B4860, 0), CPU_TYPE_ENTRY(G4860, G4860, 0), CPU_TYPE_ENTRY(G4060, G4060, 0), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 864e74c..9bb0123 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -595,7 +595,8 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -611,13 +612,18 @@ #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 #else -#define CONFIG_MAX_CPUS 8 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 7 +#define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#if defined(CONFIG_PPC_T4160) +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#elif defined(CONFIG_PPC_T4080) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } +#endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 4eba85c..1e548a0 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -16,6 +16,7 @@ static inline bool has_erratum_a006379(void) u32 svr = get_svr(); if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || @@ -49,6 +50,7 @@ static inline bool has_erratum_a006261(void) return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T4240: case SVR_T4160: + case SVR_T4080: return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T1040: return IS_SVR_REV(svr, 1, 0); diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 741b861..eff573b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1748,7 +1748,8 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1848,7 +1849,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 72f30fe..a6f121e 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1111,6 +1111,7 @@ #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 #define SVR_T4160 0x824100 +#define SVR_T4080 0x824102 #define SVR_C291 0x850000 #define SVR_C292 0x850020 #define SVR_C293 0x850030 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index ee5d768..5ae3b16 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_PPC_T2080) += t2080.o obj-$(CONFIG_PPC_T2081) += t2080.o obj-$(CONFIG_PPC_T4240) += t4240.o obj-$(CONFIG_PPC_T4160) += t4240.o +obj-$(CONFIG_PPC_T4080) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o obj-$(CONFIG_PPC_B4860) += b4860.o -- 1.8.0

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[U-Boot] [PATCH][v2] powerpc/T4QDS: add two stage boot of nand/sd
by shh.xie＠gmail.com 22 Apr '14

22 Apr '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> Add support of 2 stage NAND/SD boot loader using SPL framework. PBL initialise the internal SRAM and copy SPL, this further initialise DDR using SPD and environment and copy u-boot from NAND/SD to DDR, finally SPL transfer control to u-boot. NOR uses CS1 instead of CS2 when NAND boot, fix it. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- changes for v2: added Secure Boot header(32KB), adjust settings accordingly. board/freescale/t4qds/Makefile | 6 +- board/freescale/t4qds/ddr.c | 6 +- board/freescale/t4qds/spl.c | 145 +++++++++++++++++++++++++++++++++++++++++ board/freescale/t4qds/tlb.c | 8 ++- boards.cfg | 7 +- doc/README.t4240qds | 53 +++++++++++++++ include/configs/T4240QDS.h | 99 ++++++++++++++++++++++------ include/configs/t4qds.h | 17 ++++- 8 files changed, 314 insertions(+), 27 deletions(-) create mode 100644 board/freescale/t4qds/spl.c diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index 2b1f7aa..4e8e5cb 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T4240QDS) += t4240qds.o obj-$(CONFIG_T4240EMU) += t4240emu.o -obj-y += ddr.o obj-$(CONFIG_T4240QDS)+= eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 7586cc3..7abd38d 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -117,11 +117,15 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c new file mode 100644 index 0000000..21463fb --- /dev/null +++ b/board/freescale/t4qds/spl.c @@ -0,0 +1,145 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include "../common/qixis.h" +#include "t4240qds_qixis.h" + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + +#ifdef CONFIG_SPL_NAND_BOOT + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index b701e75..1e4d096 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -105,6 +105,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -136,6 +137,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index aac8b10..d1c0e4a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -975,13 +975,14 @@ Active powerpc mpc85xx - freescale t208xrdb Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - Active powerpc mpc85xx - freescale t4qds T4160QDS_SECURE_BOOT T4240QDS:PPC_T4160,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> -Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4160QDS_NAND T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND - +Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD - Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun(a)freescale.com> Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> -Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND - +Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD - Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf <agraf(a)suse.de> diff --git a/doc/README.t4240qds b/doc/README.t4240qds index a9841fb..ef8c75f 100644 --- a/doc/README.t4240qds +++ b/doc/README.t4240qds @@ -120,3 +120,56 @@ The override voltage takes effect when booting. Note: voltage adjustment needs to be done step by step. Changing voltage too rapidly may cause current surge. The voltage stepping is done by software. Users can set the final voltage directly. + +2-stage NAND/SD boot loader +------------------------------- +PBL initializes the internal SRAM and copy SPL(160K) in SRAM. +SPL further initialise DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T4QDS +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x140000 0x15FFFF u-boot env 128KB +0x160000 0x17FFFF FMAN Ucode 128KB + +Micro SD Card memory Map on T4QDS +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0128 FMAN ucode 64KB + +Switch Settings: (ON is 1, OFF is 0) +=============== +NAND boot SW setting: +SW1[1:8] = 10000010 +SW2[1.1] = 0 +SW6[1:4] = 1001 + +SD boot SW setting: +SW1[1:8] = 00100000 +SW2[1.1] = 0 diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 1b98cfd..e4eb30f 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -19,11 +19,64 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg +#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#else +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_NAND +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_NAND_BOOT +#endif + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + #endif +#endif /* CONFIG_RAMBOOT_PBL */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ @@ -64,12 +117,12 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -244,8 +297,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 @@ -261,6 +322,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK @@ -270,14 +339,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -379,14 +440,14 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index f8de439..36bc529 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -68,7 +68,16 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -96,7 +105,11 @@ #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R -- 1.8.0

1 0

[U-Boot] [PATCH] sandbox: ignore sandbox.dtb
by Masahiro Yamada 22 Apr '14

22 Apr '14

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Simon Glass <sjg(a)chromium.org> --- arch/sandbox/dts/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 arch/sandbox/dts/.gitignore diff --git a/arch/sandbox/dts/.gitignore b/arch/sandbox/dts/.gitignore new file mode 100644 index 0000000..b60ed20 --- /dev/null +++ b/arch/sandbox/dts/.gitignore @@ -0,0 +1 @@ +*.dtb -- 1.8.3.2

2 1

[U-Boot] [PATCH] ARM: tegra: fix CPU VDD comment in Tegra30 CPU init code
by Stephen Warren 21 Apr '14

21 Apr '14

From: Stephen Warren <swarren(a)nvidia.com> The register writes performed by arch/arm/cpu/arm720t/tegra30/cpu.c enable_cpu_power_rail() set the voltage to 1.0V not 1.4V as the comment implies. Fix the comment. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/cpu/arm720t/tegra30/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index a80648389c7c..85a945bc7918 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -60,7 +60,7 @@ static void enable_cpu_power_rail(void) /* * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. - * First set VDD to 1.4V, then enable the VDD regulator. + * First set VDD to 1.0V, then enable the VDD regulator. */ tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2); tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES); -- 1.8.1.5

1 0

[U-Boot] Please pull u-boot-ti/master
by Tom Rini 21 Apr '14

21 Apr '14

Hey, The following changes since commit 1b82491ee6ee1e986e5521b33692a00e1f38fe75: board:tricorder: fixup SPL OOB layout (2014-04-11 10:08:42 -0400) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to 2e8f5dc16ad360cc15ea402a1dc4d421a04adbbd: am43xx_evm: Drop SPI SPL (2014-04-17 17:40:15 -0400) ---------------------------------------------------------------- Karicheri, Muralidharan (6): tools: mkimage: add support for gpimage format NAND: DaVinci: allow forced disable of subpage writes i2c, davinci: move i2c_defs.h to the drivers/i2c directory spi: davinci: add support for multiple bus and chip select k2hk-evm: add configuration for spi1 and spi2 support keystone2: net: add keystone ethernet driver Manish Badarkhe (1): arm, da850: staticize funtions Nishanth Menon (11): OMAP: common: consolidate fake USB ethernet MAC address creation omap3/sys_info: provide interface to read die id OMAP3: beagle-xm: generate fake USB ethernet MAC address from dieid omap3: zoom1: enable CONFIG_SYS_GENERIC_BOARD OMAP3: zoom1: Configure GPMC for Ethernet OMAP3: zoom1: enable LAN9211 omap3: zoom1: enable common network commands omap3: zoom1: disable JFFS2 and enable FS_GENERIC omap3: zoom1: enable bootz omap3: zoom1: fix default console omap3: zoom1: switch to generic ti_omap3_common config header Poddar, Sourav (1): spi: ti_qspi: Add delay for successful bulk erase. Tom Rini (22): fw_env.c: Switch get_config to use '%ms' in sscanf env_mmc.c: Allow environment to be used within SPL env_mmc.c: Remove NULL check on tmp_env1/2 mtd: Add a CONFIG_SPL_MTD_SUPPORT for a more full NAND subsystem in SPL mtd: Build nand_util.o for CONFIG_ENV_IS_IN_NAND in SPL am335x_evm: Make SPL_OS also check the boot_os variable for falcon mode README: Add CONFIG_SPL_OS_BOOT to README README.falcon: Document environment variables for falcon mode a3m071: Make spl_start_uboot test like getenv_yesno does spl_mmc/CONFIG_SPL_OS_BOOT: Allow environment to determine what to boot TI: Add, use a DEFAULT_LINUX_BOOT_ENV environment string am335x_evm: Update the ramdisk args, we pass things in just fine via DT am43xx_evm: Update the ramdisk args, we pass things in just fine via DT TI:omap5: Move CONFIG_ENV_SIZE to board config files TI:armv7: Change Falcon Mode DT load address am335x_evm: Drop SPI SPL support from the default build SPL:SPI: Add Falcon Mode support dra7xx_evm: Add QSPI_4 support, qspiboot build target TI:armv7: Switch to CONFIG_SYS_BOARD_GENERIC TI:omap3: Convert omap3_beagle to ti_omap3_common.h am335x: Switch to CONFIG_SKIP_LOWLEVEL_INIT from guarding SPL or NOR_BOOT am43xx_evm: Drop SPI SPL Vitaly Andrianov (5): fdt: call ft_board_setup_ex() at the end of image_setup_libfdt() arm: add support for arch timer i2c, davinci: convert driver to new mutlibus/mutliadapter framework k2hk: add support for k2hk SOC and EVM keystone2: add keystone multicore navigator driver Wolfgang Denk (3): ARM: OMAP: remove sr32() from OMAP board code ARM: OMAP: hide custom bit manipulation function sr32() ARM: OMAP: replace custom sr32() by standard I/O accessors Makefile | 10 + README | 13 + arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 6 +- arch/arm/cpu/arm926ejs/davinci/dm355.c | 2 +- arch/arm/cpu/arm926ejs/davinci/dm365.c | 2 +- arch/arm/cpu/arm926ejs/davinci/dm644x.c | 2 +- arch/arm/cpu/arm926ejs/davinci/dm646x.c | 2 +- arch/arm/cpu/armv7/Makefile | 1 + arch/arm/cpu/armv7/am33xx/board.c | 4 +- arch/arm/cpu/armv7/am33xx/emif4.c | 2 +- arch/arm/cpu/armv7/arch_timer.c | 58 ++ arch/arm/cpu/armv7/keystone/Makefile | 17 + arch/arm/cpu/armv7/keystone/aemif.c | 71 ++ arch/arm/cpu/armv7/keystone/clock.c | 318 +++++++++ arch/arm/cpu/armv7/keystone/cmd_clock.c | 124 ++++ arch/arm/cpu/armv7/keystone/cmd_mon.c | 131 ++++ arch/arm/cpu/armv7/keystone/ddr3.c | 69 ++ arch/arm/cpu/armv7/keystone/init.c | 56 ++ arch/arm/cpu/armv7/keystone/keystone_nav.c | 376 ++++++++++ arch/arm/cpu/armv7/keystone/msmc.c | 68 ++ arch/arm/cpu/armv7/keystone/psc.c | 237 +++++++ arch/arm/cpu/armv7/keystone/spl.c | 45 ++ arch/arm/cpu/armv7/omap-common/boot-common.c | 11 + arch/arm/cpu/armv7/omap-common/utils.c | 21 + arch/arm/cpu/armv7/omap3/board.c | 4 +- arch/arm/cpu/armv7/omap3/clock.c | 355 ++++++---- arch/arm/cpu/armv7/omap3/sys_info.c | 19 +- arch/arm/cpu/armv7/syslib.c | 13 - arch/arm/include/asm/arch-davinci/da850_lowlevel.h | 3 - arch/arm/include/asm/arch-davinci/i2c_defs.h | 71 +- arch/arm/include/asm/arch-keystone/clock-k2hk.h | 109 +++ arch/arm/include/asm/arch-keystone/clock.h | 17 + arch/arm/include/asm/arch-keystone/clock_defs.h | 111 +++ arch/arm/include/asm/arch-keystone/emac_defs.h | 240 +++++++ arch/arm/include/asm/arch-keystone/emif_defs.h | 73 ++ arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 150 ++++ arch/arm/include/asm/arch-keystone/hardware.h | 175 +++++ arch/arm/include/asm/arch-keystone/i2c_defs.h | 17 + arch/arm/include/asm/arch-keystone/keystone_nav.h | 193 ++++++ arch/arm/include/asm/arch-keystone/nand_defs.h | 23 + arch/arm/include/asm/arch-keystone/psc_defs.h | 90 +++ arch/arm/include/asm/arch-keystone/spl.h | 12 + arch/arm/include/asm/arch-omap3/sys_proto.h | 3 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 1 - arch/arm/include/asm/arch-omap5/sys_proto.h | 1 - arch/arm/include/asm/omap_common.h | 2 + board/a3m071/a3m071.c | 3 +- board/logicpd/zoom1/config.mk | 1 - board/logicpd/zoom1/zoom1.c | 38 +- board/logicpd/zoom1/zoom1.h | 19 +- board/silica/pengwyn/Makefile | 2 +- board/ti/am335x/Makefile | 2 +- board/ti/am335x/board.c | 15 +- board/ti/beagle/beagle.c | 11 + board/ti/dra7xx/evm.c | 19 + board/ti/k2hk_evm/Makefile | 9 + board/ti/k2hk_evm/README | 122 ++++ board/ti/k2hk_evm/board.c | 301 ++++++++ board/ti/k2hk_evm/ddr3.c | 268 ++++++++ board/ti/omap5_uevm/evm.c | 25 +- board/ti/panda/panda.c | 23 +- boards.cfg | 4 +- common/env_mmc.c | 49 +- common/image-fdt.c | 5 + common/image.c | 1 + common/spl/spl_fat.c | 27 + doc/README.falcon | 13 + drivers/i2c/Makefile | 2 +- drivers/i2c/davinci_i2c.c | 402 ++++++----- drivers/i2c/davinci_i2c.h | 78 +++ drivers/mtd/nand/Makefile | 3 + drivers/mtd/nand/am335x_spl_bch.c | 54 +- drivers/mtd/nand/davinci_nand.c | 3 + drivers/mtd/spi/spi_spl_load.c | 46 +- drivers/net/Makefile | 1 + drivers/net/keystone_net.c | 716 ++++++++++++++++++++ drivers/serial/ns16550.c | 8 + drivers/spi/davinci_spi.c | 49 +- drivers/spi/davinci_spi.h | 33 + drivers/spi/ti_qspi.c | 3 + include/configs/am335x_evm.h | 25 +- include/configs/am43xx_evm.h | 17 +- include/configs/cam_enc_4xx.h | 8 +- include/configs/da830evm.h | 8 +- include/configs/da850evm.h | 8 +- include/configs/davinci_dm355evm.h | 8 +- include/configs/davinci_dm355leopard.h | 8 +- include/configs/davinci_dm365evm.h | 8 +- include/configs/davinci_dm6467evm.h | 8 +- include/configs/davinci_dvevm.h | 8 +- include/configs/davinci_schmoogie.h | 8 +- include/configs/davinci_sffsdr.h | 8 +- include/configs/davinci_sonata.h | 8 +- include/configs/dra7xx_evm.h | 38 +- include/configs/ea20.h | 7 +- include/configs/enbw_cmc.h | 8 +- include/configs/k2hk_evm.h | 256 +++++++ include/configs/omap3_beagle.h | 184 +---- include/configs/omap3_zoom1.h | 167 ++--- include/configs/omap5_uevm.h | 1 + include/configs/ti_am335x_common.h | 2 + include/configs/ti_armv7_common.h | 34 +- include/configs/ti_omap3_common.h | 4 + include/configs/ti_omap4_common.h | 6 +- include/configs/ti_omap5_common.h | 9 +- include/fdt_support.h | 7 + include/image.h | 1 + spl/Makefile | 1 + tools/Makefile | 2 + tools/env/fw_env.c | 13 +- tools/gpheader.h | 40 ++ tools/gpimage-common.c | 80 +++ tools/gpimage.c | 77 +++ tools/imagetool.c | 2 + tools/imagetool.h | 1 + tools/omapimage.c | 104 +-- tools/omapimage.h | 5 - 117 files changed, 5866 insertions(+), 996 deletions(-) create mode 100644 arch/arm/cpu/armv7/arch_timer.c create mode 100644 arch/arm/cpu/armv7/keystone/Makefile create mode 100644 arch/arm/cpu/armv7/keystone/aemif.c create mode 100644 arch/arm/cpu/armv7/keystone/clock.c create mode 100644 arch/arm/cpu/armv7/keystone/cmd_clock.c create mode 100644 arch/arm/cpu/armv7/keystone/cmd_mon.c create mode 100644 arch/arm/cpu/armv7/keystone/ddr3.c create mode 100644 arch/arm/cpu/armv7/keystone/init.c create mode 100644 arch/arm/cpu/armv7/keystone/keystone_nav.c create mode 100644 arch/arm/cpu/armv7/keystone/msmc.c create mode 100644 arch/arm/cpu/armv7/keystone/psc.c create mode 100644 arch/arm/cpu/armv7/keystone/spl.c create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2hk.h create mode 100644 arch/arm/include/asm/arch-keystone/clock.h create mode 100644 arch/arm/include/asm/arch-keystone/clock_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/emac_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/emif_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2hk.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware.h create mode 100644 arch/arm/include/asm/arch-keystone/i2c_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/keystone_nav.h create mode 100644 arch/arm/include/asm/arch-keystone/nand_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/psc_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/spl.h create mode 100644 board/ti/k2hk_evm/Makefile create mode 100644 board/ti/k2hk_evm/README create mode 100644 board/ti/k2hk_evm/board.c create mode 100644 board/ti/k2hk_evm/ddr3.c create mode 100644 drivers/i2c/davinci_i2c.h create mode 100644 drivers/net/keystone_net.c create mode 100644 include/configs/k2hk_evm.h create mode 100644 tools/gpheader.h create mode 100644 tools/gpimage-common.c create mode 100644 tools/gpimage.c Thanks! -- Tom

3 2

[U-Boot] pull request for u-boot-tegra/master into ARM/master
by Tom Warren 21 Apr '14

21 Apr '14

Albert, Please pull u-boot-tegra/master into ARM/master. Thanks! ./MAKEALL -s tegra AOK, checkpatch.pl is OK, and ./MAKEALL -a arm only shows failures that were already present in ARM/master. The following changes since commit 1b82491ee6ee1e986e5521b33692a00e1f38fe75: board:tricorder: fixup SPL OOB layout (2014-04-11 10:08:42 -0400) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to d381294aef4a5b6ddeda3685519330a5b73d884f: ARM: tegra: pack pinmux data tables tighter (2014-04-17 08:41:06 -0700) ---------------------------------------------------------------- Stefan Agner (3): usb: tegra: fix USB2 powerdown for Tegra30 and later usb: tegra: fix PHY configuration usb: tegra: combine header file Stephen Warren (14): ARM: tegra: pinctrl: remove func_safe ARM: tegra: pinctrl: remove vddio ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20 ARM: tegra: prototype pinmux_init() in board.h ARM: tegra: use apb_misc.h in more places ARM: tegra: pinctrl: remove duplication ARM: tegra: reduce public pinmux API ARM: tegra: pinmux naming consistency fixes ARM: tegra: Tegra20 pinmux cleanup ARM: tegra: Tegra30 pinmux cleanup ARM: tegra: Tegra114 pinmux cleanup ARM: tegra: Tegra124 pinmux cleanup ARM: tegra: add Jetson TK1 board ARM: tegra: pack pinmux data tables tighter arch/arm/cpu/arm720t/tegra-common/spl.c | 6 +- arch/arm/cpu/arm720t/tegra114/cpu.c | 4 +- arch/arm/cpu/arm720t/tegra124/cpu.c | 4 +- arch/arm/cpu/tegra-common/Makefile | 6 +- arch/arm/cpu/tegra-common/pinmux-common.c | 508 +++++++++++ arch/arm/cpu/tegra114-common/funcmux.c | 32 +- arch/arm/cpu/tegra114-common/pinmux.c | 895 +++++-------------- arch/arm/cpu/tegra124-common/funcmux.c | 38 +- arch/arm/cpu/tegra124-common/pinmux.c | 898 +++++-------------- arch/arm/cpu/tegra20-common/emc.c | 2 +- arch/arm/cpu/tegra20-common/funcmux.c | 185 ++-- arch/arm/cpu/tegra20-common/pinmux.c | 416 +++------ arch/arm/cpu/tegra20-common/warmboot.c | 8 +- arch/arm/cpu/tegra20-common/warmboot_avp.c | 6 +- arch/arm/cpu/tegra30-common/funcmux.c | 20 +- arch/arm/cpu/tegra30-common/pinmux.c | 948 ++++++-------------- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra124-jetson-tk1.dts | 84 ++ .../asm/{arch-tegra20 => arch-tegra}/apb_misc.h | 2 + arch/arm/include/asm/arch-tegra/board.h | 1 + arch/arm/include/asm/arch-tegra/pinmux.h | 185 ++++ arch/arm/include/asm/arch-tegra/usb.h | 223 ++++- arch/arm/include/asm/arch-tegra114/pinmux.h | 836 ++++++------------ arch/arm/include/asm/arch-tegra114/usb.h | 156 ---- arch/arm/include/asm/arch-tegra124/pinmux.h | 866 +++++++----------- arch/arm/include/asm/arch-tegra124/usb.h | 268 ------ arch/arm/include/asm/arch-tegra20/pinmux.h | 372 +++----- arch/arm/include/asm/arch-tegra20/usb.h | 155 ---- arch/arm/include/asm/arch-tegra30/pinmux.h | 963 ++++++++------------- arch/arm/include/asm/arch-tegra30/usb.h | 168 ---- .../common/pinmux-config-tamonten-ng.h | 492 +++++------ board/avionic-design/common/tamonten-ng.c | 12 +- board/avionic-design/common/tamonten.c | 4 +- board/compal/paz00/paz00.c | 22 +- board/compulab/trimslice/trimslice.c | 4 +- board/nvidia/cardhu/cardhu.c | 6 +- board/nvidia/cardhu/pinmux-config-cardhu.h | 498 +++++------ board/nvidia/common/board.c | 9 +- board/nvidia/dalmore/dalmore.c | 9 +- board/nvidia/dalmore/pinmux-config-dalmore.h | 388 ++++----- board/nvidia/harmony/harmony.c | 18 +- board/nvidia/jetson-tk1/Makefile | 9 + board/nvidia/jetson-tk1/jetson-tk1.c | 23 + board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 227 +++++ board/nvidia/seaboard/seaboard.c | 6 +- board/nvidia/venice2/as3722_init.h | 4 + board/nvidia/venice2/pinmux-config-venice2.h | 360 ++++---- board/nvidia/venice2/venice2.c | 15 +- .../colibri_t20-common/colibri_t20-common.c | 8 +- board/toradex/colibri_t20_iris/colibri_t20_iris.c | 4 +- boards.cfg | 1 + drivers/spi/tegra20_sflash.c | 6 +- drivers/usb/host/ehci-tegra.c | 28 +- drivers/video/tegra.c | 4 +- include/configs/jetson-tk1.h | 79 ++ 55 files changed, 4384 insertions(+), 6108 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/pinmux-common.c create mode 100644 arch/arm/dts/tegra124-jetson-tk1.dts rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/apb_misc.h (87%) create mode 100644 arch/arm/include/asm/arch-tegra/pinmux.h delete mode 100644 arch/arm/include/asm/arch-tegra114/usb.h delete mode 100644 arch/arm/include/asm/arch-tegra124/usb.h delete mode 100644 arch/arm/include/asm/arch-tegra20/usb.h delete mode 100644 arch/arm/include/asm/arch-tegra30/usb.h create mode 100644 board/nvidia/jetson-tk1/Makefile create mode 100644 board/nvidia/jetson-tk1/jetson-tk1.c create mode 100644 board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h create mode 100644 include/configs/jetson-tk1.h

2 1

Re: [U-Boot] config: enable CONFIG_API in distro config
by Simon Glass 21 Apr '14

21 Apr '14

Hi Dennis, On 19 April 2014 08:42, Dennis Gilmore <dennis(a)ausil.us> wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > On Sat, 19 Apr 2014 15:01:40 +0100 > Ian Campbell <ijc(a)hellion.org.uk> wrote: > > > On Fri, 2014-04-18 at 11:43 -0600, Simon Glass wrote: > > > Hi Stephen, > > > > > > On 18 April 2014 11:23, Stephen Warren <swarren(a)wwwdotorg.org> > > > wrote: > > > > On 04/18/2014 09:35 AM, Tom Rini wrote: > > > >> On Thu, Apr 10, 2014 at 03:55:48PM -0500, Rob Herring wrote: > > > >> > > > >>> From: Rob Herring <robh(a)kernel.org> > > > >>> > > > >>> CONFIG_API is needed for u-boot apps such as grub2, so enable > > > >>> it for distro config. > > > >>> > > > >>> Cc: Dennis Gilmore <dennis(a)ausil.us> > > > >>> Signed-off-by: Rob Herring <robh(a)kernel.org> > > > >> > > > >> This breaks a number of boards that have opted in to the distro > > > >> config. The full list is: > > > >> whistler trimslice beaver tec paz00 ventana cardhu harmony > > > >> dalmore plutux medcom-wide rpi_b venice2 colibri_t20_iris tec-ng > > > >> seaboard > > > >> > > > >> How do you guys want to handle this? I can apply now and they > > > >> can be fixed up later, or I can wait for fixup patches to come > > > >> out and apply them all at once. Thanks! > > > > > > > > I've sent patches that solve all the build problems on Tegra with > > > > CONFIG_API enabled. > > > > > > > > That said, I still conceptually object to config_distro_defaults.h > > > > enabling API support in order to support grub; I believe the > > > > distros need to get together and nail down a *single* boot > > > > mechanism to standardize upon, rather than having Fedora support > > > > BootloaderSpec, Ubuntu/Linaro(?) support Grub, something else > > > > support LILO, something else support UEFI, > > > > AIUI the distros *are* standardising: on grub2. > > not in arm space at least, > I have no great love for grub2 and the pain of not using on ARM devices would in my case succumb to an extremely small aspirin. > > AIUI BootloaderSpec is a spec to standardise the configuration of > > UEFI. It is used to install the distro's bootloader (often grub2) > > into the UEFI boot list, for grub-on-UEFI scenarios. > > not at all true, bootloader spec is designed to be a platform and > bootloader agnostic way to boot open systems. its designed to > share /boot between open operating systems, UEFI, bios, u-boot etc have > zero to do with it. you can compliantly boot operating systems using > any type of platform > > > Where the lowlevel firmware is u-boot then they want to use grub2 on > > it so that things are consistently grub no matter whether the > > platform uses UEFI, u-boot, PC BIOS etc. > > > > > etc. Without this, we'll force every U-Boot binary to > > > > be bloated with all kinds of redundant code. Having a single > > > > standard mechanism was always the point of > > > > config_distro_defaults.h in my mind. If we really need Grub > > > > support, wouldn't it be better to have U-Boot parse and execute > > > > grub.cfg, just like it does extlinux.cfg? > > > > > > That seems to make a lot more sense to me. How hard can it possibly > > > be? > > > > Very. grub.cfg is essentially a complete bash-a-like programming > > language. At work we try to parse it for Xen's "pygrub" utility and it > > breaks pretty frequently when people introduce random new variables > > etc. > > Which is why we are standardising distro booting using u-boots syslinux > compatibility in distro land. it's not uncommon to users, since isos > have used isolinux for years. right now its feature set is somewhat > simple. but over time we should be able to do things like commandline > editing and using menu to select different kernels. But there is a > very solid foundation available today that works really well. > Can you suggest a starting point for trying this out on am ARM platform? (e.g. OMAP, Tegra, Exynos) I'd like to see how it works. > > AFAIK no one is really working on grub2 for use with u-boot as linaro > who was doing the work have decided to drop u-boot support and only do > UEFI. > So UEFI boots through grub2? We seem to have a talent for making things complicated? Regards, Simon

3 3

[U-Boot] patchwork down again?
by York Sun 21 Apr '14

21 Apr '14

Does anyone have a problem accessing patchwork? York

1 0