April 2014 - U-Boot

[U-Boot] [PATCH] imx6: ventana: fix system-serial dt property
by Tim Harvey 09 May '14

09 May '14

Fix typo in setting of system-serial property causing the prop len to be off by 1. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/gw_ventana/gw_ventana.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index f38a777..79b3e01 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1278,7 +1278,7 @@ void ft_board_setup(void *blob, bd_t *bd) /* board serial number */ fdt_setprop(blob, 0, "system-serial", getenv("serial#"), - strlen(getenv("serial#") + 1)); + strlen(getenv("serial#")) + 1); /* board (model contains model from device-tree) */ fdt_setprop(blob, 0, "board", info->model, -- 1.8.3.2

2 1

[U-Boot] [PATCH] imx: ventana: add HDMI and LVDS display capability
by Tim Harvey 09 May '14

09 May '14

Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/gw_ventana/gw_ventana.c | 134 ++++++++++++++++++++++++++++++++ include/configs/gw_ventana.h | 16 ++++ 2 files changed, 150 insertions(+) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 79b3e01..f5b9f90 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -12,6 +12,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> +#include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> @@ -19,6 +20,7 @@ #include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/sata.h> +#include <asm/imx-common/video.h> #include <jffs2/load_kernel.h> #include <hwconfig.h> #include <i2c.h> @@ -369,6 +371,135 @@ int board_eth_init(bd_t *bis) return 0; } +#if defined(CONFIG_VIDEO_IPUV3) + +static void enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return ((0 == i2c_set_bus_num(dev->bus)) + && + (0 == i2c_probe(dev->addr))); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + + /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + + /* Enable Backlight */ + imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 18), 1); +} + +struct display_info_t const displays[] = {{ + /* HDMI Output */ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */ + .bus = 2, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + + /* Backlight CABEN on LVDS connector */ + imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 10), 0); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + /* read ventana EEPROM, check for validity, and return baseboard type */ static int read_eeprom(void) @@ -942,6 +1073,9 @@ int board_early_init_f(void) setup_iomux_uart(); gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 335f2ff..cd55495 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -194,6 +194,22 @@ #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP #define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200 +/* Framebuffer and LCD */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP + /* serial console (ttymxc1,115200) */ #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 -- 1.8.3.2

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[U-Boot] [PATCH 0/4] imx25: Add hardware support
by dietho＠gmx.de 09 May '14

09 May '14

From: Thomas Diener <dietho(a)gmx.de> This patchset adds support for the imx25 lcd controller and support for variants of cpu and base boards with drivers. Thomas Diener (4): imx25: Add new hardware registers video: Add support for imx25 lcd controller zmx25: Add extended support for the cpu board and belonging base boards Update of the company logo arch/arm/include/asm/arch-mx25/imx-regs.h | 175 ++++++ arch/arm/include/asm/arch-mx25/iomux-mx25.h | 25 +- arch/arm/include/asm/imx-common/iomux-v3.h | 13 +- arch/arm/lib/asm-offsets.c | 9 + board/syteco/zmx25/Makefile | 2 +- board/syteco/zmx25/fma1125.c | 193 ++++++ board/syteco/zmx25/fma1125.h | 19 + board/syteco/zmx25/lowlevel_init.S | 20 + board/syteco/zmx25/mpr121.c | 204 ++++++ board/syteco/zmx25/mpr121.h | 20 + board/syteco/zmx25/polytouch.c | 123 ++++ board/syteco/zmx25/polytouch.h | 19 + board/syteco/zmx25/zmx25.c | 897 +++++++++++++++++++++++++-- drivers/video/Makefile | 1 + drivers/video/imx25lcdc.c | 123 ++++ include/configs/zmx25.h | 47 +- tools/logos/syteco.bmp | Bin 11414 -> 11414 bytes 17 files changed, 1830 insertions(+), 60 deletions(-) create mode 100644 board/syteco/zmx25/fma1125.c create mode 100644 board/syteco/zmx25/fma1125.h create mode 100644 board/syteco/zmx25/mpr121.c create mode 100644 board/syteco/zmx25/mpr121.h create mode 100644 board/syteco/zmx25/polytouch.c create mode 100644 board/syteco/zmx25/polytouch.h create mode 100644 drivers/video/imx25lcdc.c -- 1.7.9.5

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[U-Boot] [PATCH v2] iomux-v3: Add support for mx6sl LVE bit
by Fabio Estevam 09 May '14

09 May '14

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad. LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - Use bit 1, which is unused. arch/arm/imx-common/iomux-v3.c | 8 ++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index b59b802..6e46ea8 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; +#if defined CONFIG_MX6SL + /* Check whether LVE bit needs to be set */ + if (pad_ctrl & PAD_CTL_LVE) { + pad_ctrl &= ~PAD_CTL_LVE; + pad_ctrl |= PAD_CTL_LVE_BIT; + } +#endif + if (mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1..cca920b 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 << 3) #define PAD_CTL_DSE_34ohm (7 << 3) +#if defined CONFIG_MX6SL +#define PAD_CTL_LVE (1 << 1) +#define PAD_CTL_LVE_BIT (1 << 22) +#endif + #elif defined(CONFIG_VF610) #define PAD_MUX_MODE_SHIFT 20 -- 1.8.3.2

3 2

[U-Boot] [PATCH 0/4] ventana: Add LTC3676 PMIC support
by Tim Harvey 09 May '14

09 May '14

The Gateworks Ventana boards share much in common, but there are two differing PMIC's used on them. This patch series adds a new PMIC driver for the LTC3676 and supports them both within the common board support file. Signed-off-By: Tim Harvey <tharvey(a)gateworks.com> Tim Harvey (4): power: make pfuze100 be able to coexist with other pmics ventana: use non-generic pfuze100 init power: Add support for LTC3676 PMIC ventana: Add support for the LTC3676 PMIC board/gateworks/gw_ventana/gw_ventana.c | 78 ++++++++++++++++++++++++--------- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_ltc3676.c | 32 ++++++++++++++ drivers/power/pmic/pmic_pfuze100.c | 2 +- include/configs/gw_ventana.h | 2 + include/power/ltc3676_pmic.h | 51 +++++++++++++++++++++ include/power/pfuze100_pmic.h | 1 + 7 files changed, 145 insertions(+), 22 deletions(-) create mode 100644 drivers/power/pmic/pmic_ltc3676.c create mode 100644 include/power/ltc3676_pmic.h -- 1.8.3.2

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[U-Boot] [PATCH] sh: delete an unused source file
by Masahiro Yamada 08 May '14

08 May '14

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- arch/sh/cpu/sh2/cache.c | 96 ------------------------------------------------- 1 file changed, 96 deletions(-) delete mode 100644 arch/sh/cpu/sh2/cache.c diff --git a/arch/sh/cpu/sh2/cache.c b/arch/sh/cpu/sh2/cache.c deleted file mode 100644 index 8093e98..0000000 --- a/arch/sh/cpu/sh2/cache.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> - * - * Copyright (C) 2007, 2008 Nobobuhiro Iwamatsu <iwamatsu(a)nigauri.org> - * Copyright (C) 2008 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> - -/* - * Jump to P2 area. - * When handling TLB or caches, we need to do it from P2 area. - */ -#define jump_to_P2() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ -} while (0) - -/* - * Back to P1 area. - */ -#define back_to_P1() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ -} while (0) - -#define CACHE_VALID 1 -#define CACHE_UPDATED 2 - -static inline void cache_wback_all(void) -{ - unsigned long addr, data, i, j; - - jump_to_P2(); - for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { - for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { - addr = CACHE_OC_ADDRESS_ARRAY - | (j << CACHE_OC_WAY_SHIFT) - | (i << CACHE_OC_ENTRY_SHIFT); - data = inl(addr); - if (data & CACHE_UPDATED) { - data &= ~CACHE_UPDATED; - outl(data, addr); - } - } - } - back_to_P1(); -} - - -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 - -int cache_control(unsigned int cmd) -{ - unsigned long ccr; - - jump_to_P2(); - ccr = inl(CCR); - - if (ccr & CCR_CACHE_ENABLE) - cache_wback_all(); - - if (cmd == CACHE_DISABLE) - outl(CCR_CACHE_STOP, CCR); - else - outl(CCR_CACHE_INIT, CCR); - back_to_P1(); - - return 0; -} -- 1.8.3.2

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[U-Boot] [PATCH 1/2] musb-new, dfu: first send request answer then call completions
by Heiko Schocher 08 May '14

08 May '14

comment in ep0_txstate() states: "report completions as soon as the fifo's loaded; there's no win in waiting till this last packet gets acked". This is wrong for using dfu. In the dfu usecase we must send a PollTimeout to the host, so the host can wait until the U-Boot Code is ready for answering new usb requests. So the answer which contains the PollTimeout must send *before* U-Boot calls req->complete. The req->complete is used in the dfu case for flushing the medium, when entering DFU_STATE_dfuMANIFEST_SYNC state. Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Kyungmin Park <kyungmin.park(a)samsung.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> --- Tested on the dxr2 and pxm2 boards. If dfu_flush() needs longer then 5 sec, dfu-util breaks with current mainline code: [...] finished! unable to read DFU status $ With this patch, it shows again: [...] finished! state(7) = dfuMANIFEST, status(0) = No error condition is present state(2) = dfuIDLE, status(0) = No error condition is present Done! $ --- drivers/usb/musb-new/musb_gadget_ep0.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c index 6599d38..8c3b0a1 100644 --- a/drivers/usb/musb-new/musb_gadget_ep0.c +++ b/drivers/usb/musb-new/musb_gadget_ep0.c @@ -576,6 +576,10 @@ static void ep0_txstate(struct musb *musb) } else request = NULL; + /* send it out, triggering a "txpktrdy cleared" irq */ + musb_ep_select(musb->mregs, 0); + musb_writew(regs, MUSB_CSR0, csr); + /* report completions as soon as the fifo's loaded; there's no * win in waiting till this last packet gets acked. (other than * very precise fault reporting, needed by USB TMC; possible with @@ -588,10 +592,6 @@ static void ep0_txstate(struct musb *musb) return; musb->ackpend = 0; } - - /* send it out, triggering a "txpktrdy cleared" irq */ - musb_ep_select(musb->mregs, 0); - musb_writew(regs, MUSB_CSR0, csr); } /* -- 1.8.3.1

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[U-Boot] [PATCH v2] dfu, nand: add medium specific polltimeout function
by Heiko Schocher 08 May '14

08 May '14

add a possibility to add a medium specific polltimeout function. So it is possible to define different poll timeouts. Used on nand medium, for setting the DFU_MANIFEST_POLL_TIMEOUT only on nand ubi partitions, which is currently the only usecase. Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Kyungmin Park <kyungmin.park(a)samsung.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> --- - changes for v2: - add comment from Pantelis Antoniou - add simple accessor for getting the poll timeout dfu_get_manifest_timeout() drivers/dfu/dfu_nand.c | 13 +++++++++++++ drivers/usb/gadget/f_dfu.c | 10 +++++++++- include/dfu.h | 1 + 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index 2d07097..ccdbef6 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -163,6 +163,18 @@ static int dfu_flush_medium_nand(struct dfu_entity *dfu) return ret; } +unsigned int dfu_polltimeout_nand(struct dfu_entity *dfu) +{ + /* + * Currently, Poll Timeout != 0 is only needed on nand + * ubi partition, as the not used sectors need an erase + */ + if (dfu->data.nand.ubi) + return DFU_MANIFEST_POLL_TIMEOUT; + + return DFU_DEFAULT_POLL_TIMEOUT; +} + int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) { char *st; @@ -211,6 +223,7 @@ int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) dfu->read_medium = dfu_read_medium_nand; dfu->write_medium = dfu_write_medium_nand; dfu->flush_medium = dfu_flush_medium_nand; + dfu->poll_timeout = dfu_polltimeout_nand; /* initial state */ dfu->inited = 0; diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index de75ff1..e32b742 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -174,10 +174,17 @@ static void dnload_request_flush(struct usb_ep *ep, struct usb_request *req) req->length, f_dfu->blk_seq_num); } +static inline int dfu_get_manifest_timeout(struct dfu_entity *dfu) +{ + return dfu->poll_timeout ? dfu->poll_timeout(dfu) : + DFU_MANIFEST_POLL_TIMEOUT; +} + static void handle_getstatus(struct usb_request *req) { struct dfu_status *dstat = (struct dfu_status *)req->buf; struct f_dfu *f_dfu = req->context; + struct dfu_entity *dfu = dfu_get_entity(f_dfu->altsetting); dfu_set_poll_timeout(dstat, 0); @@ -190,7 +197,8 @@ static void handle_getstatus(struct usb_request *req) f_dfu->dfu_state = DFU_STATE_dfuMANIFEST; break; case DFU_STATE_dfuMANIFEST: - dfu_set_poll_timeout(dstat, DFU_MANIFEST_POLL_TIMEOUT); + dfu_set_poll_timeout(dstat, dfu_get_manifest_timeout(dfu)); + break; default: break; } diff --git a/include/dfu.h b/include/dfu.h index 6c71ecb..c7fd270 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -105,6 +105,7 @@ struct dfu_entity { u64 offset, void *buf, long *len); int (*flush_medium)(struct dfu_entity *dfu); + unsigned int (*poll_timeout)(struct dfu_entity *dfu); struct list_head list; -- 1.8.3.1

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[U-Boot] [PATCH 0/3] samsung: misc: add new lcd menu options
by Przemyslaw Marczak 08 May '14

08 May '14

Changes: - small code refactor - add menu option: gpt restore - add menu option: env default Inha Song (1): samsung: misc: add env default option to lcd menu Przemyslaw Marczak (2): samsung: misc: check_keys(), key_pressed() - remove type static. samsung: misc: add gpt restore option to lcd menu board/samsung/common/misc.c | 60 +++++++++++++++++++++---------------------- include/samsung/misc.h | 6 +++++ 2 files changed, 36 insertions(+), 30 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH] ARM: tegra: use a CPU freq that all SKUs can support
by Stephen Warren 07 May '14

07 May '14

From: Stephen Warren <swarren(a)nvidia.com> U-Boot on Tegra30 currently selects a main CPU frequency that cannot be supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values on some others. This can result in unreliable operation of the main CPUs. Resolve this by switching to a CPU frequency that can be supported by any SKU. According to the following link, the maximum supported CPU frequency of the slowest Tegra30 SKU is 600MHz: repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary branch l4t/l4t-r16-r2 path arch/arm/mach-tegra/tegra3_dvfs.c table cpu_dvfs_table[] According to that same table, the minimum VDD_CPU required to operate at that frequency across all SKUs is 1.007V. Given the adjustment resolution of the TPS65911 PMIC that's used on all Tegra30-based boards we support, we'll end up using 1.0125V instead. At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates that VDD_CORE must be at least 1.2V on all SKUs. According to tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree), that voltage is safe for all SKUs. An alternative would be to port much of the code from tegra3_dvfs.c and tegra3_speedo.c in the kernel tree mentioned above. That's more work than I want to take on right now. While all the currently supported boards use the same regulator chip for VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we add some small conditional code to select how VDD_CORE is programmed. If this becomes more complex in the future as new boards are added, or we end up adding code to detect the SoC SKU and dynamically determine the allowed frequency and required voltages, we should probably make this a runtime call into a function provided by the board file and/or relevant PMIC driver. Cc: Alban Bedel <alban.bedel(a)avionic-design.de> Cc: Marcel Ziswiler <marcel(a)ziswiler.com> Cc: Bard Liao <bardliao(a)realtek.com> Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- Alban, I don't know which regulator is used for VDD_CORE on Tec-NG. If could you find this out, I can adjust tec-ng.h too. Thanks. --- arch/arm/cpu/arm720t/tegra-common/cpu.c | 10 +++++----- arch/arm/cpu/arm720t/tegra30/cpu.c | 23 +++++++++++++++++++++-- include/configs/beaver.h | 3 +++ include/configs/cardhu.h | 3 +++ 4 files changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 168f525ec7c8..c6f3b029a16e 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -82,7 +82,7 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, /* - * T30: 1.4 GHz + * T30: 600 MHz * * Register Field Bits Width * ------------------------------ @@ -92,10 +92,10 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { * PLLX_MISC cpcon 11: 8 4 */ { - { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ - { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */ - { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ - { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ }, /* * T114: 700 MHz diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index 85a945bc7918..0f52e54239e1 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config) writel(config, &reg->cnfg); } +#define TPS62366A_I2C_ADDR 0x60 +#define TPS62366A_SET1_REG 0x01 +#define TPS62366A_SET1_DATA (0x46 | TPS62366A_SET1_REG) + +#define TPS62361B_I2C_ADDR 0x60 +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x46 | TPS62361B_SET3_REG) + #define TPS65911_I2C_ADDR 0x5A #define TPS65911_VDDCTRL_OP_REG 0x28 #define TPS65911_VDDCTRL_SR_REG 0x27 -#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) #define I2C_SEND_2_BYTES 0x0A02 @@ -58,9 +66,20 @@ static void enable_cpu_power_rail(void) reg |= CPUPWRREQ_OE; writel(reg, &pmc->pmc_cntrl); + /* Set VDD_CORE to 1.200V. */ +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 + tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES); +#endif +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 + tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2); + tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES); +#endif + udelay(1000); + /* * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. - * First set VDD to 1.0V, then enable the VDD regulator. + * First set VDD to 1.0125V, then enable the VDD regulator. */ tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2); tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES); diff --git a/include/configs/beaver.h b/include/configs/beaver.h index df9a98bca6e2..9ff089e67c36 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -21,6 +21,9 @@ #include "tegra30-common.h" +/* VDD core PMIC */ +#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 + /* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */ #define CONFIG_DEFAULT_DEVICE_TREE tegra30-beaver #define CONFIG_OF_CONTROL diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index e15b52737b24..59f429cf5784 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -21,6 +21,9 @@ #include "tegra30-common.h" +/* VDD core PMIC */ +#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 + /* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */ #define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu #define CONFIG_OF_CONTROL -- 1.8.1.5

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