December 2014 - U-Boot

[U-Boot] Please pull u-boot-fdt.git (take 2)
by Simon Glass 02 Dec '14

02 Dec '14

Hi Tom, I just pulled this down from patchwork again, adding two more Tested-by: credits. The following changes since commit 85bafb6da4dddfffa78479aa49a72ae48578a4ce: Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq (2014-11-26 11:23:26 -0500) are available in the git repository at: git://git.denx.de/u-boot-fdt.git for you to fetch changes up to ffccb84c1a8e276fa7263ec4ca8186f06312305c: fdt: Fix regression in fdt_pack_reg() (2014-12-01 08:23:32 -0700) ---------------------------------------------------------------- Hans de Goede (1): fdt: Fix regression in fdt_pack_reg() Masahiro Yamada (1): fdt: remove fdtdec_get_alias_node() function common/fdt_support.c | 12 ++++++------ drivers/serial/serial-uclass.c | 2 +- include/fdtdec.h | 11 ----------- lib/fdtdec.c | 15 --------------- 4 files changed, 7 insertions(+), 33 deletions(-) Regards, Simon

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[U-Boot] Please pull u-boot-x86.git
by Simon Glass 02 Dec '14

02 Dec '14

Hi Tom, This is the last of the bare x86 support for this release. I also brought in some interrupt fixes from Bin. The following changes since commit 2a82ec77d27ef5f860a107c4b764643a655dceeb: Prepare v2015.01-rc2 (2014-11-24 17:08:47 -0500) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to 908ec6e4d1d12f746cb9b7cc73430a268ceb2c92: tools: Add ifdtool to .gitignore (2014-11-25 07:11:17 -0700) ---------------------------------------------------------------- Bin Meng (5): x86: Call cpu_init_interrupts() from interrupt_init() x86: Remove cpu_init_r() for x86 x86: Refactor interrupt_init() x86: Remove unnecessary call to initr_enable_interrupts() tools: Add ifdtool to .gitignore Simon Glass (51): x86: Add ivybridge directory to Makefile Fix SIZE_MAX compiler warning when using stdint.h Align embedded device tree correctly pci: Update pci_ids.h to include some missing IDs x86: Remove board_early_init_r() x86: Panic if there is no relocation data x86: Ensure that all relocation data is included in the image x86: Factor out common values in the link script rtc: mc146818: Set up RTC at start of day x86: Add ioapic.h header x86: pci: Add handlers before and after a PCI hose scan x86: config: Enable plug-and-play for link PCI pci: Add functions to read and write a BAR address x86: Set up edge triggering on interrupt 9 x86: ivybridge: Add support for BD82x6x PCH x86: Add a simple header file for ACPI x86: ivybridge: Add PCH init x86: ivybridge: Add additional LPC init x86: dts: Move PCI peripherals into a pci node x86: dts: Add LPC settings for link x86: ivybridge: Add SATA init x86: dts: Add SATA settings for link x86: ivybridge: Set up EHCI USB x86: config: Enable USB on link x86: ivybridge: Set up XHCI USB x86: Add Intel speedstep and turbo mode code x86: Drop old CONFIG_INTEL_CORE_ARCH code x86: Add LAPIC setup code x86: Add init for model 206AX CPU x86: Drop some msr functions that we don't support x86: ivybridge: Add northbridge init functions x86: config: Enable SPI for chromebook_link x86: Add a definition of asmlinkage Introduce a header file for the BIOS emulator x86: Add GDT descriptors for option ROMs x86: Add vesa mode configuration options Add support for Vesa BIOS extensions x86: Add support for running option ROMs natively pci: Add general support for execution of video ROMs x86: video: Add video driver for bare x86 boards x86: Allow an option ROM to be built into U-Boot x86: Add initial video device init for Intel GMA x86: dts: Add video information to the device tree x86: config: Enable video support for chromebook_link bios_emulator: Allow x86 to use the emulator bios_emulator: Add vesa support and allow ROMs to be passed in as data bios_emulator: Allow a custom interrupt handler to be installed bios_emulator: Add an option to enable debugging bios_emulator: Always print errors when opcode decode fails x86: chromebook_link: Enable the x86 emulator x86: chromebook_link: Enable the Chrome OS EC Makefile | 3 + arch/x86/Kconfig | 149 +++++++++++++++ arch/x86/cpu/Makefile | 4 + arch/x86/cpu/config.mk | 5 +- arch/x86/cpu/coreboot/coreboot.c | 11 -- arch/x86/cpu/cpu.c | 17 +- arch/x86/cpu/interrupts.c | 54 ++---- arch/x86/cpu/ivybridge/Makefile | 8 + arch/x86/cpu/ivybridge/bd82x6x.c | 146 +++++++++++++++ arch/x86/cpu/ivybridge/gma.c | 756 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/gma.h | 156 ++++++++++++++++ arch/x86/cpu/ivybridge/lpc.c | 523 ++++++++++++++++++++++++++++++++++++++++++++++++++- arch/x86/cpu/ivybridge/model_206ax.c | 514 ++++++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/ivybridge/northbridge.c | 188 +++++++++++++++++++ arch/x86/cpu/ivybridge/pch.c | 123 ++++++++++++ arch/x86/cpu/ivybridge/pci.c | 40 ++++ arch/x86/cpu/ivybridge/sata.c | 225 ++++++++++++++++++++++ arch/x86/cpu/ivybridge/usb_ehci.c | 29 +++ arch/x86/cpu/ivybridge/usb_xhci.c | 32 ++++ arch/x86/cpu/lapic.c | 57 ++++++ arch/x86/cpu/pci.c | 12 ++ arch/x86/cpu/turbo.c | 98 ++++++++++ arch/x86/cpu/u-boot.lds | 18 +- arch/x86/dts/link.dts | 54 ++++-- arch/x86/include/asm/acpi.h | 24 +++ arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 23 +++ arch/x86/include/asm/arch-ivybridge/model_206ax.h | 4 + arch/x86/include/asm/arch-ivybridge/pch.h | 120 ++++++++++++ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 13 +- arch/x86/include/asm/i8259.h | 2 + arch/x86/include/asm/interrupt.h | 11 ++ arch/x86/include/asm/ioapic.h | 38 ++++ arch/x86/include/asm/lapic.h | 124 +++++++++++- arch/x86/include/asm/msr-index.h | 2 + arch/x86/include/asm/msr.h | 11 -- arch/x86/include/asm/pci.h | 3 + arch/x86/include/asm/post.h | 1 + arch/x86/include/asm/processor.h | 31 ++- arch/x86/include/asm/speedstep.h | 89 +++++++++ arch/x86/include/asm/turbo.h | 31 +++ arch/x86/include/asm/u-boot-x86.h | 2 - arch/x86/lib/Makefile | 3 + arch/x86/lib/bios.c | 347 ++++++++++++++++++++++++++++++++++ arch/x86/lib/bios.h | 98 ++++++++++ arch/x86/lib/bios_asm.S | 281 ++++++++++++++++++++++++++++ arch/x86/lib/bios_interrupts.c | 217 +++++++++++++++++++++ arch/x86/lib/pcat_interrupts.c | 42 ++++- arch/x86/lib/relocate.c | 3 + board/google/chromebook_link/link.c | 7 +- common/board_r.c | 7 +- doc/device-tree-bindings/ata/intel-sata.txt | 26 +++ doc/device-tree-bindings/misc/intel-lpc.txt | 47 ++++- doc/device-tree-bindings/video/intel-gma.txt | 40 ++++ drivers/bios_emulator/Makefile | 2 +- drivers/bios_emulator/atibios.c | 198 ++++++++++++++------ drivers/bios_emulator/besys.c | 100 +++++++--- drivers/bios_emulator/bios.c | 4 +- drivers/bios_emulator/biosemui.h | 2 +- drivers/bios_emulator/include/biosemu.h | 53 +----- drivers/bios_emulator/include/x86emu.h | 7 +- drivers/bios_emulator/include/x86emu/debug.h | 20 +- drivers/bios_emulator/include/x86emu/regs.h | 2 +- drivers/bios_emulator/x86emu/debug.c | 10 +- drivers/bios_emulator/x86emu/decode.c | 24 +-- drivers/bios_emulator/x86emu/ops.c | 58 +++--- drivers/bios_emulator/x86emu/ops2.c | 4 +- drivers/bios_emulator/x86emu/sys.c | 5 + drivers/pci/Makefile | 2 +- drivers/pci/pci.c | 24 ++- drivers/pci/pci_rom.c | 278 +++++++++++++++++++++++++++ drivers/rtc/bfin_rtc.c | 2 +- drivers/rtc/mc146818.c | 43 ++++- drivers/video/Makefile | 1 + drivers/video/ati_radeon_fb.c | 2 +- drivers/video/x86_fb.c | 37 ++++ include/bios_emul.h | 66 +++++++ include/common.h | 3 + include/configs/chromebook_link.h | 30 +-- include/fdtdec.h | 3 + include/linux/kernel.h | 2 + include/pci.h | 23 +++ include/pci_ids.h | 187 ++++++++++++++++++- include/pci_rom.h | 58 ++++++ include/rtc.h | 5 + include/vbe.h | 103 ++++++++++ include/video_fb.h | 2 +- lib/fdtdec.c | 3 + scripts/Makefile.lib | 2 + tools/.gitignore | 1 + 89 files changed, 5872 insertions(+), 363 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/bd82x6x.c create mode 100644 arch/x86/cpu/ivybridge/gma.c create mode 100644 arch/x86/cpu/ivybridge/gma.h create mode 100644 arch/x86/cpu/ivybridge/model_206ax.c create mode 100644 arch/x86/cpu/ivybridge/northbridge.c create mode 100644 arch/x86/cpu/ivybridge/pch.c create mode 100644 arch/x86/cpu/ivybridge/sata.c create mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c create mode 100644 arch/x86/cpu/ivybridge/usb_xhci.c create mode 100644 arch/x86/cpu/lapic.c create mode 100644 arch/x86/cpu/turbo.c create mode 100644 arch/x86/include/asm/acpi.h create mode 100644 arch/x86/include/asm/arch-ivybridge/bd82x6x.h create mode 100644 arch/x86/include/asm/ioapic.h create mode 100644 arch/x86/include/asm/speedstep.h create mode 100644 arch/x86/include/asm/turbo.h create mode 100644 arch/x86/lib/bios.c create mode 100644 arch/x86/lib/bios.h create mode 100644 arch/x86/lib/bios_asm.S create mode 100644 arch/x86/lib/bios_interrupts.c create mode 100644 doc/device-tree-bindings/ata/intel-sata.txt create mode 100644 doc/device-tree-bindings/video/intel-gma.txt create mode 100644 drivers/pci/pci_rom.c create mode 100644 drivers/video/x86_fb.c create mode 100644 include/bios_emul.h create mode 100644 include/pci_rom.h create mode 100644 include/vbe.h Regards, Simon

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Re: [U-Boot] [PATCH V2 06/12] lcd: replace CONSOLE_(ROWS|COLS) with variables
by Nikita Kiryanov 02 Dec '14

02 Dec '14

Hi Simon, On 11/30/2014 09:25 PM, Simon Glass wrote: > On 30 November 2014 at 05:29, Nikita Kiryanov <nikita(a)compulab.co.il> wrote: >> Replace CONSOLE_(ROWS|COLS) macros with variables, and assign the >> original macro values. >> >> This is a preparatory step for extracting lcd console code into its own >> file. >> >> Signed-off-by: Nikita Kiryanov <nikita(a)compulab.co.il> >> Cc: Anatolij Gustschin <agust(a)denx.de> >> Cc: Simon Glass <sjg(a)chromium.org> >> --- >> Changes in V2: >> - New patch. > > Are you intended to want to support multiple displays, or just to > change the resolution after start? This did cross my mind as possible future work, but for this patch set the change was driven by the goal of decoupling lcd_console stuff as much as possible from the rest of the code, which meant that I did not want to bring panel_info references into lcd_console.c (there's actually one use of panel_info still remaining in console_scrollup() but I'll get rid of it if/when this series is applied). In the case of console_cols and console_rows, the idea was that the use of panel_info can be avoided if lcd.c would pass the values as parameters to lcd_init_console() (introduced in a later patch), which meant that the macros had to be replaced with variables. > > Acked-by: Simon Glass <sjg(a)chromium.org> > > Tested on pit, LCD works fine. > > Tested-by: Simon Glass <sjg(a)chromium.org> > This mail did not reach mainline, so I'm Cc-ing the mailing list. I don't know if patchworks will register the Ack and Tested-by though, can you maybe resend them in a separate reply? -- Regards, Nikita Kiryanov

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[U-Boot] [PATCH v2 1/7] arm: rmobile: rcar: Move module control register to header file of SoC
by Nobuhiro Iwamatsu 02 Dec '14

02 Dec '14

Module control registers of R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) are same address. This moves these to header file of SoC. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- arch/arm/include/asm/arch-rmobile/rcar-base.h | 39 +++++++++++++++++++++++++++ board/renesas/alt/alt.c | 11 -------- board/renesas/gose/gose.c | 8 ------ board/renesas/koelsch/koelsch.c | 8 ------ board/renesas/lager/lager.c | 8 ------ 5 files changed, 39 insertions(+), 35 deletions(-) diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h index dbbebcf..23c4bba 100644 --- a/arch/arm/include/asm/arch-rmobile/rcar-base.h +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -29,6 +29,45 @@ #define SCIF4_BASE 0xE6EE0000 #define SCIF5_BASE 0xE6EE8000 +/* Module stop status register */ +#define MSTPSR0 0xE6150030 +#define MSTPSR1 0xE6150038 +#define MSTPSR2 0xE6150040 +#define MSTPSR3 0xE6150048 +#define MSTPSR4 0xE615004C +#define MSTPSR5 0xE615003C +#define MSTPSR7 0xE61501C4 +#define MSTPSR8 0xE61509A0 +#define MSTPSR9 0xE61509A4 +#define MSTPSR10 0xE61509A8 +#define MSTPSR11 0xE61509AC + +/* Realtime module stop control register */ +#define RMSTPCR0 0xE6150110 +#define RMSTPCR1 0xE6150114 +#define RMSTPCR2 0xE6150118 +#define RMSTPCR3 0xE615011C +#define RMSTPCR4 0xE6150120 +#define RMSTPCR5 0xE6150124 +#define RMSTPCR7 0xE615012C +#define RMSTPCR8 0xE6150980 +#define RMSTPCR9 0xE6150984 +#define RMSTPCR10 0xE6150988 +#define RMSTPCR11 0xE615098C + +/* System module stop control register */ +#define SMSTPCR0 0xE6150130 +#define SMSTPCR1 0xE6150134 +#define SMSTPCR2 0xE6150138 +#define SMSTPCR3 0xE615013C +#define SMSTPCR4 0xE6150140 +#define SMSTPCR5 0xE6150144 +#define SMSTPCR7 0xE615014C +#define SMSTPCR8 0xE6150990 +#define SMSTPCR9 0xE6150994 +#define SMSTPCR10 0xE6150998 +#define SMSTPCR11 0xE615099C + /* * SH-I2C * Ch2 and ch3 are different address. These are defined diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 523c5f1..bf90f2e 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -37,20 +37,9 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF2_MSTP719 (1 << 19) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) - -#define MSTPSR3 0xE6150048 -#define SMSTPCR3 0xE615013C #define IIC1_MSTP323 (1 << 23) #define mstp_setbits(type, addr, saddr, set) \ diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 715fba0..bb6849e 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -41,16 +41,8 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) #define mstp_setbits(type, addr, saddr, set) \ diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 244bc58..14d1770 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -43,16 +43,8 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) #define mstp_setbits(type, addr, saddr, set) \ diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 93273b2..23ef194 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -50,16 +50,8 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) #define mstp_setbits(type, addr, saddr, set) \ -- 2.1.3

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[U-Boot] [PATCH] powerpc/t1040qds: Add support of SD boot for T1040QDS Board
by Vijay Rai 02 Dec '14

02 Dec '14

Add support of 2 stage SD boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - Update tlb and ddr accordingly Add T1040QDS_SDCARD_defconfig Update t1040_pbi.cfg to support errata A-007662, A-008007 and LAW for CPC1 Signed-off-by: Vijay Rai <vijay.rai(a)freescale.com> --- board/freescale/t1040qds/MAINTAINERS | 5 ++ board/freescale/t1040qds/Makefile | 10 ++- board/freescale/t1040qds/ddr.c | 5 +- board/freescale/t1040qds/spl.c | 155 ++++++++++++++++++++++++++++++++ board/freescale/t1040qds/t1040_pbi.cfg | 16 +++- board/freescale/t1040qds/t1040qds.c | 6 +- board/freescale/t1040qds/tlb.c | 11 +++ configs/T1040QDS_SDCARD_defconfig | 5 ++ include/configs/T1040QDS.h | 85 ++++++++++++++---- 9 files changed, 275 insertions(+), 23 deletions(-) create mode 100644 board/freescale/t1040qds/spl.c create mode 100644 configs/T1040QDS_SDCARD_defconfig diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS index 83f6b3c..44d56b6 100644 --- a/board/freescale/t1040qds/MAINTAINERS +++ b/board/freescale/t1040qds/MAINTAINERS @@ -6,6 +6,11 @@ F: include/configs/T1040QDS.h F: configs/T1040QDS_defconfig F: configs/T1040QDS_D4_defconfig +T1040QDS_SDCARD BOARD +M: Priyanka Jain <Priyanka.Jain(a)freescale.com> +S: Maintained +F: configs/T1040QDS_SDCARD_defconfig + T1040QDS_SECURE_BOOT BOARD M: Aneesh Bansal <aneesh.bansal(a)freescale.com> S: Maintained diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 19ed21b..27eed4c 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += t1040qds.o -obj-y += ddr.o +obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_FSL_DIU_FB) += diu.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o -obj-y += eth.o -obj-y += diu.o diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 43f952f..6147430 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -104,13 +104,16 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t1040qds/spl.c b/board/freescale/t1040qds/spl.c new file mode 100644 index 0000000..b601c95 --- /dev/null +++ b/board/freescale/t1040qds/spl.c @@ -0,0 +1,155 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> +#include "../common/qixis.h" +#include "t1040qds_qixis.h" +#include <asm/mpc85xx_gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#ifdef CONFIG_SPL_NAND_BOOT + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg index 10b1a6d..f7d9a74 100644 --- a/board/freescale/t1040qds/t1040_pbi.cfg +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -1,4 +1,14 @@ #PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 #Initialize CPC1 09010000 00200400 09138000 00000000 @@ -9,9 +19,9 @@ 09010f00 08000000 09010000 80000000 #Configure LAW for CPC1 -09000cf0 00000000 -09000cf4 fffc0000 -09000cf8 81000011 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 #Configure alternate space 09000010 00000000 09000014 ff000000 diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 19af46e..7d24348 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -277,7 +277,11 @@ void qixis_dump_switch(void) int board_need_mem_reset(void) { - return 1; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + return 1; +#else + return 0; +#endif } #ifdef CONFIG_DEEP_SLEEP diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c index 412c591..0a7ceda 100644 --- a/board/freescale/t1040qds/tlb.c +++ b/board/freescale/t1040qds/tlb.c @@ -53,6 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -82,6 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -103,6 +105,15 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 11, BOOKE_PAGESZ_4K, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/T1040QDS_SDCARD_defconfig b/configs/T1040QDS_SDCARD_defconfig new file mode 100644 index 0000000..fbee8c5 --- /dev/null +++ b/configs/T1040QDS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T1040QDS=y diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index a781ba3..c267e00 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -30,11 +30,47 @@ #define CONFIG_PHYS_64BIT #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg + +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH #endif +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE @@ -72,15 +108,12 @@ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#else +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif -#ifndef CONFIG_SYS_NO_FLASH #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH @@ -96,7 +129,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND @@ -149,6 +182,17 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -175,8 +219,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_SPD #ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 -#define CONFIG_FSL_DDR_INTERACTIVE #endif +#define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -359,7 +403,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -407,7 +455,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER @@ -631,15 +681,21 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif + +#if defined(CONFIG_SDCARD) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#else #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 #endif + #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ @@ -762,8 +818,7 @@ unsigned long get_board_ddr_clk(void); #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ + "hwconfig=fsl_ddr:bank_intlv=auto;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ -- 1.7.9.5

2 1

[U-Boot] [PATCH 1/7] arm: rmobile: Move module control register to header file of SoC
by Nobuhiro Iwamatsu 01 Dec '14

01 Dec '14

Module control registers of R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) are same address. This moves these to header file of SoC. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- arch/arm/include/asm/arch-rmobile/rcar-base.h | 39 +++++++++++++++++++++++++++ board/renesas/alt/alt.c | 11 -------- board/renesas/gose/gose.c | 8 ------ board/renesas/koelsch/koelsch.c | 8 ------ board/renesas/lager/lager.c | 8 ------ 5 files changed, 39 insertions(+), 35 deletions(-) diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h index dbbebcf..23c4bba 100644 --- a/arch/arm/include/asm/arch-rmobile/rcar-base.h +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -29,6 +29,45 @@ #define SCIF4_BASE 0xE6EE0000 #define SCIF5_BASE 0xE6EE8000 +/* Module stop status register */ +#define MSTPSR0 0xE6150030 +#define MSTPSR1 0xE6150038 +#define MSTPSR2 0xE6150040 +#define MSTPSR3 0xE6150048 +#define MSTPSR4 0xE615004C +#define MSTPSR5 0xE615003C +#define MSTPSR7 0xE61501C4 +#define MSTPSR8 0xE61509A0 +#define MSTPSR9 0xE61509A4 +#define MSTPSR10 0xE61509A8 +#define MSTPSR11 0xE61509AC + +/* Realtime module stop control register */ +#define RMSTPCR0 0xE6150110 +#define RMSTPCR1 0xE6150114 +#define RMSTPCR2 0xE6150118 +#define RMSTPCR3 0xE615011C +#define RMSTPCR4 0xE6150120 +#define RMSTPCR5 0xE6150124 +#define RMSTPCR7 0xE615012C +#define RMSTPCR8 0xE6150980 +#define RMSTPCR9 0xE6150984 +#define RMSTPCR10 0xE6150988 +#define RMSTPCR11 0xE615098C + +/* System module stop control register */ +#define SMSTPCR0 0xE6150130 +#define SMSTPCR1 0xE6150134 +#define SMSTPCR2 0xE6150138 +#define SMSTPCR3 0xE615013C +#define SMSTPCR4 0xE6150140 +#define SMSTPCR5 0xE6150144 +#define SMSTPCR7 0xE615014C +#define SMSTPCR8 0xE6150990 +#define SMSTPCR9 0xE6150994 +#define SMSTPCR10 0xE6150998 +#define SMSTPCR11 0xE615099C + /* * SH-I2C * Ch2 and ch3 are different address. These are defined diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 523c5f1..bf90f2e 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -37,20 +37,9 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF2_MSTP719 (1 << 19) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) - -#define MSTPSR3 0xE6150048 -#define SMSTPCR3 0xE615013C #define IIC1_MSTP323 (1 << 23) #define mstp_setbits(type, addr, saddr, set) \ diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 715fba0..bb6849e 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -41,16 +41,8 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) #define mstp_setbits(type, addr, saddr, set) \ diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 244bc58..14d1770 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -43,16 +43,8 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) #define mstp_setbits(type, addr, saddr, set) \ diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 93273b2..23ef194 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -50,16 +50,8 @@ void s_init(void) qos_init(); } -#define MSTPSR1 0xE6150038 -#define SMSTPCR1 0xE6150134 #define TMU0_MSTP125 (1 << 25) - -#define MSTPSR7 0xE61501C4 -#define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) - -#define MSTPSR8 0xE61509A0 -#define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) #define mstp_setbits(type, addr, saddr, set) \ -- 2.1.3

2 8

[U-Boot] [PATCH v3] fs/ext4/ext4fs.c, fs/fs.c fs/fat/fat_write.c: Adjust 64bit math methods
by Tom Rini 01 Dec '14

01 Dec '14

The changes to introduce loff_t into filesize means that we need to do 64bit math on 32bit platforms. Make sure we use the right wrappers for these operations. Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Suriyan Ramasami <suriyan.r(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)ti.com> --- Changes in v3: - Fix bug Simon pointed out in fs/fs.c Changes in v2: - Correct fs/fat/fat_write.c --- fs/ext4/ext4fs.c | 11 ++++++----- fs/fat/fat_write.c | 10 ++++++---- fs/fs.c | 6 ++++-- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 943b5bc..258b9379 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -25,6 +25,7 @@ #include <ext_common.h> #include <ext4fs.h> #include "ext4_common.h" +#include <div64.h> int ext4fs_symlinknest; struct ext_filesystem ext_fs; @@ -67,11 +68,11 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, if (len > filesize) len = filesize; - blockcnt = ((len + pos) + blocksize - 1) / blocksize; + blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize); - for (i = pos / blocksize; i < blockcnt; i++) { + for (i = lldiv(pos, blocksize); i < blockcnt; i++) { lbaint_t blknr; - int blockoff = pos % blocksize; + int blockoff = pos - (blocksize * i); int blockend = blocksize; int skipfirst = 0; blknr = read_allocated_block(&(node->inode), i); @@ -82,7 +83,7 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, /* Last block. */ if (i == blockcnt - 1) { - blockend = (len + pos) % blocksize; + blockend = (len + pos) - (blocksize * i); /* The last portion is exactly blocksize. */ if (!blockend) @@ -90,7 +91,7 @@ int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, } /* First block. */ - if (i == pos / blocksize) { + if (i == lldiv(pos, blocksize)) { skipfirst = blockoff; blockend -= skipfirst; } diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 88dd495..473723b 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -13,6 +13,8 @@ #include <asm/byteorder.h> #include <part.h> #include <linux/ctype.h> +#include <div64.h> +#include <linux/math64.h> #include "fat.c" static void uppercase(char *str, int len) @@ -770,7 +772,7 @@ static void fill_dentry(fsdata *mydata, dir_entry *dentptr, */ static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size) { - __u32 startsect, sect_num; + __u32 startsect, sect_num, offset; if (clustnum > 0) { startsect = mydata->data_begin + @@ -779,13 +781,13 @@ static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size) startsect = mydata->rootdir_sect; } - sect_num = size / mydata->sect_size; - if (size % mydata->sect_size) + sect_num = div_u64_rem(size, mydata->sect_size, &offset); + + if (offset != 0) sect_num++; if (startsect + sect_num > cur_part_info.start + total_sector) return -1; - return 0; } diff --git a/fs/fs.c b/fs/fs.c index 3da7860..ddd751c 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -23,6 +23,8 @@ #include <fs.h> #include <sandboxfs.h> #include <asm/io.h> +#include <div64.h> +#include <linux/math64.h> DECLARE_GLOBAL_DATA_PTR; @@ -399,7 +401,7 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], printf("%llu bytes read in %lu ms", len_read, time); if (time > 0) { puts(" ("); - print_size(len_read / time * 1000, "/s"); + print_size(div_u64(len_read, time) * 1000, "/s"); puts(")"); } puts("\n"); @@ -469,7 +471,7 @@ int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], printf("%llu bytes written in %lu ms", len, time); if (time > 0) { puts(" ("); - print_size(len / time * 1000, "/s"); + print_size(div_u64(len, time) * 1000, "/s"); puts(")"); } puts("\n"); -- 1.7.9.5

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[U-Boot] Pull request: u-boot-uniphier/master
by Masahiro YAMADA 01 Dec '14

01 Dec '14

Hi Tom, This series introduces Device Tree control support to Panasonic UniPhier platform. The following changes since commit 85bafb6da4dddfffa78479aa49a72ae48578a4ce: Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq (2014-11-26 11:23:26 -0500) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to 25e274e20208e047ea93afde04040e8c87430904: ARM: UniPhier: move CONFIG_CMD_* and CONFIG_FIT* defines to defconfig (2014-11-28 02:21:02 +0900) ---------------------------------------------------------------- Masahiro Yamada (7): ARM: UniPhier: do not compile platform data when CONFIG_OF_CONTROL=y ARM: UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROL ARM: UniPhier: add device tree sources serial: UniPhier: support OF configuration usb: UniPhier: support OF configuration ARM: UniPhier: enable Device Tree control ARM: UniPhier: move CONFIG_CMD_* and CONFIG_FIT* defines to defconfig arch/arm/Kconfig | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 2 +- arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c | 1 - arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 2 +- arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c | 1 - arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 2 +- arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c | 1 - arch/arm/dts/Makefile | 4 +++ arch/arm/dts/uniphier-ph1-ld4-ref.dts | 42 +++++++++++++++++++++++++++++++ arch/arm/dts/uniphier-ph1-ld4.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/uniphier-ph1-pro4-ref.dts | 42 +++++++++++++++++++++++++++++++ arch/arm/dts/uniphier-ph1-pro4.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/uniphier-ph1-sld8-ref.dts | 42 +++++++++++++++++++++++++++++++ arch/arm/dts/uniphier-ph1-sld8.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-uniphier/gpio.h | 6 +++++ configs/ph1_ld4_defconfig | 26 ++++++++++++++++++++ configs/ph1_pro4_defconfig | 26 ++++++++++++++++++++ configs/ph1_sld8_defconfig | 26 ++++++++++++++++++++ drivers/serial/serial_uniphier.c | 19 ++++++++------ drivers/usb/host/ehci-uniphier.c | 38 +++++++++++++++++++++++++++- include/configs/uniphier-common.h | 15 ----------- 21 files changed, 500 insertions(+), 30 deletions(-) create mode 100644 arch/arm/dts/uniphier-ph1-ld4-ref.dts create mode 100644 arch/arm/dts/uniphier-ph1-ld4.dtsi create mode 100644 arch/arm/dts/uniphier-ph1-pro4-ref.dts create mode 100644 arch/arm/dts/uniphier-ph1-pro4.dtsi create mode 100644 arch/arm/dts/uniphier-ph1-sld8-ref.dts create mode 100644 arch/arm/dts/uniphier-ph1-sld8.dtsi create mode 100644 arch/arm/include/asm/arch-uniphier/gpio.h -- Best Regards Masahiro Yamada

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[U-Boot] [PATCH v3 1/4] dts: Bring in Chrome OS keyboard device tree definition
by Simon Glass 01 Dec '14

01 Dec '14

This will be used by nyan, but bring it in in a separate patch since it will be common to other boards. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Add patch to bring in cros-ec-keyboard.dtsi Changes in v2: None arch/arm/dts/cros-ec-keyboard.dtsi | 105 +++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/arm/dts/cros-ec-keyboard.dtsi diff --git a/arch/arm/dts/cros-ec-keyboard.dtsi b/arch/arm/dts/cros-ec-keyboard.dtsi new file mode 100644 index 0000000..9c7fb0a --- /dev/null +++ b/arch/arm/dts/cros-ec-keyboard.dtsi @@ -0,0 +1,105 @@ +/* + * Keyboard dts fragment for devices that use cros-ec-keyboard + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <dt-bindings/input/input.h> + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) + MATRIX_KEY(0x00, 0x02, KEY_F1) + MATRIX_KEY(0x00, 0x03, KEY_B) + MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x06, KEY_N) + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) + + MATRIX_KEY(0x01, 0x01, KEY_ESC) + MATRIX_KEY(0x01, 0x02, KEY_F4) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_F7) + MATRIX_KEY(0x01, 0x06, KEY_H) + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) + MATRIX_KEY(0x01, 0x09, KEY_F9) + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) + MATRIX_KEY(0x02, 0x01, KEY_TAB) + MATRIX_KEY(0x02, 0x02, KEY_F3) + MATRIX_KEY(0x02, 0x03, KEY_T) + MATRIX_KEY(0x02, 0x04, KEY_F6) + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) + MATRIX_KEY(0x02, 0x06, KEY_Y) + MATRIX_KEY(0x02, 0x07, KEY_102ND) + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) + MATRIX_KEY(0x02, 0x09, KEY_F8) + + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) + MATRIX_KEY(0x03, 0x02, KEY_F2) + MATRIX_KEY(0x03, 0x03, KEY_5) + MATRIX_KEY(0x03, 0x04, KEY_F5) + MATRIX_KEY(0x03, 0x06, KEY_6) + MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x04, 0x02, KEY_D) + MATRIX_KEY(0x04, 0x03, KEY_F) + MATRIX_KEY(0x04, 0x04, KEY_S) + MATRIX_KEY(0x04, 0x05, KEY_K) + MATRIX_KEY(0x04, 0x06, KEY_J) + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) + MATRIX_KEY(0x04, 0x09, KEY_L) + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) + + MATRIX_KEY(0x05, 0x01, KEY_Z) + MATRIX_KEY(0x05, 0x02, KEY_C) + MATRIX_KEY(0x05, 0x03, KEY_V) + MATRIX_KEY(0x05, 0x04, KEY_X) + MATRIX_KEY(0x05, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x06, KEY_M) + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) + MATRIX_KEY(0x05, 0x08, KEY_SLASH) + MATRIX_KEY(0x05, 0x09, KEY_DOT) + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) + + MATRIX_KEY(0x06, 0x01, KEY_1) + MATRIX_KEY(0x06, 0x02, KEY_3) + MATRIX_KEY(0x06, 0x03, KEY_4) + MATRIX_KEY(0x06, 0x04, KEY_2) + MATRIX_KEY(0x06, 0x05, KEY_8) + MATRIX_KEY(0x06, 0x06, KEY_7) + MATRIX_KEY(0x06, 0x08, KEY_0) + MATRIX_KEY(0x06, 0x09, KEY_9) + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) + + MATRIX_KEY(0x07, 0x01, KEY_Q) + MATRIX_KEY(0x07, 0x02, KEY_E) + MATRIX_KEY(0x07, 0x03, KEY_R) + MATRIX_KEY(0x07, 0x04, KEY_W) + MATRIX_KEY(0x07, 0x05, KEY_I) + MATRIX_KEY(0x07, 0x06, KEY_U) + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) + MATRIX_KEY(0x07, 0x08, KEY_P) + MATRIX_KEY(0x07, 0x09, KEY_O) + MATRIX_KEY(0x07, 0x0b, KEY_UP) + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + >; + }; +}; -- 2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v4 1/3] dts: Bring in Chrome OS keyboard device tree definition
by Simon Glass 01 Dec '14

01 Dec '14

This will be used by nyan-big, but bring it in in a separate patch since it will be common to other boards. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v4: None Changes in v3: - Add patch to bring in cros-ec-keyboard.dtsi Changes in v2: None arch/arm/dts/cros-ec-keyboard.dtsi | 105 +++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/arm/dts/cros-ec-keyboard.dtsi diff --git a/arch/arm/dts/cros-ec-keyboard.dtsi b/arch/arm/dts/cros-ec-keyboard.dtsi new file mode 100644 index 0000000..9c7fb0a --- /dev/null +++ b/arch/arm/dts/cros-ec-keyboard.dtsi @@ -0,0 +1,105 @@ +/* + * Keyboard dts fragment for devices that use cros-ec-keyboard + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <dt-bindings/input/input.h> + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) + MATRIX_KEY(0x00, 0x02, KEY_F1) + MATRIX_KEY(0x00, 0x03, KEY_B) + MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x06, KEY_N) + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) + + MATRIX_KEY(0x01, 0x01, KEY_ESC) + MATRIX_KEY(0x01, 0x02, KEY_F4) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_F7) + MATRIX_KEY(0x01, 0x06, KEY_H) + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) + MATRIX_KEY(0x01, 0x09, KEY_F9) + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) + MATRIX_KEY(0x02, 0x01, KEY_TAB) + MATRIX_KEY(0x02, 0x02, KEY_F3) + MATRIX_KEY(0x02, 0x03, KEY_T) + MATRIX_KEY(0x02, 0x04, KEY_F6) + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) + MATRIX_KEY(0x02, 0x06, KEY_Y) + MATRIX_KEY(0x02, 0x07, KEY_102ND) + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) + MATRIX_KEY(0x02, 0x09, KEY_F8) + + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) + MATRIX_KEY(0x03, 0x02, KEY_F2) + MATRIX_KEY(0x03, 0x03, KEY_5) + MATRIX_KEY(0x03, 0x04, KEY_F5) + MATRIX_KEY(0x03, 0x06, KEY_6) + MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x04, 0x02, KEY_D) + MATRIX_KEY(0x04, 0x03, KEY_F) + MATRIX_KEY(0x04, 0x04, KEY_S) + MATRIX_KEY(0x04, 0x05, KEY_K) + MATRIX_KEY(0x04, 0x06, KEY_J) + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) + MATRIX_KEY(0x04, 0x09, KEY_L) + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) + + MATRIX_KEY(0x05, 0x01, KEY_Z) + MATRIX_KEY(0x05, 0x02, KEY_C) + MATRIX_KEY(0x05, 0x03, KEY_V) + MATRIX_KEY(0x05, 0x04, KEY_X) + MATRIX_KEY(0x05, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x06, KEY_M) + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) + MATRIX_KEY(0x05, 0x08, KEY_SLASH) + MATRIX_KEY(0x05, 0x09, KEY_DOT) + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) + + MATRIX_KEY(0x06, 0x01, KEY_1) + MATRIX_KEY(0x06, 0x02, KEY_3) + MATRIX_KEY(0x06, 0x03, KEY_4) + MATRIX_KEY(0x06, 0x04, KEY_2) + MATRIX_KEY(0x06, 0x05, KEY_8) + MATRIX_KEY(0x06, 0x06, KEY_7) + MATRIX_KEY(0x06, 0x08, KEY_0) + MATRIX_KEY(0x06, 0x09, KEY_9) + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) + + MATRIX_KEY(0x07, 0x01, KEY_Q) + MATRIX_KEY(0x07, 0x02, KEY_E) + MATRIX_KEY(0x07, 0x03, KEY_R) + MATRIX_KEY(0x07, 0x04, KEY_W) + MATRIX_KEY(0x07, 0x05, KEY_I) + MATRIX_KEY(0x07, 0x06, KEY_U) + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) + MATRIX_KEY(0x07, 0x08, KEY_P) + MATRIX_KEY(0x07, 0x09, KEY_O) + MATRIX_KEY(0x07, 0x0b, KEY_UP) + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + >; + }; +}; -- 2.2.0.rc0.207.ga3a616c

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