December 2014 - U-Boot

[U-Boot] [PATCH] arm: ls102xa: Update PCIe dts node status
by Minghuan Lian 11 Dec '14

11 Dec '14

The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/config.h | 3 ++ arch/arm/include/asm/pcie_layerscape.h | 13 ++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 5 +++ board/freescale/ls1021atwr/ls1021atwr.c | 5 +++ drivers/pci/Makefile | 1 + drivers/pci/pcie_layerscape.c | 51 ++++++++++++++++++++++++++++++ include/configs/ls1021aqds.h | 8 +++++ include/configs/ls1021atwr.h | 7 ++++ 8 files changed, 93 insertions(+) create mode 100644 arch/arm/include/asm/pcie_layerscape.h create mode 100644 drivers/pci/pcie_layerscape.c diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index f2c9687..9fd0b2c 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -49,6 +49,9 @@ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h new file mode 100644 index 0000000..fb08578 --- /dev/null +++ b/arch/arm/include/asm/pcie_layerscape.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PCIE_LAYERSCAPE_H_ +#define __PCIE_LAYERSCAPE_H_ + +void pci_init_board(void); +void ft_pcie_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 5fafc85..fccf6b6 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -10,6 +10,7 @@ #include <asm/arch/immap_ls102xa.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#include <asm/pcie_layerscape.h> #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> @@ -243,6 +244,10 @@ int board_init(void) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif } u8 flash_read8(void *addr) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 50d5640..0b548eb 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -10,6 +10,7 @@ #include <asm/arch/immap_ls102xa.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#include <asm/pcie_layerscape.h> #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> @@ -293,6 +294,10 @@ int misc_init_r(void) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif } u8 flash_read8(void *addr) diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index e73a498..e525ceb 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o obj-$(CONFIG_WINBOND_83C553) += w83c553f.o +obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c new file mode 100644 index 0000000..291c249 --- /dev/null +++ b/drivers/pci/pcie_layerscape.c @@ -0,0 +1,51 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Layerscape PCIe driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/pcie_layerscape.h> + +#ifdef CONFIG_OF_BOARD_SETUP +#include <libfdt.h> +#include <fdt_support.h> + +static void ft_pcie_ls_setup(void *blob, const char *pci_compat, + unsigned long ctrl_addr, enum srds_prtcl dev) +{ + int off; + + off = fdt_node_offset_by_compat_reg(blob, pci_compat, + (phys_addr_t)ctrl_addr); + if (off < 0) + return; + + if (!is_serdes_configured(dev)) + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +} + +void ft_pcie_setup(void *blob, bd_t *bd) +{ + #ifdef CONFIG_PCIE1 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); + #endif + + #ifdef CONFIG_PCIE2 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); + #endif +} + +#else +void ft_pcie_setup(void *blob, bd_t *bd) +{ +} +#endif + +void pci_init_board(void) +{ +} diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d1f6ea7..5544b81 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -318,6 +318,14 @@ unsigned long get_board_ddr_clk(void); #endif #endif + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3c73af8..15873a9 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -220,6 +220,13 @@ #define CONFIG_HAS_ETH2 #endif +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -- 1.9.1

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[U-Boot] [PATCH] arm: ls102xa: clear EPU registers for deep sleep
by Chenhui Zhao 11 Dec '14

11 Dec '14

After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +++++++ arch/arm/cpu/armv7/ls102xa/fsl_epu.c | 57 +++++++++++++++++++++++ arch/arm/cpu/armv7/ls102xa/fsl_epu.h | 68 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + 5 files changed, 143 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.c create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.h diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index d82ce8d..ae4f25d 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -7,6 +7,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o +obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index b7dde45..fae6c68 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -12,6 +12,8 @@ #include <netdev.h> #include <fsl_esdhc.h> +#include "fsl_epu.h" + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_DISPLAY_CPUINFO) @@ -101,3 +103,17 @@ int cpu_eth_init(bd_t *bis) return 0; } + +int arch_cpu_init(void) +{ + void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + + /* + * After wakeup from deep sleep, Clear EPU registers + * as early as possible to prevent from possible issue. + * It's also safe to clear at normal boot. + */ + fsl_epu_clean(epu_base); + + return 0; +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c new file mode 100644 index 0000000..6212640 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c @@ -0,0 +1,57 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +#include "fsl_epu.h" + +/** + * fsl_epu_clean - Clear EPU registers + */ +void fsl_epu_clean(void *epu_base) +{ + u32 offset; + + /* follow the exact sequence to clear the registers */ + /* Clear EPACRn */ + for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPEVTCRn */ + for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPGCR */ + out_be32(epu_base + EPGCR, 0); + + /* Clear EPSMCRn */ + for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCCRn */ + for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCMPRn */ + for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCTRn */ + for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPIMCRn */ + for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPXTRIGCRn */ + out_be32(epu_base + EPXTRIGCR, 0); + + /* Clear EPECRn */ + for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE) + out_be32(epu_base + offset, 0); +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h new file mode 100644 index 0000000..d658aad --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h @@ -0,0 +1,68 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_EPU_H +#define __FSL_EPU_H + +#include <asm/types.h> + +#define FSL_STRIDE_4B 4 +#define FSL_STRIDE_8B 8 + +/* Block offsets */ +#define EPU_BLOCK_OFFSET 0x00000000 + +/* EPGCR (Event Processor Global Control Register) */ +#define EPGCR 0x000 + +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */ +#define EPEVTCR0 0x050 +#define EPEVTCR9 0x074 +#define EPEVTCR_STRIDE FSL_STRIDE_4B + +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ +#define EPXTRIGCR 0x090 + +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */ +#define EPIMCR0 0x100 +#define EPIMCR31 0x17C +#define EPIMCR_STRIDE FSL_STRIDE_4B + +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */ +#define EPSMCR0 0x200 +#define EPSMCR15 0x278 +#define EPSMCR_STRIDE FSL_STRIDE_8B + +/* EPECR0-15 (Event Processor Event Control Registers) */ +#define EPECR0 0x300 +#define EPECR15 0x33C +#define EPECR_STRIDE FSL_STRIDE_4B + +/* EPACR0-15 (Event Processor Action Control Registers) */ +#define EPACR0 0x400 +#define EPACR15 0x43C +#define EPACR_STRIDE FSL_STRIDE_4B + +/* EPCCRi0-15 (Event Processor Counter Control Registers) */ +#define EPCCR0 0x800 +#define EPCCR15 0x83C +#define EPCCR31 0x87C +#define EPCCR_STRIDE FSL_STRIDE_4B + +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */ +#define EPCMPR0 0x900 +#define EPCMPR15 0x93C +#define EPCMPR31 0x97C +#define EPCMPR_STRIDE FSL_STRIDE_4B + +/* EPCTR0-31 (Event Processor Counter Register) */ +#define EPCTR0 0xA00 +#define EPCTR31 0xA7C +#define EPCTR_STRIDE FSL_STRIDE_4B + +void fsl_epu_clean(void *epu_base); + +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index f2c9687..6fff74c 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -13,6 +13,7 @@ #define OCRAM_SIZE 0x00020000 #define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) -- 1.7.3

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[U-Boot] [PATCH] arm: ls102xa: fixed a bus frequency setting error
by Yuantian.Tang＠freescale.com 11 Dec '14

11 Dec '14

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 4ce3808..989780d 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -91,7 +91,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) } do_fixup_by_prop_u32(blob, "device_type", "soc", - 4, "bus-frequency", busclk / 2, 1); + 4, "bus-frequency", busclk, 1); ft_fixup_enet_phy_connect_type(blob); -- 2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v5 3/3] ARM: tegra: Add support for nyan-big board
by Simon Glass 11 Dec '14

11 Dec '14

Hi Tom, On 10 December 2014 at 14:09, Tom Warren <TWarren(a)nvidia.com> wrote: > Simon, > >> -----Original Message----- >> From: sjg(a)google.com [mailto:sjg@google.com] On Behalf Of Simon Glass >> Sent: Wednesday, December 10, 2014 2:04 PM >> To: Tom Warren >> Cc: U-Boot Mailing List; Stephen Warren; Allen Martin; Stephen Warren; >> Albert Aribaud >> Subject: Re: [PATCH v5 3/3] ARM: tegra: Add support for nyan-big board >> >> Hi Tom, >> >> On 10 December 2014 at 12:36, Simon Glass <sjg(a)chromium.org> wrote: >> > Hi Tom, >> > >> > On Dec 10, 2014 12:05 PM, "Tom Warren" <TWarren(a)nvidia.com> wrote: >> >> >> >> Simon, >> >> >> >> > -----Original Message----- >> >> > From: sjg(a)google.com [mailto:sjg@google.com] On Behalf Of Simon >> >> > Glass >> >> > Sent: Wednesday, December 10, 2014 10:50 AM >> >> > To: Tom Warren >> >> > Cc: U-Boot Mailing List; Allen Martin; Albert Aribaud; Stephen >> >> > Warren; Stephen Warren >> >> > Subject: Re: [PATCH v5 3/3] ARM: tegra: Add support for nyan-big >> >> > board >> >> > >> >> > Hi Tom, >> >> > >> >> > >> >> > On 10 December 2014 at 10:39, Tom Warren <TWarren(a)nvidia.com> >> wrote: >> >> > > Simon, >> >> > > >> >> > > The v4 PCIE patch series fails to apply to u-boot-tegra/master >> >> > > after >> >> > rebasing my repo against both ARM master and U-Boot 'master' master >> >> > (i.e. >> >> > FETCH_HEAD = >> >> > > 32fdf0e4d82bdca5d64d86330e461e59685f9959 branch 'master' of >> >> > git://git.denx.de/u-boot). 3 - 4 patches fail when using git am. >> >> > > >> >> > > I worked thru the conflicts for both branches (my master rebased >> >> > > against >> >> > ARM and U-Boot TOT), and did a MAKEALL -s tegra, and jetson-tk1, >> >> > beaver and cardhu fail to build (jetson err log below). Looks like >> >> > you developed this with your DM I2C series in place? >> >> > > >> >> > > To submit a PR from the Tegra repo, I need to either rebase first >> >> > > against >> >> > ARM master (my SOP), or against U-Boot 'master'. So you patches, >> >> > if they're bound for the Tegra repo, need to work in one of those >> >> > scenarios. >> >> > > >> >> > > Tom >> >> > >> >> > Thanks for looking at it. This series depends on the I2C driver >> >> > model series. >> >> > It's available at u-boot-dm/i2c-working if you want to check it >> >> > out. I plan to apply that very soon. >> >> > >> >> > I'm sorry I didn't make that clear in this series. I mentioned it >> >> > on the list at one point but should have added it here. If you >> >> > like, you could ack it and I can apply to u-boot-dm after I2C is in >> >> > there. >> >> I can't ACK something that I can't get to apply to my repo nor build >> >> nor test. So you'll have to wait on that from Stephen, Thierry (based >> >> on code >> >> review) or someone that wants to add DM I2C to Tegra, apply your PCIe >> >> patches, and test. That's not my normal workflow, though, and I don't >> >> have the BW to devote to extra hurdles right now. >> >> >> > >> > You could try applying to u-boot-dm/i2c-working. It only has the DM >> > i2c series in it, plus Tegra stuff. I put a lot of time into cleaning >> > up this Tegra series to save you and Thierry time. >> >> Also Thierry took a look the PCIe series and responded here: >> >> http://patchwork.ozlabs.org/patch/410175/ >> >> There were three nits which I have addressed. >> >> For this Nyan-big patch I really don't need a test credit (would be nice, but >> not necessary). After all it's a new board and if problems are found they can >> be fixed. But I do need to apply it before DM I2C. >> Stephen has looked at a few revs. >> >> How about this for a plan: >> >> - Apply Nyan-big to DM >> - Apply DM I2C series to DM >> - Pull request to mainline (final for DM this release unless SPL is resolved >> somehow) >> >> Then if you have time: >> - Tom - apply PCIe to Tegra tree >> - Pull request to mainline > The problem there is that I'd need to wait for the PR to mainline to go thru before I could rebase Tegra against mainline, and only then apply PCIe patches. Time-wise, it's obviously better for you to do this in one fell swoop from the DM repo. > > Does the nyan-big patchset apply/build cleanly in u-boot-tegra/master? If so, I can apply it and do a Tegra test build and then send a PR to Albert if all is clear. OK, true. The Tegra tree is too far behind master, but if you catch it up you can make it work: (try-nyan=9e10b9: b/ common/ doc/ sandbox/) u> pwclient git-am 417781 Applying patch #417781 using 'git am' Description: [U-Boot,v5,1/3] dts: Bring in Chrome OS keyboard device tree definition Applying: dts: Bring in Chrome OS keyboard device tree definition (try-nyan=ddebcc: b/ common/ doc/ sandbox/) u> pwclient git-am 417782 Applying patch #417782 using 'git am' Description: [U-Boot,v5,2/3] tegra: dts: Sync tegra124.dtsi with linux kernel Applying: tegra: dts: Sync tegra124.dtsi with linux kernel ^[[A(try-nyan=9df313: b/ common/ doc/ sandbox/) u> pwclient git-am 417783 Applying patch #417783 using 'git am' Description: [U-Boot,v5,3/3] ARM: tegra: Add support for nyan-big board Applying: ARM: tegra: Add support for nyan-big board error: patch failed: arch/arm/dts/Makefile:31 error: arch/arm/dts/Makefile: patch does not apply Patch failed at 0001 ARM: tegra: Add support for nyan-big board The copy of the patch that failed is found in: /usr/local/google/home/sjg/u/.git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". (try-nyan=9df313: b/ common/ doc/ sandbox/) u> patch -p1 < /usr/local/google/home/sjg/u/.git/rebase-apply/patch patching file arch/arm/cpu/armv7/tegra124/Kconfig patching file arch/arm/dts/Makefile Hunk #1 succeeded at 29 with fuzz 2 (offset -2 lines). patching file arch/arm/dts/tegra124-nyan-big.dts patching file board/nvidia/nyan-big/Kconfig patching file board/nvidia/nyan-big/MAINTAINERS patching file board/nvidia/nyan-big/Makefile patching file board/nvidia/nyan-big/nyan-big.c patching file board/nvidia/nyan-big/pinmux-config-nyan-big.h patching file board/nvidia/venice2/as3722_init.h patching file configs/nyan-big_defconfig patching file include/configs/nyan-big.h Then: git add arch/arm/cpu/armv7/tegra124/Kconfig arch/arm/dts/Makefile board/nvidia/venice2/as3722_init.h arch/arm/dts/tegra124-nyan-big.dts board/nvidia/nyan-big/ configs/nyan-big_defconfig include/configs/nyan-big.h git am --resolved I've pushed it to u-boot-dm/for-tom. It all builds cleanly for me. Regards, Simon > >> >> If you don't have time, I could do this last bit through DM. In any case the >> problem is that it is getting late and we need to resolve this soon. >> >> Regards, >> Simon >> >> > >> > Regards, >> > Simon >> > >> >> Tom >> >> > >> >> > Regards, >> >> > Simon >> >> > > >> >> > > drivers/power/as3722.c: In function 'as3722_read': >> >> > > drivers/power/as3722.c:34: warning: passing argument 1 of 'i2c_read' >> >> > > makes integer from pointer without a cast >> >> > > include/i2c.h:235: note: expected 'uint8_t' but argument is of >> >> > > type 'struct >> >> > udevice *' >> >> > > drivers/power/as3722.c:34: warning: passing argument 3 of 'i2c_read' >> >> > > makes integer from pointer without a cast >> >> > > include/i2c.h:235: note: expected 'int' but argument is of type 'u8 *' >> >> > > drivers/power/as3722.c:34: warning: passing argument 4 of 'i2c_read' >> >> > > makes pointer from integer without a cast >> >> > > include/i2c.h:235: note: expected 'uint8_t *' but argument is of >> >> > > type 'int' >> >> > > drivers/power/as3722.c:34: error: too few arguments to function >> >> > > 'i2c_read' >> >> > > drivers/power/as3722.c: In function 'as3722_write': >> >> > > drivers/power/as3722.c:45: warning: passing argument 1 of 'i2c_write' >> >> > > makes integer from pointer without a cast >> >> > > include/i2c.h:238: note: expected 'uint8_t' but argument is of >> >> > > type 'struct >> >> > udevice *' >> >> > > drivers/power/as3722.c:45: warning: passing argument 3 of 'i2c_write' >> >> > > makes integer from pointer without a cast >> >> > > include/i2c.h:238: note: expected 'int' but argument is of type 'u8 *' >> >> > > drivers/power/as3722.c:45: warning: passing argument 4 of 'i2c_write' >> >> > > makes pointer from integer without a cast >> >> > > include/i2c.h:238: note: expected 'uint8_t *' but argument is of >> >> > > type 'int' >> >> > > drivers/power/as3722.c:45: error: too few arguments to function >> >> > 'i2c_write' >> >> > > drivers/power/as3722.c: In function 'as3722_init': >> >> > > drivers/power/as3722.c:245: warning: implicit declaration of >> >> > > function >> >> > 'i2c_get_chip_for_busnum' >> >> > > make[1]: *** [drivers/power/as3722.o] Error 1 >> >> > > make: *** [drivers/power] Error 2 >> >> > > make: *** Waiting for unfinished jobs.... >> >> > > >> >> > >> -----Original Message----- >> >> > >> From: Tom Warren >> >> > >> Sent: Wednesday, December 10, 2014 8:46 AM >> >> > >> To: Simon Glass; U-Boot Mailing List >> >> > >> Cc: Allen Martin; Albert Aribaud; Stephen Warren; Stephen Warren >> >> > >> Subject: RE: [PATCH v5 3/3] ARM: tegra: Add support for nyan-big >> >> > >> board >> >> > >> >> >> > >> Simon, >> >> > >> >> >> > >> > -----Original Message----- >> >> > >> > From: sjg(a)google.com [mailto:sjg@google.com] On Behalf Of >> >> > >> > Simon Glass >> >> > >> > Sent: Wednesday, December 10, 2014 8:01 AM >> >> > >> > To: U-Boot Mailing List >> >> > >> > Cc: Allen Martin; Simon Glass; Albert Aribaud; Tom Warren; >> >> > >> > Stephen Warren; Stephen Warren >> >> > >> > Subject: Re: [PATCH v5 3/3] ARM: tegra: Add support for >> >> > >> > nyan-big board >> >> > >> > >> >> > >> > Hi, >> >> > >> > >> >> > >> > On 4 December 2014 at 06:36, Simon Glass <sjg(a)chromium.org> >> wrote: >> >> > >> > > From: Allen Martin <amartin(a)nvidia.com> >> >> > >> > > >> >> > >> > > Nyan-big is a Tegra124 clamshell board that is very similar >> >> > >> > > to venice2, but it has a different panel, the sdcard cd and >> >> > >> > > wp sense are flipped, and it has a different revision of the AS3722 >> PMIC. >> >> > >> > > >> >> > >> > > This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, >> >> > >> > > NVIDIA Tegra K1, 2GB). The display is not currently >> >> > >> > > supported, so it should boot on other nyan-based Chromebooks >> >> > >> > > also, but only the device tree for nyan-big is provided here. >> >> > >> > > >> >> > >> > > The device tree file is from Linux but with features removed >> >> > >> > > which are unlikely to be supported in U-Boot soon >> >> > >> > > (regulators, >> >> > pinmux). >> >> > >> > > Also the addresses are updated to 32-bit. >> >> > >> > > >> >> > >> > > Signed-off-by: Allen Martin <amartin(a)nvidia.com> >> >> > >> > > Signed-off-by: Simon Glass <sjg(a)chromium.org> (rebase, >> >> > >> > > change to 'nyan-big', fix pinmux that resets nyan-big) >> >> > >> > > >> >> > >> > > --- >> >> > >> > > >> >> > >> > > Changes in v5: >> >> > >> > > - Remove call to pinmux_set_tristate_input_clamping() >> >> > >> > > >> >> > >> > >> >> > >> > Any further comments on v5 please? >> >> > >> > >> >> > >> > I would like to apply this patch before the DM I2C series, so >> >> > >> > that I2C works correct for nyan-big also. >> >> > >> > >> >> > >> > Tom are you looking at the rest of the PCI-e series? I resent >> >> > >> > it so would like to get that in soon - the patches originally >> >> > >> > date from August. >> >> > >> I was waiting for Thierry or Stephen to Ack the series, or >> >> > >> provide other feedback. I don't have time/boards to test this right >> now. >> >> > >> >> >> > >> If someone can say it looks good, or has been tested on X board, etc. >> >> > >> I can apply it. >> >> > >> >> >> > >> Tom >> >> > >> > >> >> > >> > Regards, >> >> > >> > Simon >> >> > >> -- >> >> > >> nvpublic

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[U-Boot] [PATCH v6 0/11] dm: Add I2C support and convert sandbox, tegra
by Simon Glass 11 Dec '14

11 Dec '14

This series adds I2C support to driver model. It has become apparent that this is a high priority as it is widely used. It follows along to some extent from the SPI conversion. Several changes are made from the original I2C implementations. Firstly it is not necessary to specify the chip address with every call, since each chip knows its own address - it is stored in struct dm_i2c_chip which is attached to each chip on the I2C bus. However, this information *is* passed to the driver since I presume most drivers need it and it would be cumbersome to look up in every call. Secondly there is no concept of a 'current' I2C bus so all associated logic is removed. With driver model i2c_set_bus_num() and i2c_get_bus_num() are not available. Since the chip device specifies both the bus and the chip address, there is no need for this concept. It also causes problems when one driver changes the current bus and forgets to change it back. Thirdly initialisation is handled by driver model's normal probe() method on each device so there should be no need for i2c_init_all(), i2c_init(), i2c_init_board(), i2c_board_late_init() and board_i2c_init(). I2C muxes are not yet supported. To support these we will need to maintain state of the current mux settings to avoid resetting every mux every time. Probably we need to add a sandbox I2C mux driver to permit testing of this. This can probably be done later. Platform data is not yet supported either, only device tree. The U_BOOT_I2C_MKENT_COMPLETE() and U_BOOT_I2C_ADAP_COMPLETE() macros are not used. Also struct i2c_adapter is not defined anymore. This will need to be addressed, perhaps as part of converting over a board that does not use device tree, assuming that we want to support this. The following I2C CONFIGs are no-longer needed when driver model is used: CONFIG_SYS_I2C_INIT_BOARD - each I2C bus is inited in its probe() method CONFIG_I2C_MULTI_BUS - we always support multi-bus with driver model CONFIG_SYS_MAX_I2C_BUS - the device tree aliases define available buses CONFIG_SYS_I2C_SPEED - the device tree specifies the speed for each bus CONFIG_SYS_I2C - this is the 'new old' API, now deprecated There are a few SPI patches included here due to a dependency on a new device binding function. v3 changes the uclass to driver interface significantly. It is now a list of messages to be processed by the driver. This matches the Linux user space API which may be a benefit. It does introduce one complication, which is that the protocol does not support separate chip offset and data. I have enhanced it to do so. This series is available at u-boot-dm/i2c-working2. Changes in v6: - Drop a stale comment - Drop the probe_chip() method which is not needed - Pass value from i2c_get_chip() to get_emul() - Use dm_scan_fdt_node() to find emulator Changes in v5: - Add a function comment for i2c_probe_chip() - Add an assert for offset_len in i2c_setup_offset() - Add more detail to return value comment on get_buf_speed() - Add more detail to return value comment on xfer() method - Adjust tests for DM_I2C_CHIP_RE_ADDRESS split - Fix -INVAL typo - Make i2c_get_bus_speed() independent of i2c_set_bus_speed() - Split DM_I2C_CHIP_RD_ADDRESS into read and write varaints - Update comments in struct i2c_msg to allow buf to be NULL - Use a NULL buffer in i2c_probe_chip() Changes in v4: - Add a constant for I2C_MAX_OFFSET_LEN - Add a probe_chip() method for the eeprom - Add a probe_chip() method to the uclass - Add a remove() method for the eeprom - Add an assert for non-null - Add an eeprom test mode - Add chip flags to i2c_probe() - Add comment to i2c_setup_offset() - Add comments to indicate which methods are optional - Add comments to set_bus_speed() method - Add eeprom debugging output - Add new patch to add newline to debug() messages - Add probe_chip() method - Add support for eeprom offset length - Add tests for offset length - Adjust i2c_bind_driver() to avoid calloc()/free() - Adjust tests to match uclass changes - Drop set_offset_len() method - Fix copying of chip flags to message in i2c_setup_offset() - Fix endianness of i2c_setup_offset() - Fix method comment for xfer() - Invert return value of i2c_setup_offset() - Probe with a message length of 0 - Rename i2c_generic_drv to i2c_generic_chip_drv - Rename i2c_read_bytewise() and implement a real one - Update call to i2c_probe() Changes in v3: - Add a helper to query chip flags - Add new 'i2c flags' command to get/set chip flags - Add support for reading a byte at a time with an address for each byte - Adjust for slightly altered I2C uclass API - Change driver to support new message-based I2C uclass API - Change uclass <=> driver API to use a message list - Correct bogus address len code (was confused with chip address length) - Drop extra call to i2c_bind_driver() in i2c_probe() - Update emulator for new uclass interface - Update for new uclass <=> driver interface - Update for new uclass <=> emulateor interface Changes in v2: - Add a 'deblock' method to recover an I2C bus stuck in mid-transaction - Add a helper function to find a chip on a particular bus number - Add a new asm/test.h header for tests in sandbox - Add a test for automatic binding of generic I2C devices - Add some debugging for generic I2C device binding - Adjust tegra_i2c_child_pre_probe() to permit generic I2C devices - Call the deblock() method for 'i2c reset' - Change alen to int so that it can be -1 (this was a bug) - Correct the compatible strings for I2C buses - Don't init if the speed is 0, since this breaks the controller - Expand coverage to all Tegra boards - Fix cihp typo - Implement generic I2C devices to allow 'i2c probe' on unknown devices - Return the probed device from i2c_probe() - Set the bus speed after the bus is probed - Update commit message for EEPROM driver Simon Glass (11): dm: i2c: Add a uclass for I2C dm: i2c: Implement driver model support in the i2c command dm: i2c: Add I2C emulation driver for sandbox dm: i2c: Add a sandbox I2C driver dm: i2c: Add an I2C EEPROM simulator dm: i2c: config: Enable I2C for sandbox using driver model dm: i2c: dts: Add an I2C bus for sandbox dm: Add a simple EEPROM driver dm: i2c: Add tests for I2C dm: device: Add newline to debug() messages dm: i2c: tegra: Convert to driver model arch/arm/cpu/tegra20-common/pmu.c | 21 +- arch/arm/dts/tegra124-jetson-tk1.dts | 1 - arch/arm/dts/tegra30-tec-ng.dts | 4 + arch/arm/include/asm/arch-tegra/tegra_i2c.h | 2 +- arch/sandbox/dts/sandbox.dts | 17 + arch/sandbox/include/asm/test.h | 26 ++ board/avionic-design/common/tamonten-ng.c | 12 +- board/nvidia/cardhu/cardhu.c | 13 +- board/nvidia/common/board.c | 4 - board/nvidia/dalmore/dalmore.c | 21 +- board/nvidia/whistler/whistler.c | 29 +- board/toradex/apalis_t30/apalis_t30.c | 19 +- common/cmd_i2c.c | 376 ++++++++++++++++++---- drivers/core/device.c | 6 +- drivers/i2c/Makefile | 2 + drivers/i2c/i2c-emul-uclass.c | 14 + drivers/i2c/i2c-uclass.c | 466 ++++++++++++++++++++++++++++ drivers/i2c/sandbox_i2c.c | 111 +++++++ drivers/i2c/tegra_i2c.c | 366 +++++++--------------- drivers/misc/Makefile | 4 + drivers/misc/i2c_eeprom.c | 51 +++ drivers/misc/i2c_eeprom_emul.c | 168 ++++++++++ drivers/power/tps6586x.c | 27 +- include/config_fallbacks.h | 6 + include/configs/apalis_t30.h | 3 - include/configs/beaver.h | 3 - include/configs/cardhu.h | 5 - include/configs/colibri_t30.h | 3 - include/configs/dalmore.h | 5 - include/configs/jetson-tk1.h | 5 - include/configs/nyan-big.h | 5 - include/configs/sandbox.h | 6 + include/configs/seaboard.h | 3 - include/configs/tec-ng.h | 5 - include/configs/tegra-common.h | 1 + include/configs/tegra114-common.h | 3 - include/configs/tegra124-common.h | 3 - include/configs/tegra20-common.h | 3 - include/configs/tegra30-common.h | 3 - include/configs/trimslice.h | 3 - include/configs/venice2.h | 5 - include/configs/whistler.h | 3 - include/dm/uclass-id.h | 4 + include/dm/ut.h | 12 + include/i2c.h | 352 +++++++++++++++++++++ include/i2c_eeprom.h | 19 ++ include/tps6586x.h | 4 +- test/dm/Makefile | 1 + test/dm/i2c.c | 216 +++++++++++++ test/dm/test.dts | 17 + 50 files changed, 2028 insertions(+), 430 deletions(-) create mode 100644 arch/sandbox/include/asm/test.h create mode 100644 drivers/i2c/i2c-emul-uclass.c create mode 100644 drivers/i2c/i2c-uclass.c create mode 100644 drivers/i2c/sandbox_i2c.c create mode 100644 drivers/misc/i2c_eeprom.c create mode 100644 drivers/misc/i2c_eeprom_emul.c create mode 100644 include/i2c_eeprom.h create mode 100644 test/dm/i2c.c -- 2.2.0.rc0.207.ga3a616c

3 26

[U-Boot] [PATCH] arm: socfpga: Add DT support for SoCFPGA
by Stefan Roese 11 Dec '14

11 Dec '14

This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for socfpga_cyclone5 to make use of this new DT support. Note that now the image to use is u-boot-dtb.img! Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Pavel Machek <pavel(a)denx.de> --- arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga.dtsi | 755 +++++++++++++++++++++++++++++++ arch/arm/dts/socfpga_cyclone5.dtsi | 51 +++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 90 ++++ configs/socfpga_cyclone5_defconfig | 2 + include/dt-bindings/reset/altr,rst-mgr.h | 90 ++++ 6 files changed, 990 insertions(+) create mode 100644 arch/arm/dts/socfpga.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c346063..a208ff7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -39,6 +39,8 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb +dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socdk.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi new file mode 100644 index 0000000..4472fd9 --- /dev/null +++ b/arch/arm/dts/socfpga.dtsi @@ -0,0 +1,755 @@ +/* + * Copyright (C) 2012 Altera <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/reset/altr,rst-mgr.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc@fffed000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffed000 0x1000>, + <0xfffec100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffe01000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffe01000 0x1000>; + interrupts = <0 104 4>, + <0 105 4>, + <0 106 4>, + <0 107 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + can0: can@ffc00000 { + compatible = "bosch,d_can"; + reg = <0xffc00000 0x1000>; + interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; + clocks = <&can0_clk>; + status = "disabled"; + }; + + can1: can@ffc01000 { + compatible = "bosch,d_can"; + reg = <0xffc01000 0x1000>; + interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; + clocks = <&can1_clk>; + status = "disabled"; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc2: osc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_periph_ref_clk: f2s_periph_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_sdram_ref_clk: f2s_sdram_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>; + reg = <0x40>; + + mpuclk: mpuclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe0 0 9>; + reg = <0x48>; + }; + + mainclk: mainclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe4 0 9>; + reg = <0x4C>; + }; + + dbg_base_clk: dbg_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe8 0 9>; + reg = <0x50>; + }; + + main_qspi_clk: main_qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x54>; + }; + + main_nand_sdmmc_clk: main_nand_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x58>; + }; + + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x5C>; + }; + }; + + periph_pll: periph_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; + reg = <0x80>; + + emac0_clk: emac0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x88>; + }; + + emac1_clk: emac1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x8C>; + }; + + per_qspi_clk: per_qsi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x90>; + }; + + per_nand_mmc_clk: per_nand_mmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x94>; + }; + + per_base_clk: per_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x98>; + }; + + h2f_usr1_clk: h2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x9C>; + }; + }; + + sdram_pll: sdram_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; + reg = <0xC0>; + + ddr_dqs_clk: ddr_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xC8>; + }; + + ddr_2x_dqs_clk: ddr_2x_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xCC>; + }; + + ddr_dq_clk: ddr_dq_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD0>; + }; + + h2f_usr2_clk: h2f_usr2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD4>; + }; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; + }; + + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; + }; + + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mainclk>; + fixed-divider = <1>; + }; + + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; + }; + + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; + }; + + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; + }; + + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; + }; + + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; + }; + + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; + }; + + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 8>; + }; + + h2f_user0_clk: h2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 9>; + }; + + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; + }; + + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; + }; + + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; + }; + + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; + }; + + h2f_user1_clk: h2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr1_clk>; + clk-gate = <0xa0 7>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; + clk-phase = <0 135>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; + }; + }; + }; + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac0_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + gmac1: ethernet@ff702000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 2>; + reg = <0xff702000 0x2000>; + interrupts = <0 120 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac1_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + gpio0: gpio@ff708000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff708000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 164 4>; + }; + }; + + gpio1: gpio@ff709000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff709000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 165 4>; + }; + }; + + gpio2: gpio@ff70a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff70a000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 166 4>; + }; + }; + + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + + L2: l2-cache@fffef000 { + compatible = "arm,pl310-cache"; + reg = <0xfffef000 0x1000>; + interrupts = <0 38 0x04>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <2 1 1>; + }; + + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + }; + + /* Local timer */ + timer@fffec600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfffec600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc08000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 167 4>; + reg = <0xffc08000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer1: timer1@ffc09000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 168 4>; + reg = <0xffc09000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 169 4>; + reg = <0xffd00000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + timer3: timer3@ffd01000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffd01000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x1000>; + interrupts = <0 162 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + uart1: serial1@ffc03000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc03000 0x1000>; + interrupts = <0 163 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 125 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 128 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd02000 { + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd03000 { + compatible = "snps,dw-wdt"; + reg = <0xffd03000 0x1000>; + interrupts = <0 172 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi new file mode 100644 index 0000000..28c05e7 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: dwmmc0@ff704000 { + num-slots = <1>; + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + }; + + ethernet@ff702000 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + status = "okay"; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts new file mode 100644 index 0000000..258865d --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Altera SOCFPGA Cyclone V SoC Development Kit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* this allow the ethaddr uboot environmnet variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&mmc0 { + cd-gpios = <&portb 18 0>; + vmmc-supply = <&regulator_3_3v>; + vqmmc-supply = <&regulator_3_3v>; +}; + +&usb1 { + status = "okay"; +}; diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 4b2ede4..2d3dd47 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -1,3 +1,5 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h new file mode 100644 index 0000000..3f04908 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar(a)pengutronix.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 +#define L2_RESET 4 + +/* PERMODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define USB0_RESET 34 +#define USB1_RESET 35 +#define NAND_RESET 36 +#define QSPI_RESET 37 +#define L4WD0_RESET 38 +#define L4WD1_RESET 39 +#define OSC1TIMER0_RESET 40 +#define OSC1TIMER1_RESET 41 +#define SPTIMER0_RESET 42 +#define SPTIMER1_RESET 43 +#define I2C0_RESET 44 +#define I2C1_RESET 45 +#define I2C2_RESET 46 +#define I2C3_RESET 47 +#define UART0_RESET 48 +#define UART1_RESET 49 +#define SPIM0_RESET 50 +#define SPIM1_RESET 51 +#define SPIS0_RESET 52 +#define SPIS1_RESET 53 +#define SDMMC_RESET 54 +#define CAN0_RESET 55 +#define CAN1_RESET 56 +#define GPIO0_RESET 57 +#define GPIO1_RESET 58 +#define GPIO2_RESET 59 +#define DMA_RESET 60 +#define SDR_RESET 61 + +/* PER2MODRST */ +#define DMAIF0_RESET 64 +#define DMAIF1_RESET 65 +#define DMAIF2_RESET 66 +#define DMAIF3_RESET 67 +#define DMAIF4_RESET 68 +#define DMAIF5_RESET 69 +#define DMAIF6_RESET 70 +#define DMAIF7_RESET 71 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 + +/* MISCMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +#define SYSMGR_RESET 130 +#define SYSMGRCOLD_RESET 131 +#define FPGAMGR_RESET 132 +#define ACPIDMAP_RESET 133 +#define S2F_RESET 134 +#define S2FCOLD_RESET 135 +#define NRSTPIN_RESET 136 +#define TIMESTAMPCOLD_RESET 137 +#define CLKMGRCOLD_RESET 138 +#define SCANMGR_RESET 139 +#define FRZCTRLCOLD_RESET 140 +#define SYSDBG_RESET 141 +#define DBG_RESET 142 +#define TAPCOLD_RESET 143 +#define SDRCOLD_RESET 144 + +#endif -- 2.1.3

2 4

[U-Boot] Controlling write protect pin on SPI flash
by Andy Pont 11 Dec '14

11 Dec '14

Hello, Is there, or is anyone working on, code for controlling the write protect pin of SPI flash devices using a GPIO? In effect an "sf protect <on|off>" command? I have had a look in 2014.07 which is on the platform we are using but can't see anything. Thanks, Andy.

1 0

[U-Boot] [PATCH v3] fastboot: handle flash write to GPT partitions
by Steve Rae 11 Dec '14

11 Dec '14

Implement a feature to allow fastboot to write the downloaded image to the space reserved for the Protective MBR and the Primary GUID Partition Table. Additionally, prepare and write the Backup GUID Partition Table. Signed-off-by: Steve Rae <srae(a)broadcom.com> --- Changes in v3: - prefer leXX_to_cpu() over cpu_to_leXX() - enhance calculation of pointer to GPT Entries - prepare and write the Backup GPT (requested by: Lukasz Majewski <l.majewski(a)samsung.com>) Changes in v2: add validation of the GPT before writing to flash (suggested by: Lukasz Majewski <l.majewski(a)samsung.com>) README | 9 +++++ common/fb_mmc.c | 26 ++++++++++++-- disk/part_efi.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/part.h | 20 +++++++++++ 4 files changed, 159 insertions(+), 3 deletions(-) diff --git a/README b/README index 4ca04d0..42ece99 100644 --- a/README +++ b/README @@ -1773,6 +1773,15 @@ The following options need to be configured: regarding the non-volatile storage device. Define this to the eMMC device that fastboot should use to store the image. + CONFIG_FASTBOOT_GPT_NAME + The fastboot "flash" command supports writing the downloaded + image to the Protective MBR and the Primary GUID Partition + Table. (Additionally, this downloaded image is post-processed + to generate and write the Backup GUID Partition Table.) + This occurs when the specified "partition name" on the + "fastboot flash" command line matches this value. + Default is GPT_ENTRY_NAME (currently "gpt") if undefined. + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV diff --git a/common/fb_mmc.c b/common/fb_mmc.c index fb06d8a..5acc8df 100644 --- a/common/fb_mmc.c +++ b/common/fb_mmc.c @@ -4,12 +4,17 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <config.h> #include <common.h> #include <fb_mmc.h> #include <part.h> #include <aboot.h> #include <sparse_format.h> +#ifndef CONFIG_FASTBOOT_GPT_NAME +#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME +#endif + /* The 64 defined bytes plus the '\0' */ #define RESPONSE_LEN (64 + 1) @@ -62,7 +67,6 @@ static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info, void fb_mmc_flash_write(const char *cmd, void *download_buffer, unsigned int download_bytes, char *response) { - int ret; block_dev_desc_t *dev_desc; disk_partition_t info; @@ -76,8 +80,24 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer, return; } - ret = get_partition_info_efi_by_name(dev_desc, cmd, &info); - if (ret) { + if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) { + printf("%s: updating MBR, Primary and Backup GPT(s)\n", + __func__); + if (is_valid_gpt_buf(download_buffer, dev_desc->blksz)) { + printf("%s: invalid GPT - refusing to write to flash\n", + __func__); + fastboot_fail("invalid GPT partition"); + return; + } + if (write_mbr_and_gpt_partitions(dev_desc, download_buffer)) { + printf("%s: writing GPT partitions failed\n", __func__); + fastboot_fail("writing GPT partitions failed"); + return; + } + printf("........ success\n"); + fastboot_okay(""); + return; + } else if (get_partition_info_efi_by_name(dev_desc, cmd, &info)) { error("cannot find partition: '%s'\n", cmd); fastboot_fail("cannot find partition"); return; diff --git a/disk/part_efi.c b/disk/part_efi.c index efed58f..9cc04da 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -455,6 +455,113 @@ err: free(gpt_h); return ret; } + +int is_valid_gpt_buf(void *buf, unsigned long blksz) +{ + int rc = 0; + gpt_header *gpt_h; + gpt_entry *gpt_e; + gpt_header gpt_hdr; + uint32_t calc_crc32; + + /* GPT Header starts at "LBA[1]" in the buffer */ + gpt_h = buf + blksz; + if (le64_to_cpu(gpt_h->signature) != GPT_HEADER_SIGNATURE) { + printf("%s: 'signature' is invalid\n", __func__); + return -1; + } + + memcpy(&gpt_hdr, gpt_h, sizeof(gpt_header)); + gpt_hdr.header_crc32 = 0; + calc_crc32 = efi_crc32((const unsigned char *)&gpt_hdr, + le32_to_cpu(gpt_h->header_size)); + if (le32_to_cpu(gpt_h->header_crc32) != calc_crc32) { + printf("%s: 'header_crc32' is invalid\n", __func__); + rc += 1; + } + + /* determine start of GPT Entries in the buffer */ + gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) * blksz); + calc_crc32 = efi_crc32((const unsigned char *)gpt_e, + le32_to_cpu(gpt_h->num_partition_entries) * + le32_to_cpu(gpt_h->sizeof_partition_entry)); + if (le32_to_cpu(gpt_h->partition_entry_array_crc32) != calc_crc32) { + printf("%s: 'partition_entry_array_crc32' is invalid\n", + __func__); + rc += 1; + } + return rc; +} + +int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf) +{ + gpt_header *gpt_h; + gpt_entry *gpt_e; + int gpt_e_blk_cnt; + uint32_t calc_crc32; + uint64_t val; + lbaint_t lba; + int cnt; + + if (is_valid_gpt_buf(buf, dev_desc->blksz)) + return -1; + + /* GPT Header starts at "LBA[1]" in the buffer */ + gpt_h = buf + dev_desc->blksz; + + /* determine start of GPT Entries in the buffer */ + gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) * + dev_desc->blksz); + gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) * + le32_to_cpu(gpt_h->sizeof_partition_entry)), + dev_desc); + + /* write MBR plus Primary GPT */ + lba = 0; /* MBR is always at 0 */ + cnt = 2; /* MBR + GPT Header (2 blocks) */ + if (dev_desc->block_write(dev_desc->dev, lba, cnt, buf) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "MBR + Primary GPT Header", cnt, lba); + return 1; + } + + lba = le64_to_cpu(gpt_h->partition_entry_lba); + cnt = gpt_e_blk_cnt; + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Primary GPT Entries", cnt, lba); + return 1; + } + + /* recalculate the values for the Backup GPT Header */ + val = le64_to_cpu(gpt_h->my_lba); + gpt_h->my_lba = gpt_h->alternate_lba; + gpt_h->alternate_lba = cpu_to_le64(val); + gpt_h->header_crc32 = 0; + + calc_crc32 = efi_crc32((const unsigned char *)gpt_h, + le32_to_cpu(gpt_h->header_size)); + gpt_h->header_crc32 = cpu_to_le32(calc_crc32); + + /* write Backup GPT */ + lba = le64_to_cpu(gpt_h->last_usable_lba) + 1; + cnt = gpt_e_blk_cnt; + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Backup GPT Entries", cnt, lba); + return 1; + } + + lba = le64_to_cpu(gpt_h->my_lba); + cnt = 1; /* GPT Header (1 block) */ + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Backup GPT Header", cnt, lba); + return 1; + } + + return 0; +} #endif /* diff --git a/include/part.h b/include/part.h index a496a4a..fee1c2d 100644 --- a/include/part.h +++ b/include/part.h @@ -244,6 +244,26 @@ int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h, */ int gpt_restore(block_dev_desc_t *dev_desc, char *str_disk_guid, disk_partition_t *partitions, const int parts_count); + +/** + * is_valid_gpt_buf() - Ensure that the Primary GPT information is valid + * + * @param buf - buffer which contains the MBR and Primary GPT info + * @param blksz - block size (in bytes) + * + * @return - '0' on success, otherwise error + */ +int is_valid_gpt_buf(void *buf, unsigned long blksz); + +/** + * write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT + * + * @param dev_desc - block device descriptor + * @param buf - buffer which contains the MBR and Primary GPT info + * + * @return - '0' on success, otherwise error + */ +int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf); #endif #endif /* _PART_H */ -- 1.8.5

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[U-Boot] [PATCH v2] fastboot: handle flash write to GPT partition
by Steve Rae 11 Dec '14

11 Dec '14

Implement a feature to allow fastboot to write the downloaded image to the space reserved for the Protective MBR and the Primary GUID Partition Table. Signed-off-by: Steve Rae <srae(a)broadcom.com> --- Changes in v2: add validation of the GPT before writing to flash (suggested by: Lukasz Majewski <l.majewski(a)samsung.com>) README | 7 +++++++ common/fb_mmc.c | 26 +++++++++++++++++++++++--- disk/part_efi.c | 37 +++++++++++++++++++++++++++++++++++++ include/part.h | 10 ++++++++++ 4 files changed, 77 insertions(+), 3 deletions(-) diff --git a/README b/README index 4ca04d0..5f50cdd 100644 --- a/README +++ b/README @@ -1773,6 +1773,13 @@ The following options need to be configured: regarding the non-volatile storage device. Define this to the eMMC device that fastboot should use to store the image. + CONFIG_FASTBOOT_GPT_NAME + The fastboot "flash" command supports writing the downloaded + image to the Protective MBR and the Primary GUID Partition + Table. This occurs when the specified "partition name" on the + "fastboot flash" command line matches this value. + Default is GPT_ENTRY_NAME (currently "gpt") if undefined. + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV diff --git a/common/fb_mmc.c b/common/fb_mmc.c index fb06d8a..a646a7b 100644 --- a/common/fb_mmc.c +++ b/common/fb_mmc.c @@ -4,12 +4,17 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <config.h> #include <common.h> #include <fb_mmc.h> #include <part.h> #include <aboot.h> #include <sparse_format.h> +#ifndef CONFIG_FASTBOOT_GPT_NAME +#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME +#endif + /* The 64 defined bytes plus the '\0' */ #define RESPONSE_LEN (64 + 1) @@ -62,9 +67,9 @@ static void write_raw_image(block_dev_desc_t *dev_desc, disk_partition_t *info, void fb_mmc_flash_write(const char *cmd, void *download_buffer, unsigned int download_bytes, char *response) { - int ret; block_dev_desc_t *dev_desc; disk_partition_t info; + lbaint_t blksz; /* initialize the response buffer */ response_str = response; @@ -76,8 +81,23 @@ void fb_mmc_flash_write(const char *cmd, void *download_buffer, return; } - ret = get_partition_info_efi_by_name(dev_desc, cmd, &info); - if (ret) { + if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) { + printf("%s: updating GUID Partition Table (including MBR)\n", + __func__); + /* start at Protective MBR */ + info.start = (GPT_PRIMARY_PARTITION_TABLE_LBA - 1); + blksz = dev_desc->blksz; + info.blksz = blksz; + /* assume that the Partition Entry Array starts in LBA 2 */ + info.size = (2 + (GPT_ENTRY_NUMBERS * GPT_ENTRY_SIZE) / blksz); + + if (is_valid_gpt_primary(download_buffer, dev_desc->blksz)) { + printf("%s: invalid GPT - refusing to write to flash\n", + __func__); + fastboot_fail("invalid GPT partition"); + return; + } + } else if (get_partition_info_efi_by_name(dev_desc, cmd, &info)) { error("cannot find partition: '%s'\n", cmd); fastboot_fail("cannot find partition"); return; diff --git a/disk/part_efi.c b/disk/part_efi.c index efed58f..86cb160 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -455,6 +455,43 @@ err: free(gpt_h); return ret; } + +int is_valid_gpt_primary(void *buf, unsigned long blksz) +{ + int rc = 0; + gpt_header *gpt_h; + gpt_entry *gpt_e; + gpt_header gpt_hdr; + uint32_t calc_crc32; + + /* GPT Header starts at "LBA[1]" in the buffer */ + gpt_h = buf + blksz; + if (gpt_h->signature != cpu_to_le64(GPT_HEADER_SIGNATURE)) { + printf("%s: 'signature' is invalid\n", __func__); + rc += 1; + } + + memcpy(&gpt_hdr, gpt_h, sizeof(gpt_header)); + gpt_hdr.header_crc32 = 0; + calc_crc32 = efi_crc32((const unsigned char *)&gpt_hdr, + le32_to_cpu(gpt_h->header_size)); + if (gpt_h->header_crc32 != cpu_to_le32(calc_crc32)) { + printf("%s: 'header_crc32' is invalid\n", __func__); + rc += 1; + } + + /* GPT Entries start at "LBA[2]" in the buffer */ + gpt_e = buf + (2 * blksz); + calc_crc32 = efi_crc32((const unsigned char *)gpt_e, + le32_to_cpu(gpt_h->num_partition_entries) * + le32_to_cpu(gpt_h->sizeof_partition_entry)); + if (gpt_h->partition_entry_array_crc32 != cpu_to_le32(calc_crc32)) { + printf("%s: 'partition_entry_array_crc32' is invalid\n", + __func__); + rc += 1; + } + return rc; +} #endif /* diff --git a/include/part.h b/include/part.h index a496a4a..9cfa4c9 100644 --- a/include/part.h +++ b/include/part.h @@ -244,6 +244,16 @@ int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h, */ int gpt_restore(block_dev_desc_t *dev_desc, char *str_disk_guid, disk_partition_t *partitions, const int parts_count); + +/** + * is_valid_gpt_primary() - Ensure that the Primary GPT information is valid + * + * @param buf - buffer which contains the Primary GPT info + * @param blksz - block size (in bytes) + * + * @return - '0' on success, otherwise error + */ +int is_valid_gpt_primary(void *buf, unsigned long blksz); #endif #endif /* _PART_H */ -- 1.8.5

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[U-Boot] [PATCH 1/2] usb, g_dnl: generalize DFU detach functions
by Rob Herring 11 Dec '14

11 Dec '14

From: Rob Herring <robh(a)kernel.org> In order to add detach functions for fastboot, make the DFU detach related functions common so they can be shared. Signed-off-by: Rob Herring <robh(a)kernel.org> --- common/cmd_dfu.c | 6 +++--- drivers/dfu/dfu.c | 16 ---------------- drivers/usb/gadget/f_dfu.c | 2 +- drivers/usb/gadget/g_dnl.c | 17 +++++++++++++++++ include/dfu.h | 3 --- include/g_dnl.h | 4 ++++ 6 files changed, 25 insertions(+), 23 deletions(-) diff --git a/common/cmd_dfu.c b/common/cmd_dfu.c index 9e020b4..e975abe 100644 --- a/common/cmd_dfu.c +++ b/common/cmd_dfu.c @@ -38,10 +38,10 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int controller_index = simple_strtoul(usb_controller, NULL, 0); board_usb_init(controller_index, USB_INIT_DEVICE); - dfu_clear_detach(); + g_dnl_clear_detach(); g_dnl_register("usb_dnl_dfu"); while (1) { - if (dfu_detach()) { + if (g_dnl_detach()) { /* * Check if USB bus reset is performed after detach, * which indicates that -R switch has been passed to @@ -74,7 +74,7 @@ done: if (dfu_reset) run_command("reset", 0); - dfu_clear_detach(); + g_dnl_clear_detach(); return ret; } diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index c0aba6e..a3e3ec5 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -17,7 +17,6 @@ #include <linux/list.h> #include <linux/compiler.h> -static bool dfu_detach_request; static LIST_HEAD(dfu_list); static int dfu_alt_num; static int alt_num_cnt; @@ -39,21 +38,6 @@ __weak bool dfu_usb_get_reset(void) return true; } -bool dfu_detach(void) -{ - return dfu_detach_request; -} - -void dfu_trigger_detach(void) -{ - dfu_detach_request = true; -} - -void dfu_clear_detach(void) -{ - dfu_detach_request = false; -} - static int dfu_find_alt_num(const char *s) { int i = 0; diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 16fc9dd..ead71eb 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -366,7 +366,7 @@ static int state_dfu_idle(struct f_dfu *f_dfu, to_runtime_mode(f_dfu); f_dfu->dfu_state = DFU_STATE_appIDLE; - dfu_trigger_detach(); + g_dnl_trigger_detach(); break; default: f_dfu->dfu_state = DFU_STATE_dfuERROR; diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index 25611ac..ee52a29 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -163,6 +163,23 @@ __weak int g_dnl_board_usb_cable_connected(void) return -EOPNOTSUPP; } +static bool g_dnl_detach_request; + +bool g_dnl_detach(void) +{ + return g_dnl_detach_request; +} + +void g_dnl_trigger_detach(void) +{ + g_dnl_detach_request = true; +} + +void g_dnl_clear_detach(void) +{ + g_dnl_detach_request = false; +} + static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev) { struct usb_gadget *gadget = cdev->gadget; diff --git a/include/dfu.h b/include/dfu.h index f1a71c7..c27856c 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -150,9 +150,6 @@ struct dfu_entity *dfu_get_entity(int alt); char *dfu_extract_token(char** e, int *n); void dfu_trigger_reset(void); int dfu_get_alt(char *name); -bool dfu_detach(void); -void dfu_trigger_detach(void); -void dfu_clear_detach(void); int dfu_init_env_entities(char *interface, char *devstr); unsigned char *dfu_get_buf(struct dfu_entity *dfu); unsigned char *dfu_free_buf(void); diff --git a/include/g_dnl.h b/include/g_dnl.h index 1b1b35e..4eeb5e4 100644 --- a/include/g_dnl.h +++ b/include/g_dnl.h @@ -39,4 +39,8 @@ int g_dnl_register(const char *s); void g_dnl_unregister(void); void g_dnl_set_serialnumber(char *); +bool g_dnl_detach(void); +void g_dnl_trigger_detach(void); +void g_dnl_clear_detach(void); + #endif /* __G_DOWNLOAD_H_ */ -- 2.1.0

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