November 2014 - U-Boot

[U-Boot] [PATCH 0/5] add usb support for mx6 board
by Peng Fan 03 Nov '14

03 Nov '14

Add usb support for mx6qarm2 mx6sabresd mx6sxsabresd mx6slevk. Mainly add pad settings and ehci power settings. Also introduce a new function to set IOMUXC GPR registers, because mx6sabresd usb needs that function to work. This patch set only contains board related settings for usb and a new gpr function. ehci_hcd_init and otg power polarity in ehci-mx6.c are not touched. Thus usb start can not work fine. As this is new feature support, post this patch set for review first. In future patch, related patch that maybe bugfix to make `usb start` fine will be sent out. Peng Fan (5): imx:mx6sxsabresd add usb support imx:mx6slevk add usb support arm:imx-common introduce a new function to set gpr imx:mx6qarm2 add usb support imx:mx6sabresd add usb support arch/arm/imx-common/iomux-v3.c | 25 ++++++++++++++ board/freescale/mx6qarm2/mx6qarm2.c | 27 +++++++++++++++ board/freescale/mx6sabresd/mx6sabresd.c | 53 +++++++++++++++++++++++++++++ board/freescale/mx6slevk/mx6slevk.c | 29 ++++++++++++++++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 29 ++++++++++++++++ include/configs/mx6qarm2.h | 14 ++++++++ include/configs/mx6sabresd.h | 14 ++++++++ include/configs/mx6slevk.h | 14 ++++++++ include/configs/mx6sxsabresd.h | 14 ++++++++ 9 files changed, 219 insertions(+) -- 1.8.4.5

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[U-Boot] [PATCH v2] arm, imx, spi: detect spi flash again on aristainetos board
by Heiko Schocher 03 Nov '14

03 Nov '14

155fa9af95a "spi: mxc: fix sf probe when using mxc_spi" break spi flash detection on the aristainetos board. Fix this. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- Changes in v2: - fix bus number board/aristainetos/aristainetos.c | 6 ++++++ include/configs/aristainetos.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 3bfcf5b..06922c0 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -230,6 +230,12 @@ static iomux_v3_cfg_t const backlight_pads[] = { MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) + ? (IMX_GPIO_NR(3, 20)) : -1; +} + static void setup_spi(void) { int i; diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h index 20aea85..e6a08df 100644 --- a/include/configs/aristainetos.h +++ b/include/configs/aristainetos.h @@ -77,7 +77,7 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 3 -#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 20)<<8)) +#define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN -- 1.8.3.1

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[U-Boot] [PATCH v3] imx: mx6 sabreauto: Add board support for USB EHCI
by Ye.Li 03 Nov '14

03 Nov '14

On mx6 sabreauto board, there are two USB ports: 0: OTG 1: HOST The EHCI driver is enabled for this board, but the IOMUX and VBUS power control is not implemented, which cause both USB port failed to work. This patch fix the problem by adding the board support codes. Since the power control uses the GPIO pin from port expander MAX7310, the PCA953X driver is enabled for accessing the MAX7310. The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting its daisy chain. Add a new function "imx_iomux_set_gpr_register" to handle GPR register setting. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes since v2: - Resolve syntax error and checkpatch warning Changes since v1: - Modify codes and patch message according with Fabio's comments. arch/arm/imx-common/iomux-v3.c | 15 ++++ arch/arm/include/asm/imx-common/iomux-v3.h | 5 ++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 93 +++++++++++++++++++++++++ include/configs/mx6qsabreauto.h | 3 + 4 files changed, 116 insertions(+), 0 deletions(-) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 22cd11a..e88e6e2 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -77,3 +77,18 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, p += stride; } } + +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value) +{ + int i = 0; + u32 reg; + reg = readl(base + group * 4); + while (num_bits) { + reg &= ~(1<<(start_bit + i)); + i++; + num_bits--; + } + reg |= (value << start_bit); + writel(reg, base + group * 4); +} diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index a8ca49c..e0a49be 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -182,6 +182,11 @@ typedef u64 iomux_v3_cfg_t; void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count); +/* +* Set bits for general purpose registers +*/ +void imx_iomux_set_gpr_register(int group, int start_bit, + int num_bits, int value); /* macros for declaring and using pinmux array */ #if defined(CONFIG_MX6QDL) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 0dc0160..42ae6fa 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -27,6 +27,7 @@ #include <asm/arch/mxc_hdmi.h> #include <asm/imx-common/video.h> #include <asm/arch/crm_regs.h> +#include <pca953x.h> DECLARE_GLOBAL_DATA_PTR; @@ -116,6 +117,44 @@ static iomux_v3_cfg_t const port_exp[] = { MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +/*Define for building port exp gpio, pin starts from 0*/ +#define PORTEXP_IO_NR(chip, pin) \ + ((chip << 5) + pin) + +/*Get the chip addr from a ioexp gpio*/ +#define PORTEXP_IO_TO_CHIP(gpio_nr) \ + (gpio_nr >> 5) + +/*Get the pin number from a ioexp gpio*/ +#define PORTEXP_IO_TO_PIN(gpio_nr) \ + (gpio_nr & 0x1f) + +static int port_exp_direction_output(unsigned gpio, int value) +{ + int ret; + + i2c_set_bus_num(2); + ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio)); + if (ret) + return ret; + + ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio))); + + if (ret) + return ret; + + ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio), + (1 << PORTEXP_IO_TO_PIN(gpio)), + (value << PORTEXP_IO_TO_PIN(gpio))); + + if (ret) + return ret; + + return 0; +} + static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); @@ -361,3 +400,57 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7) +#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1) + +iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + if (on) + port_exp_direction_output(USB_OTG_PWR, 1); + else + port_exp_direction_output(USB_OTG_PWR, 0); + break; + case 1: + if (on) + port_exp_direction_output(USB_HOST1_PWR, 1); + else + port_exp_direction_output(USB_HOST1_PWR, 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} +#endif diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 0ab3127..235dd6d 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -32,6 +32,9 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } + #include "mx6sabre_common.h" #define CONFIG_SYS_FSL_USDHC_NUM 2 -- 1.7.4.1

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[U-Boot] [PATCH v3 1/2] imx: mx6sl: Add IOMUX setting for USDHC1-3
by Ye.Li 03 Nov '14

03 Nov '14

Set the USDHC1-3 IOMUX settings which are used for mx6slevk board. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes since v2: - None Changes since v1: - None arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 045ccc4..d9db58c 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -14,12 +14,31 @@ enum { MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0), MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0), MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), -- 1.7.4.1

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[U-Boot] [PATCH v2] imximage: Fix the bootdata.size calculation
by Ye.Li 03 Nov '14

03 Nov '14

In system boot chapter of i.MX6 reference manual, the "Image Vector Table" figure shows the bootdata.start points to the beginning of the destination memory. It means the bootdata.size should contain the IVT offset part, but the calculation in imximage tool does not have. We found this issue when booting from QuadSPI NOR on i.MX6SX. The u-boot runs into abnormal (crash or stop) after booting. After checked the destination memory where the image is loaded to, there are hundreds of bytes at the image end are not loaded into memory. Since there is a 4096 bytes round in the calculation, for the booting devices using smaller IVT offset, such as SD and SPI booting, they are not easy to reproduce. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes since v1: - Improve the patch message to explicate the issue and reason. tools/imximage.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tools/imximage.c b/tools/imximage.c index faba238..526b7d4 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -587,7 +587,7 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, * * The remaining fraction of a block bytes would not be loaded! */ - *header_size_ptr = ROUND(sbuf->st_size, 4096); + *header_size_ptr = ROUND((sbuf->st_size + imximage_ivt_offset), 4096); if (csf_ptr && imximage_csf_size) { *csf_ptr = params->ep - imximage_init_loadsize + -- 1.7.4.1

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[U-Boot] [PATCH v3 1/5] imx: gpt: Add High frequency clock source support for GPT
by Ye.Li 03 Nov '14

03 Nov '14

Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set, the GPT will select a high frequency clock as clock source. Otherwise, the GPT will stay to use 32Khz OSC as clock source. In the implementation, since only the GPT on i.MX6 series provide the clock source option for 24Mhz OSC. For others (only i.MX5 and i.MX6 compile the driver), if the configuration is set, the perclk will be selected as clock source. MX6Q/D Rev 1.0 and MX6SL are special in the implementation, because they don't have the 24Mhz OSC clock source option, so also select the perclk for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so eventually the clock comes from OSC 24Mhz. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- Changes since v2: - Resolve the checkpatch warnings Changes since v1: - Modify the patch message content to clear the implementation. - Remove the change for copyright date. arch/arm/imx-common/timer.c | 75 +++++++++++++++++++++++++++++++++++++----- 1 files changed, 66 insertions(+), 9 deletions(-) diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index c63f78f..2af9f34 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -12,6 +12,7 @@ #include <div64.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> /* General purpose timers registers */ struct mxc_gpt { @@ -26,23 +27,60 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; /* General purpose timers bitfields */ #define GPTCR_SWR (1 << 15) /* Software reset */ +#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */ #define GPTCR_FRR (1 << 9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */ +#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */ +#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */ +#define GPTCR_CLKSOURCE_MASK (0x7 << 6) #define GPTCR_TEN 1 /* Timer enable */ +#define GPTPR_PRESCALER24M_SHIFT 12 +#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT) + DECLARE_GLOBAL_DATA_PTR; +static inline int gpt_has_clk_source_osc(void) +{ +#if defined(CONFIG_MX6) + if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + && (is_soc_rev(CHIP_REV_1_0) > 0)) + || is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO) + || is_cpu_type(MXC_CPU_MX6SX)) + return 1; + + return 0; +#else + return 0; +#endif +} + +static inline ulong gpt_get_clk(void) +{ +#ifdef CONFIG_MXC_GPT_HCLK + if (gpt_has_clk_source_osc()) + return MXC_HCLK >> 3; + else + return mxc_get_clock(MXC_IPG_PERCLK); +#else + return MXC_CLK32; +#endif +} static inline unsigned long long tick_to_time(unsigned long long tick) { + ulong gpt_clk = gpt_get_clk(); + tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); + do_div(tick, gpt_clk); return tick; } static inline unsigned long long us_to_tick(unsigned long long usec) { - usec = usec * MXC_CLK32 + 999999; + ulong gpt_clk = gpt_get_clk(); + + usec = usec * gpt_clk + 999999; do_div(usec, 1000000); return usec; @@ -59,11 +97,30 @@ int timer_init(void) for (i = 0; i < 100; i++) __raw_writel(0, &cur_gpt->control); - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ - - /* Freerun Mode, PERCLK1 input */ i = __raw_readl(&cur_gpt->control); - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); + i &= ~GPTCR_CLKSOURCE_MASK; + +#ifdef CONFIG_MXC_GPT_HCLK + if (gpt_has_clk_source_osc()) { + i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; + + /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */ + if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO) + || is_cpu_type(MXC_CPU_MX6SX)) { + i |= GPTCR_24MEN; + + /* Produce 3Mhz clock */ + __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT), + &cur_gpt->prescaler); + } + } else { + i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN; + } +#else + __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ + i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; +#endif + __raw_writel(i, &cur_gpt->control); gd->arch.tbl = __raw_readl(&cur_gpt->counter); gd->arch.tbu = 0; @@ -86,7 +143,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -117,5 +174,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return MXC_CLK32; + return gpt_get_clk(); } -- 1.7.4.1

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[U-Boot] [PATCH 1/2] imx:mx6sl_pins add pad settings for usb
by Peng Fan 03 Nov '14

03 Nov '14

Add pad settings for usb support. This patch "imx:mx6slevk add usb support" missed to add pad definition. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 045ccc4..17b4798 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -34,5 +34,10 @@ enum { MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ -- 1.8.4.5

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[U-Boot] Need FTP client support in U-Boot
by Mythri, Madhukar (Artesyn) 03 Nov '14

03 Nov '14

Hi, I'm a newbie to U-boot(familiar with Linux). We are looking for FTP client command in U-boot commands, So that, we can boot the O.S kernel-image through ftp-client(instead of tftpboot over network). Why doesn't the U-boot support FTP client ? Can we implement/add the FTP client protocol code to U-boot sources and customize. if so, how much work activity involved in this ? Is this just need to write a small ftp-client program file by using TCP stream sockets (as like in Linux) ? Or do we need to write up anything more like TCP/IP network stack.. Please give some suggestion on this. Thanks, Madhu.

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[U-Boot] [PATCH v3 0/2] mmc: Board-specific MMC power initializations
by Paul Kocialkowski 03 Nov '14

03 Nov '14

Changelog: v3: Changes to make v2 apply on master v2: Implement board_mmc_power_init instead of define

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[U-Boot] [PATCH] drivers/i2c/fsl_i2c: Change CONFIG_I2C_TIMEOUT to 100ms
by Shaveta Leekha 03 Nov '14

03 Nov '14

Some slow I2C devices like Power Monitor(ZM7304) at times do not work well with low timeout value, so I2C bus get stuck during read cycle with this device, changing it to 100ms from 10ms works fine A lot of other i2c drivers like mxc and i2c drivers of BOOTROM also use relax timeouts to give sufficient ticks to work well with slower devices Signed-off-by: Shaveta Leekha <shaveta(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> --- drivers/i2c/fsl_i2c.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 811033b..7bb1702 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -38,7 +38,7 @@ * generic value. */ #ifndef CONFIG_I2C_TIMEOUT -#define CONFIG_I2C_TIMEOUT 10000 +#define CONFIG_I2C_TIMEOUT 100000 #endif #define I2C_READ_BIT 1 -- 1.7.6.GIT

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