October 2014 - U-Boot

[U-Boot] [PATCH 0/2] e1000: add i210 support
by Tim Harvey 04 Oct '14

04 Oct '14

Two patches to add Intel i210 support to the e1000 driver. Marek Vasut (2): e1000: Implement dcache support e1000: add i210 support drivers/net/e1000.c | 266 ++++++++++++++++++++++++++++++++++++++++++---------- drivers/net/e1000.h | 12 +++ include/pci_ids.h | 7 ++ 3 files changed, 236 insertions(+), 49 deletions(-) -- 1.8.3.2

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[U-Boot] [PATCH] mmc: Tegra: Fix timeout issue seen on certain eMMC parts
by Marcel Ziswiler 04 Oct '14

04 Oct '14

During rigorous testing of our latest update infrastructure I came across quite consistent timeouts on certain eMMC parts (e.g. Hynix H26M21001ECR) when writing big (e.g. in excess of 400 MB) file system images: MMC write: dev # 0, block # 40960, count 944128 ... mmc_send_cmd_bounced: MMC Timeout Interrupt status 0x00000001 Interrupt status enable 0xdfff003b Interrupt signal enable 0xdfff0002 Present status 0x01870106 mmc write failed Comparing the various data sheets I came across the following timeout specification: Secure Erase/TRIM Timeout=300ms*2*10=6000ms Unfortunately empirical testing still failed albeit much more rarely. Increasing the timeout to 8000ms made it finally disappear entirely. This patch allows us writing various eMMC parts without seeing any further issues. Signed-off-by: Marcel Ziswiler <marcel(a)ziswiler.com> --- drivers/mmc/tegra_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index ca9c4aa..2642fe2 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -292,7 +292,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, /* Transfer Complete */ debug("r/w is done\n"); break; - } else if (get_timer(start) > 2000UL) { + } else if (get_timer(start) > 8000UL) { writel(mask, &host->reg->norintsts); printf("%s: MMC Timeout\n" " Interrupt status 0x%08x\n" -- 1.9.3

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[U-Boot] [PATCH v3 00/10] ARM: sunxi: Add basic support for Allwinner A31 (sun6i)
by Chen-Yu Tsai 03 Oct '14

03 Oct '14

Hi everyone, This is v3 of the A31 support series. This series add basic (UART and MMC) support for Allwinner's A31 SoC. The patches, excluding the first one, were cherry-picked from u-boot-sunxi. Due to the difference between u-boot mainline and u-boot-sunxi, some patches were rearranged or squashed to better fit the current state of u-boot, and not introduce any build breaks. It follows Ian's initial merge method of sun7i support: introducing various components first, then enabling them in the last commit. I tried to keep the commits separate, thus retaining the original author and Signed-off-bys. Patch 1 updates the current UART pinmuxing code to use macros for pull-up values. This is for existing platforms, but is included as it would conflict with patch 7. Patch 2 adds a wrapper around "func(USB, usb, 0)" in BOOT_TARGET_DEVICES to deal with breakage when USB support is not enabled. Patch 3 adds memory addresses for some hardware blocks new in sun6i. Patch 4 adds support for the new PRCM (power reset and clock management) block, which also contains PLL bias voltage control. Patch 5 adds support for the clock module. This patch is a bunch of different sun6i related patches on the clock code, from when sun6i support was introduced to u-boot-sunxi, up to its current form. This is done to avoid various conflicts and needlessly introducing then removing macros. Patch 6 adds mmc support on sun6i. Patch 7 adds uart0 pin macros. Patch 8 adds uart0 muxing on sun6i. Patch 9 enables sun6i support. Patch 10 adds a defconfig for the Colombus board, which is an A31 evaluation board. Changes since v2: - Added Maxime Ripard as maintainer of Colombus board Changes since v1: - Added macros for sun6i uart pinmuxes (patch 7) - Use gpio macros when muxing uarts (patch 1, 8) - Clarify what is enabled in PRCM (patch 4) - Dropped old comments in commit message from Hans (patch 4) - Use setbits helpers in PRCM code (patch 4) - Drop SPL code block from clock code (patch 5) - Make mmc code use fifo in register structure definition, and add reserved area to adjust for sun6i's different fifo address (patch 6) - Rewrite patch 9 commit message to reflect what is supported - Split out Colombus board defconfig into separate patch (patch 10) Cheers ChenYu Chen-Yu Tsai (5): ARM: sunxi: Use macro values for setting UART GPIO pull-ups ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined ARM: sun6i: Add clock support ARM: sun6i: Define UART0 pins for A31 ARM: sun6i: Add Colombus board defconfig Hans de Goede (1): ARM: sunxi-mmc: Add mmc support for sun6i / A31 Maxime Ripard (2): ARM: sun6i: Setup the A31 UART0 muxing ARM: sunxi: Add basic A31 support Oliver Schinagl (2): ARM: sun6i: Add base address for the new controllers in A31 ARM: sun6i: Add support for the power reset control module found on the A31 arch/arm/Kconfig | 3 + arch/arm/cpu/armv7/sunxi/Makefile | 2 + arch/arm/cpu/armv7/sunxi/board.c | 10 +- arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 70 ++++++++ arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 + arch/arm/cpu/armv7/sunxi/prcm.c | 33 ++++ arch/arm/include/asm/arch-sunxi/clock.h | 4 + arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 205 ++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 9 + arch/arm/include/asm/arch-sunxi/gpio.h | 3 + arch/arm/include/asm/arch-sunxi/mmc.h | 5 +- arch/arm/include/asm/arch-sunxi/prcm.h | 238 ++++++++++++++++++++++++++ board/sunxi/Kconfig | 10 +- board/sunxi/MAINTAINERS | 5 + configs/Colombus_defconfig | 4 + drivers/mmc/sunxi_mmc.c | 11 +- include/configs/sun6i.h | 26 +++ include/configs/sunxi-common.h | 8 +- 18 files changed, 638 insertions(+), 10 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun6i.c create mode 100644 arch/arm/cpu/armv7/sunxi/prcm.c create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun6i.h create mode 100644 arch/arm/include/asm/arch-sunxi/prcm.h create mode 100644 configs/Colombus_defconfig create mode 100644 include/configs/sun6i.h -- 2.1.1

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[U-Boot] Seeing only 256MB of RAM
by John Tobias 03 Oct '14

03 Oct '14

Hi All, I have an iMX6SL custom board with two 512 MB (CS0 and CS1) of DDR3. The two DDR are working fine and the kernel could see it 1GB. I need to disable the CS1 to work my device with 512MB at the same time to see the performance of my system. I used the MX6SL_MMDC_DDR3_register programming v0.5 to disable the CS1. Here are the summary of the new settings: // Manufacturer: Micron // Clock Freq.: 400MHz // Density per CS in Gb: 4 // Chip Selects used: 1 // Total DRAM density (Gb) 4 // Number of Banks: 8 // Row address: 14 // Column address: 10 // Data bus width 16 In my u-boot config file, I changed default value of PHYS_SDRAM_SIZE from SZ_1GB to SZ_512M The problem right now is that the kernel only seeing 256M instead of 512M. I would like to know if I am missing something on my configuration?. Regards, John

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[U-Boot] [PATCH] ARM: tegra: Use mem size from MC in combination with get_ram_size()
by Marcel Ziswiler 03 Oct '14

03 Oct '14

On popular request this now completes the Warren's work started for TK1: aeb3fcb35956461077804720b8a252d50758d7e0 In addition to the move of using the Tegra memory controller (MC) register rather than ODMDATA for T20, T30 and T114 as well it further uses the generic get_ram_size() function (see "common/memsize.c") <supposed to be used in each and every U-Boot port>TM. Added benefit is that it should <catch 99% of hardware related (i. e. reliably reproducible) memory errors> as well. Thoroughly tested on the various Toradex line of Tegra modules available which unfortunately does not include T114 and T124 (yet at least) plus on the Jetson TK1. Based-on-work-by: Stephen Warren <swarren(a)nvidia.com> Based-on-work-by: Tom Warren <twarren(a)nvidia.com> Signed-off-by: Marcel Ziswiler <marcel(a)ziswiler.com> --- arch/arm/cpu/tegra-common/board.c | 64 ++++++------------------------ arch/arm/include/asm/arch-tegra114/mc.h | 37 +++++++++++++++++ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra20/mc.h | 36 +++++++++++++++++ arch/arm/include/asm/arch-tegra20/tegra.h | 1 + arch/arm/include/asm/arch-tegra30/mc.h | 38 ++++++++++++++++++ arch/arm/include/asm/arch-tegra30/tegra.h | 1 + 7 files changed, 127 insertions(+), 51 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra114/mc.h create mode 100644 arch/arm/include/asm/arch-tegra20/mc.h create mode 100644 arch/arm/include/asm/arch-tegra30/mc.h diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c index 433da09..a313061 100644 --- a/arch/arm/cpu/tegra-common/board.c +++ b/arch/arm/cpu/tegra-common/board.c @@ -9,6 +9,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> +#include <asm/arch/mc.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/pmc.h> @@ -27,55 +28,6 @@ enum { UART_COUNT = 5, }; -#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ - defined(CONFIG_TEGRA114) -/* - * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0, - * so we are using this value to identify memory size. - */ -unsigned int query_sdram_size(void) -{ - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; - u32 reg; - - reg = readl(&pmc->pmc_scratch20); - debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg); - -#if defined(CONFIG_TEGRA20) - /* bits 30:28 in OdmData are used for RAM size on T20 */ - reg &= 0x70000000; - - switch ((reg) >> 28) { - case 1: - return 0x10000000; /* 256 MB */ - case 0: - case 2: - default: - return 0x20000000; /* 512 MB */ - case 3: - return 0x40000000; /* 1GB */ - } -#else /* Tegra30/Tegra114 */ - /* bits 31:28 in OdmData are used for RAM size on T30 */ - switch ((reg) >> 28) { - case 0: - case 1: - default: - return 0x10000000; /* 256 MB */ - case 2: - return 0x20000000; /* 512 MB */ - case 3: - return 0x30000000; /* 768 MB */ - case 4: - return 0x40000000; /* 1GB */ - case 8: - return 0x7ff00000; /* 2GB - 1MB */ - } -#endif -} -#else -#include <asm/arch/mc.h> - /* Read the RAM size directly from the memory controller */ unsigned int query_sdram_size(void) { @@ -83,12 +35,22 @@ unsigned int query_sdram_size(void) u32 size_mb; size_mb = readl(&mc->mc_emem_cfg); +#if defined(CONFIG_TEGRA20) + debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb); + size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024); +#else debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb); + size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024); +#endif - return size_mb * 1024 * 1024; -} +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) + /* External memory limited to 2047 MB due to IROM/HI-VEC */ + if (size_mb == 0x80000000) size_mb -= 0x100000; #endif + return size_mb; +} + int dram_init(void) { /* We do not initialise DRAM here. We just query the size */ diff --git a/arch/arm/include/asm/arch-tegra114/mc.h b/arch/arm/include/asm/arch-tegra114/mc.h new file mode 100644 index 0000000..044b1e0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/mc.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA114_MC_H_ +#define _TEGRA114_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA114_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index 5d426b5..c3d061e 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -19,6 +19,7 @@ #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 #include <asm/arch-tegra/tegra.h> diff --git a/arch/arm/include/asm/arch-tegra20/mc.h b/arch/arm/include/asm/arch-tegra20/mc.h new file mode 100644 index 0000000..9c6e3ff --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/mc.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA20_MC_H_ +#define _TEGRA20_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[3]; /* offset 0x00 - 0x08 */ + u32 mc_emem_cfg; /* offset 0x0C */ + u32 mc_emem_adr_cfg; /* offset 0x10 */ + u32 mc_emem_arb_cfg0; /* offset 0x14 */ + u32 mc_emem_arb_cfg1; /* offset 0x18 */ + u32 mc_emem_arb_cfg2; /* offset 0x1C */ + u32 reserved1; /* offset 0x20 */ + u32 mc_gart_cfg; /* offset 0x24 */ + u32 mc_gart_entry_addr; /* offset 0x28 */ + u32 mc_gart_entry_data; /* offset 0x2C */ + u32 mc_gart_error_req; /* offset 0x30 */ + u32 mc_gart_error_addr; /* offset 0x34 */ + u32 reserved2; /* offset 0x38 */ + u32 mc_timeout_ctrl; /* offset 0x3C */ + u32 reserved3[6]; /* offset 0x40 - 0x54 */ + u32 mc_decerr_emem_others_status; /* offset 0x58 */ + u32 mc_decerr_emem_others_adr; /* offset 0x5C */ + u32 reserved4[40]; /* offset 0x60 - 0xFC */ + u32 reserved5[93]; /* offset 0x100 - 0x270 */ +}; + +#endif /* _TEGRA20_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h index 18856ac..22774ab 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ b/arch/arm/include/asm/arch-tegra20/tegra.h @@ -9,6 +9,7 @@ #define _TEGRA20_H_ #define NV_PA_SDRAM_BASE 0x00000000 +#define NV_PA_MC_BASE 0x7000F000 #include <asm/arch-tegra/tegra.h> diff --git a/arch/arm/include/asm/arch-tegra30/mc.h b/arch/arm/include/asm/arch-tegra30/mc.h new file mode 100644 index 0000000..242a1fc --- /dev/null +++ b/arch/arm/include/asm/arch-tegra30/mc.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA30_MC_H_ +#define _TEGRA30_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 mc_smmu_asid_security; /* offset 0x38 */ + u32 reserved2[5]; /* offset 0x3C - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA30_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index c02c5d8..9367179 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -17,6 +17,7 @@ #ifndef _TEGRA30_H_ #define _TEGRA30_H_ +#define NV_PA_MC_BASE 0x7000F000 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ #include <asm/arch-tegra/tegra.h> -- 1.9.3

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[U-Boot] iMX6 Device Tree: status of CONFIG_OF_CONTROL
by Luca Ellero 03 Oct '14

03 Oct '14

Hi, I'm about to start the porting of U-Boot on a custom board based on iMX6 (close to SabreSD). My questions are: 1) should I use device tree or use the "old" way (cloning directory and make modifications)? 2) How is the status of CONFIG_OF_CONTROL on u-boot in general (and in particular on iMX6)? Thank you Regards Luca ---- Luca Ellero http://www.brickedbrain.com

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[U-Boot] [PATCH] cmd_mmc: fix bootpart-resize maxarg to 4
by Wally Yeh 03 Oct '14

03 Oct '14

sub-command 'bootpart-resize' check for argc == 4, it will retrun CMD_RET_FAILURE when argc value not matched. but bootpart-resize's maxarg is 3, which means you never execute this sub-command successfully. fix it by change bootpart-resize maxarg to 4. Signed-off-by: wally.yeh <wally.yeh(a)atrustcorp.com> --- common/cmd_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 1e40983..4286e26 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -602,7 +602,7 @@ static cmd_tbl_t cmd_mmc[] = { U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""), #ifdef CONFIG_SUPPORT_EMMC_BOOT U_BOOT_CMD_MKENT(bootbus, 5, 0, do_mmc_bootbus, "", ""), - U_BOOT_CMD_MKENT(bootpart-resize, 3, 0, do_mmc_boot_resize, "", ""), + U_BOOT_CMD_MKENT(bootpart-resize, 4, 0, do_mmc_boot_resize, "", ""), U_BOOT_CMD_MKENT(partconf, 5, 0, do_mmc_partconf, "", ""), U_BOOT_CMD_MKENT(rst-function, 3, 0, do_mmc_rst_func, "", ""), #endif -- 1.7.10.4

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[U-Boot] [PATCH] make mxsldr behave like sb_loader.exe
by Jacob Kjaergaard 03 Oct '14

03 Oct '14

Hi, I have made a patch to mxsldr to be able to boot non-u-boot bootstreams (linux and barebox) as well as u-boot bootstreams. I added an option to send one last BLTS command after uploading the firmware. This is tested with bootstreams that work with sb_loader.exe in windows as well. Jacob Kjaergaard (1): add option to send a last interrupt transfer. mxsldr.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] sunxi: Add support for the Mele M3 board
by Hans de Goede 03 Oct '14

03 Oct '14

The Mele M3 is yet another Allwinnner based Android top set box from Mele. It uses a housing similar to the A2000, but without the USM sata storage slot at the top. It features an A20 SoC, 1G RAM, 4G eMMC (unique for Allwinner devices), 100Mbit ethernet, HDMI out, 3 USB A receptacles, VGA, and A/V OUT connections. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- board/sunxi/MAINTAINERS | 1 + board/sunxi/Makefile | 1 + configs/Mele_M3_defconfig | 5 +++++ 3 files changed, 7 insertions(+) create mode 100644 configs/Mele_M3_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 4ed82cf..6c4226e 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -8,6 +8,7 @@ F: configs/ba10_tv_box_defconfig F: configs/Cubieboard_defconfig F: configs/Mele_A1000_defconfig F: configs/Mele_A1000G_defconfig +F: configs/Mele_M3_defconfig F: configs/Mini-X_defconfig F: configs/Mini-X-1Gb_defconfig F: include/configs/sun5i.h diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index d63a6d2..6a2e4c9 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o obj-$(CONFIG_I12_TVBOX) += dram_sun7i_384_1024_iow16.o obj-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o obj-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o +obj-$(CONFIG_MELE_M3) += dram_sun7i_384_1024_iow16.o obj-$(CONFIG_MINI_X) += dram_sun4i_360_512.o obj-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o obj-$(CONFIG_PCDUINO3) += dram_linksprite_pcduino3.o diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig new file mode 100644 index 0000000..645b236 --- /dev/null +++ b/configs/Mele_M3_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="MELE_M3,AXP209_POWER,SUNXI_GMAC,USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-m3.dtb" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SUN7I=y -- 2.1.0

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[U-Boot] U-boot for samsung peach-pi (chromebook 2 13")
by Sjoerd Simons 03 Oct '14

03 Oct '14

Hey, While giving upstream u-boot a go on my Chromebook(s), I noticed that while the peach pit is support the peach pi is not. Are there any plans for supporting that board as well? -- Sjoerd Simons <sjoerd.simons(a)collabora.co.uk> Collabora Ltd.

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