January 2014 - U-Boot

[U-Boot] [PATCH 0/7] common, fit, rsa: enhancements
by Heiko Schocher 14 Feb '14

14 Feb '14

- add sha256,rsa2048 and sha256,rsa4098 support to u-boot. - add "fdt sign" command to u-boot cmdshell. This command checks, if a fdt is correct signed. - add hosttool "fit_info" which prints the offset and the len of a property from in a fdt file. This values can be used, to extract the data from a property (for example with "dd") - add hosttool "fit_check_sign". This does the same as the u-boot cmdshell tool "fdt sign". It checks, if fit image is correct signed Heiko Schocher (7): tools/image-host: fix sign-images bug fdt: add "fdt sign" command fit: add sha256 support rsa: add sha256-rsa2048 algorithm rsa: add sha256,rsa4096 algorithm tools, fit: add fit_info host command tools, fit_check_sign: verify a signed fit image Makefile | 2 + common/cmd_fdt.c | 38 +++++++++++- common/image-fit.c | 5 ++ common/image-sig.c | 66 ++++++++++++++++++++ include/fdt_support.h | 5 ++ include/image.h | 37 ++++++++++- include/rsa-checksum.h | 26 ++++++++ include/rsa.h | 35 +++++++++++ lib/libfdt/fdt_wip.c | 17 ++++++ lib/rsa/Makefile | 2 +- lib/rsa/rsa-checksum.c | 163 +++++++++++++++++++++++++++++++++++++++++++++++++ lib/rsa/rsa-sign.c | 10 +-- lib/rsa/rsa-verify.c | 101 ++++++++++-------------------- lib/sha256.c | 2 +- tools/Makefile | 42 ++++++++++++- tools/fdt_host.h | 2 + tools/fit_check_sign.c | 119 ++++++++++++++++++++++++++++++++++++ tools/fit_common.c | 81 ++++++++++++++++++++++++ tools/fit_common.h | 22 +++++++ tools/fit_image.c | 62 ++----------------- tools/fit_info.c | 116 +++++++++++++++++++++++++++++++++++ tools/image-host.c | 15 ++++- 22 files changed, 831 insertions(+), 137 deletions(-) create mode 100644 include/rsa-checksum.h create mode 100644 lib/rsa/rsa-checksum.c create mode 100644 tools/fit_check_sign.c create mode 100644 tools/fit_common.c create mode 100644 tools/fit_common.h create mode 100644 tools/fit_info.c Cc: Simon Glass <sjg(a)chromium.org> Cc: andreas(a)oetken.name -- 1.8.3.1

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[U-Boot] [PATCH v3] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
by Chin Liang See 13 Feb '14

13 Feb '14

To add the Cadence SPI driver support for Altera SOCFPGA. It required information such as clocks and timing from platform's configuration header file within include/configs folder Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Jagan Teki <jagannadh.teki(a)gmail.com> Cc: Gerhard Sittig <gsi(a)denx.de> --- Changes for v3 - Moved the documentation from doc folder to driver - Documented down macro specific to driver only Changes for v2 - Combine driver into single C file instead of 2 - Added documentation on the macro used - Using structure for registers instead of macro --- drivers/spi/Makefile | 1 + drivers/spi/cadence_qspi.c | 1018 ++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/cadence_qspi.h | 196 +++++++++ 3 files changed, 1215 insertions(+) create mode 100644 drivers/spi/cadence_qspi.c create mode 100644 drivers/spi/cadence_qspi.h diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index ed4ecd7..b8d56ea 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_CF_QSPI) += cf_qspi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c new file mode 100644 index 0000000..4712b45 --- /dev/null +++ b/drivers/spi/cadence_qspi.c @@ -0,0 +1,1018 @@ +/* + * (C) Copyright 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <malloc.h> +#include <spi.h> +#include "cadence_qspi.h" + +static int qspi_is_init; +static unsigned int qspi_calibrated_hz; +static unsigned int qspi_calibrated_cs; + +static const struct cadence_qspi *cadence_qspi_base = (void *)QSPI_BASE; + +#define to_cadence_qspi_slave(s) \ + container_of(s, struct cadence_qspi_slave, slave) + +#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \ + ((((tdelay_ns) - (tsclk_ns)) / (tref_ns))) + +#define CQSPI_GET_WR_SRAM_LEVEL() \ + ((readl(&cadence_qspi_base->sramfill) >> \ + CQSPI_REG_SRAMLEVEL_WR_LSB) & CQSPI_REG_SRAMLEVEL_WR_MASK) + +static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf, + unsigned int addr_width) +{ + unsigned int addr; + + addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2]; + + if (addr_width == 4) + addr = (addr << 8) | addr_buf[3]; + + return addr; +} + +static void cadence_qspi_apb_read_fifo_data(void *dest, + const void *src_ahb_addr, unsigned int bytes) +{ + unsigned int temp; + int remaining = bytes; + unsigned int *dest_ptr = (unsigned int *)dest; + unsigned int *src_ptr = (unsigned int *)src_ahb_addr; + + while (remaining > 0) { + if (remaining >= CQSPI_FIFO_WIDTH) { + *dest_ptr = readl(src_ptr); + remaining -= CQSPI_FIFO_WIDTH; + } else { + /* dangling bytes */ + temp = readl(src_ptr); + memcpy(dest_ptr, &temp, remaining); + break; + } + dest_ptr++; + } + + return; +} + +static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr, + const void *src, unsigned int bytes) +{ + unsigned int temp; + int remaining = bytes; + unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr; + unsigned int *src_ptr = (unsigned int *)src; + + while (remaining > 0) { + if (remaining >= CQSPI_FIFO_WIDTH) { + writel(*src_ptr, dest_ptr); + remaining -= sizeof(unsigned int); + } else { + /* dangling bytes */ + memcpy(&temp, src_ptr, remaining); + writel(temp, dest_ptr); + break; + } + src_ptr++; + } + + return; +} + +/* Read from SRAM FIFO with polling SRAM fill level. */ +static int qspi_read_sram_fifo_poll(void *dest_addr, + const void *src_addr, unsigned int num_bytes) +{ + unsigned int remaining = num_bytes; + unsigned int retry; + unsigned int sram_level = 0; + unsigned char *dest = (unsigned char *)dest_addr; + + while (remaining > 0) { + retry = CQSPI_REG_RETRY; + while (retry--) { + sram_level = (readl(&cadence_qspi_base->sramfill) >> + CQSPI_REG_SRAMLEVEL_RD_LSB) & + CQSPI_REG_SRAMLEVEL_RD_MASK; + if (sram_level) + break; + udelay(1); + } + + if (!retry) { + printf("QSPI: No receive data after polling for %d " + "times\n", CQSPI_REG_RETRY); + return -1; + } + + sram_level *= CQSPI_FIFO_WIDTH; + sram_level = sram_level > remaining ? remaining : sram_level; + + /* Read data from FIFO. */ + cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level); + dest += sram_level; + remaining -= sram_level; + udelay(1); + } + return 0; +} + + +/* Write to SRAM FIFO with polling SRAM fill level. */ +static int qpsi_write_sram_fifo_push(void *dest_addr, + const void *src_addr, unsigned int num_bytes) +{ + unsigned int retry = CQSPI_REG_RETRY; + unsigned int sram_level; + unsigned int wr_bytes; + unsigned char *src = (unsigned char *)src_addr; + int remaining = num_bytes; + unsigned int page_size = CONFIG_CQSPI_PAGE_SIZE; + unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS; + + while (remaining > 0) { + retry = CQSPI_REG_RETRY; + while (retry--) { + sram_level = CQSPI_GET_WR_SRAM_LEVEL(); + if (sram_level <= sram_threshold_words) + break; + } + if (!retry) { + printf("QSPI: SRAM fill level (0x%08x) " + "not hit lower expected level (0x%08x)", + sram_level, sram_threshold_words); + return -1; + } + /* Write a page or remaining bytes. */ + wr_bytes = (remaining > page_size) ? + page_size : remaining; + + cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes); + src += wr_bytes; + remaining -= wr_bytes; + } + + return 0; +} + +static void cadence_qspi_apb_controller_enable(void) +{ + setbits_le32(&cadence_qspi_base->cfg, CQSPI_REG_CONFIG_ENABLE_MASK); +} + +static void cadence_qspi_apb_controller_disable(void) +{ + clrbits_le32(&cadence_qspi_base->cfg, CQSPI_REG_CONFIG_ENABLE_MASK); +} + +/* Return 1 if idle, otherwise return 0 (busy). */ +static unsigned int cadence_qspi_wait_idle(void) +{ + unsigned int start, count = 0; + /* timeout in unit of ms */ + unsigned int timeout = 5000; + + start = get_timer(0); + for ( ; get_timer(start) < timeout ; ) { + if ((readl(&cadence_qspi_base->cfg) >> + CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) + count++; + else + count = 0; + /* + * Ensure the QSPI controller is in true idle state after + * reading back the same idle status consecutively + */ + if (count >= CQSPI_POLL_IDLE_RETRY) + return 1; + } + + /* Timeout, still in busy mode. */ + printf("QSPI: QSPI is still busy after poll for %d times.\n", + CQSPI_REG_RETRY); + return 0; +} + +static void cadence_qspi_apb_readdata_capture(unsigned int bypass, + unsigned int delay) +{ + unsigned int reg; + cadence_qspi_apb_controller_disable(); + + reg = readl(&cadence_qspi_base->rddatacap); + + if (bypass) + reg |= (1 << CQSPI_REG_RD_DATA_CAPTURE_BYPASS_LSB); + else + reg &= ~(1 << CQSPI_REG_RD_DATA_CAPTURE_BYPASS_LSB); + + reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK + << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB); + + reg |= ((delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK) + << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB); + + writel(reg, &cadence_qspi_base->rddatacap); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_config_baudrate_div(unsigned int ref_clk_hz, + unsigned int sclk_hz) +{ + unsigned int reg; + unsigned int div; + + cadence_qspi_apb_controller_disable(); + reg = readl(&cadence_qspi_base->cfg); + reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); + + div = ref_clk_hz / sclk_hz; + + if (div > 32) + div = 32; + + /* Check if even number. */ + if ((div & 1)) + div = (div / 2); + else + div = (div / 2) - 1; + + debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__, + ref_clk_hz, sclk_hz, div); + + div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; + reg |= div; + writel(reg, &cadence_qspi_base->cfg); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_set_clk_mode(unsigned int clk_pol, + unsigned int clk_pha) +{ + unsigned int reg; + + cadence_qspi_apb_controller_disable(); + reg = readl(&cadence_qspi_base->cfg); + reg &= ~(1 << + (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); + + reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); + reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); + + writel(reg, &cadence_qspi_base->cfg); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_chipselect(unsigned int chip_select, + unsigned int decoder_enable) +{ + unsigned int reg; + + cadence_qspi_apb_controller_disable(); + + debug("%s : chipselect %d decode %d\n", __func__, chip_select, + decoder_enable); + + reg = readl(&cadence_qspi_base->cfg); + /* docoder */ + if (decoder_enable) + reg |= CQSPI_REG_CONFIG_DECODE_MASK; + else { + reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; + /* Convert CS if without decoder. + * CS0 to 4b'1110 + * CS1 to 4b'1101 + * CS2 to 4b'1011 + * CS3 to 4b'0111 + */ + chip_select = 0xF & ~(1 << chip_select); + } + + reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK + << CQSPI_REG_CONFIG_CHIPSELECT_LSB); + reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) + << CQSPI_REG_CONFIG_CHIPSELECT_LSB; + writel(reg, &cadence_qspi_base->cfg); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_delay(unsigned int ref_clk, unsigned int sclk_hz, + unsigned int tshsl_ns, unsigned int tsd2d_ns, + unsigned int tchsh_ns, unsigned int tslch_ns) +{ + unsigned int ref_clk_ns; + unsigned int sclk_ns; + unsigned int tshsl, tchsh, tslch, tsd2d; + unsigned int reg; + + cadence_qspi_apb_controller_disable(); + + /* Convert to ns. */ + ref_clk_ns = (1000000000) / ref_clk; + + /* Convert to ns. */ + sclk_ns = (1000000000) / sclk_hz; + + /* Plus 1 to round up 1 clock cycle. */ + tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1; + tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1; + tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1; + tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1; + + reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) + << CQSPI_REG_DELAY_TSHSL_LSB); + reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK) + << CQSPI_REG_DELAY_TCHSH_LSB); + reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK) + << CQSPI_REG_DELAY_TSLCH_LSB); + reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) + << CQSPI_REG_DELAY_TSD2D_LSB); + writel(reg, &cadence_qspi_base->delay); + + cadence_qspi_apb_controller_enable(); + return; +} + +static void cadence_qspi_apb_controller_init(void) +{ + unsigned reg; + + cadence_qspi_apb_controller_disable(); + + /* Configure the device size and address bytes */ + reg = readl(&cadence_qspi_base->devsz); + /* Clear the previous value */ + reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); + reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); + reg |= (CONFIG_CQSPI_PAGE_SIZE << CQSPI_REG_SIZE_PAGE_LSB); + reg |= (CONFIG_CQSPI_BLOCK_SIZE << CQSPI_REG_SIZE_BLOCK_LSB); + writel(reg, &cadence_qspi_base->devsz); + + /* Configure the remap address register, no remap */ + writel(0, &cadence_qspi_base->remapaddr); + + /* Disable all interrupts */ + writel(0, &cadence_qspi_base->irqmask); + + cadence_qspi_apb_controller_enable(); + return; +} + +static int cadence_qspi_apb_exec_flash_cmd(unsigned int reg) +{ + unsigned int retry = CQSPI_REG_RETRY; + + /* Write the CMDCTRL without start execution. */ + writel(reg, &cadence_qspi_base->flashcmd); + /* Start execute */ + reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; + writel(reg, &cadence_qspi_base->flashcmd); + + while (retry--) { + reg = readl(&cadence_qspi_base->flashcmd); + if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0) + break; + udelay(1); + } + + if (!retry) { + printf("QSPI: flash command execution timeout\n"); + return -EIO; + } + + /* Polling QSPI idle status. */ + if (!cadence_qspi_wait_idle()) + return -EIO; + + return 0; +} + +/* For command RDID, RDSR. */ +static int cadence_qspi_apb_command_read(unsigned int cmdlen, const u8 *cmdbuf, + unsigned int rxlen, u8 *rxbuf) +{ + unsigned int reg; + unsigned int read_len; + int status; + + if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) { + printf("QSPI: Invalid input arguments cmdlen %d " + "rxlen %d\n", cmdlen, rxlen); + return -EINVAL; + } + + reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; + + reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); + + /* 0 means 1 byte. */ + reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + status = cadence_qspi_apb_exec_flash_cmd(reg); + if (status != 0) + return status; + + reg = readl(&cadence_qspi_base->flashcmdrddatalo); + + /* Put the read value into rx_buf */ + read_len = (rxlen > 4) ? 4 : rxlen; + memcpy(rxbuf, &reg, read_len); + rxbuf += read_len; + + if (rxlen > 4) { + reg = readl(&cadence_qspi_base->flashcmdrddataup); + + read_len = rxlen - read_len; + memcpy(rxbuf, &reg, read_len); + } + return 0; +} + +/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */ +static int cadence_qspi_apb_command_write(unsigned int cmdlen, + const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf) +{ + unsigned int reg = 0; + unsigned int addr_value; + unsigned int wr_data; + unsigned int wr_len; + + if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) { + printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n", + cmdlen, txlen); + return -EINVAL; + } + + reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; + + if (cmdlen == 4 || cmdlen == 5) { + /* Command with address */ + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + /* Number of bytes to write. */ + reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + /* Get address */ + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], + cmdlen >= 5 ? 4 : 3); + + writel(addr_value, &cadence_qspi_base->flashcmdaddr); + } + + if (txlen) { + /* writing data = yes */ + reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); + reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) + << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; + + wr_len = txlen > 4 ? 4 : txlen; + memcpy(&wr_data, txbuf, wr_len); + writel(wr_data, &cadence_qspi_base->flashcmdwrdatalo); + + if (txlen > 4) { + txbuf += wr_len; + wr_len = txlen - wr_len; + memcpy(&wr_data, txbuf, wr_len); + writel(wr_data, &cadence_qspi_base->flashcmdwrdataup); + } + } + + /* Execute the command */ + return cadence_qspi_apb_exec_flash_cmd(reg); +} + +/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */ +static int cadence_qspi_apb_indirect_read_setup(unsigned int ahb_phy_addr, + unsigned int cmdlen, const u8 *cmdbuf) +{ + unsigned int reg; + unsigned int rd_reg; + unsigned int addr_value; + unsigned int dummy_clk; + unsigned int dummy_bytes; + unsigned int addr_bytes; + + /* + * Identify addr_byte. All NOR flash device drivers are using fast read + * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte. + * With that, the length is in value of 5 or 6. Only FRAM chip from + * ramtron using normal read (which won't need dummy byte). + * Unlikely NOR flash using normal read due to performance issue. + */ + if (cmdlen >= 5) + /* to cater fast read where cmd + addr + dummy */ + addr_bytes = cmdlen - 2; + else + /* for normal read (only ramtron as of now) */ + addr_bytes = cmdlen - 1; + + /* Setup the indirect trigger address */ + writel((ahb_phy_addr & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + &cadence_qspi_base->indaddrtrig); + + /* Configure SRAM partition for read. */ + writel(CQSPI_REG_SRAM_PARTITION_RD, &cadence_qspi_base->srampart); + + /* Configure the opcode */ + rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; + +#if (CONFIG_SPI_FLASH_QUAD == 1) + /* Instruction and address at DQ0, data at DQ0-3. */ + rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; +#endif + + /* Get address */ + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); + writel(addr_value, &cadence_qspi_base->indrdstaddr); + + /* The remaining lenght is dummy bytes. */ + dummy_bytes = cmdlen - addr_bytes - 1; + if (dummy_bytes) { + + if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX) + dummy_bytes = CQSPI_DUMMY_BYTES_MAX; + + rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); +#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) + writel(0x0, &cadence_qspi_base->modebit); +#else + writel(0xFF, &cadence_qspi_base->modebit); +#endif + + /* Convert to clock cycles. */ + dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE; + /* Need to minus the mode byte (8 clocks). */ + dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE; + + if (dummy_clk) + rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) + << CQSPI_REG_RD_INSTR_DUMMY_LSB; + } + + writel(rd_reg, &cadence_qspi_base->devrd); + + /* set device size */ + reg = readl(&cadence_qspi_base->devsz); + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; + reg |= (addr_bytes - 1); + writel(reg, &cadence_qspi_base->devsz); + return 0; +} + +static int cadence_qspi_apb_indirect_read_execute(void *ahb_base_addr, + unsigned int rxlen, u8 *rxbuf) +{ + unsigned int reg; + + writel(rxlen, &cadence_qspi_base->indrdcnt); + + /* Start the indirect read transfer */ + writel(CQSPI_REG_INDIRECTRD_START_MASK, + &cadence_qspi_base->indrd); + + if (qspi_read_sram_fifo_poll((void *)rxbuf, + (const void *)ahb_base_addr, rxlen)) { + goto failrd; + } + + /* Check flash indirect controller */ + reg = readl(&cadence_qspi_base->indrd); + if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) { + reg = readl(&cadence_qspi_base->indrd); + printf("QSPI: indirect completion status " + "error with reg 0x%08x\n", reg); + goto failrd; + } + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTRD_DONE_MASK, &cadence_qspi_base->indrd); + return 0; + +failrd: + /* Cancel the indirect read */ + writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, &cadence_qspi_base->indrd); + return -1; +} + +/* Opcode + Address (3/4 bytes) */ +static int cadence_qspi_apb_indirect_write_setup(unsigned int ahb_phy_addr, + unsigned int cmdlen, const u8 *cmdbuf) +{ + unsigned int reg; + unsigned int addr_bytes = cmdlen > 4 ? 4 : 3; + + if (cmdlen < 4 || cmdbuf == NULL) { + printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n", + cmdlen, (unsigned int)cmdbuf); + return -EINVAL; + } + /* Setup the indirect trigger address */ + writel((ahb_phy_addr & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + &cadence_qspi_base->indaddrtrig); + + writel(CQSPI_REG_SRAM_PARTITION_WR, + &cadence_qspi_base->srampart); + + /* Configure the opcode */ + reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; + writel(reg, &cadence_qspi_base->devwr); + + /* Setup write address. */ + reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); + writel(reg, &cadence_qspi_base->indwrstaddr); + + reg = readl(&cadence_qspi_base->devsz); + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; + reg |= (addr_bytes - 1); + writel(reg, &cadence_qspi_base->devsz); + return 0; +} + +static int cadence_qspi_apb_indirect_write_execute(void *ahb_base_addr, + unsigned int txlen, const u8 *txbuf) +{ + unsigned int reg = 0; + unsigned int retry; + + /* Configure the indirect read transfer bytes */ + writel(txlen, &cadence_qspi_base->indwrcnt); + + /* Start the indirect write transfer */ + writel(CQSPI_REG_INDIRECTWR_START_MASK, &cadence_qspi_base->indwr); + + if (qpsi_write_sram_fifo_push(ahb_base_addr, + (const void *)txbuf, txlen)) { + goto failwr; + } + + /* Wait until last write is completed (FIFO empty) */ + retry = CQSPI_REG_RETRY; + while (retry--) { + reg = CQSPI_GET_WR_SRAM_LEVEL(); + if (reg == 0) + break; + + udelay(1); + } + if (reg != 0) { + printf("QSPI: timeout for indirect write\n"); + goto failwr; + } + + /* Check flash indirect controller status */ + retry = CQSPI_REG_RETRY; + while (retry--) { + reg = readl(&cadence_qspi_base->indwr); + if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK) + break; + udelay(1); + } + if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) { + printf("QSPI: indirect completion " + "status error with reg 0x%08x\n", reg); + goto failwr; + } + + /* Clear indirect completion status */ + writel(CQSPI_REG_INDIRECTWR_DONE_MASK, &cadence_qspi_base->indwr); + return 0; + +failwr: + /* Cancel the indirect write */ + writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, &cadence_qspi_base->indwr); + return -1; +} + +static void cadence_qspi_apb_enter_xip(char xip_dummy) +{ + unsigned int reg; + + /* enter XiP mode immediately and enable direct mode */ + reg = readl(&cadence_qspi_base->cfg); + reg |= CQSPI_REG_CONFIG_ENABLE_MASK; + reg |= CQSPI_REG_CONFIG_DIRECT_MASK; + reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK; + writel(reg, &cadence_qspi_base->cfg); + + /* keep the XiP mode */ + writel(xip_dummy, &cadence_qspi_base->modebit); + + /* Enable mode bit at devrd */ + reg = readl(&cadence_qspi_base->devrd); + reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); + writel(reg, &cadence_qspi_base->devrd); +} + +void spi_set_speed(struct spi_slave *slave, uint hz) +{ + cadence_qspi_apb_config_baudrate_div(CONFIG_CQSPI_REF_CLK, hz); + + /* Reconfigure delay timing if speed is changed. */ + cadence_qspi_apb_delay(CONFIG_CQSPI_REF_CLK, hz, + CONFIG_CQSPI_TSHSL_NS, CONFIG_CQSPI_TSD2D_NS, + CONFIG_CQSPI_TCHSH_NS, CONFIG_CQSPI_TSLCH_NS); + return; +} + +/* calibration sequence to determine the read data capture delay register */ +int spi_calibration(struct spi_slave *slave) +{ + struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave); + u8 opcode_rdid = 0x9F; + unsigned int idcode = 0, temp = 0; + int err = 0, i, range_lo = -1, range_hi = -1; + + /* start with slowest clock (1 MHz) */ + spi_set_speed(slave, 1000000); + + /* configure the read data capture delay register to 0 */ + cadence_qspi_apb_readdata_capture(1, 0); + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(); + + /* read the ID which will be our golden value */ + err = cadence_qspi_apb_command_read(1, &opcode_rdid, + 3, (u8 *)&idcode); + if (err) { + puts("SF: Calibration failed (read)\n"); + return err; + } + + /* use back the intended clock and find low range */ + spi_set_speed(slave, cadence_qspi->max_hz); + for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(); + + /* reconfigure the read data capture delay register */ + cadence_qspi_apb_readdata_capture(1, i); + + /* Enable back QSPI */ + cadence_qspi_apb_controller_enable(); + + /* issue a RDID to get the ID value */ + err = cadence_qspi_apb_command_read(1, &opcode_rdid, + 3, (u8 *)&temp); + if (err) { + puts("SF: Calibration failed (read)\n"); + return err; + } + + /* search for range lo */ + if (range_lo == -1 && temp == idcode) { + range_lo = i; + continue; + } + + /* search for range hi */ + if (range_lo != -1 && temp != idcode) { + range_hi = i - 1; + break; + } + range_hi = i; + } + + if (range_lo == -1) { + puts("SF: Calibration failed (low range)\n"); + return err; + } + + /* Disable QSPI for subsequent initialization */ + cadence_qspi_apb_controller_disable(); + + /* configure the final value for read data capture delay register */ + cadence_qspi_apb_readdata_capture(1, (range_hi + range_lo) / 2); + printf("SF: Read data capture delay calibrated to %i (%i - %i)\n", + (range_hi + range_lo) / 2, range_lo, range_hi); + + /* just to ensure we do once only when speed or chip select change */ + qspi_calibrated_hz = cadence_qspi->max_hz; + qspi_calibrated_cs = slave->cs; + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ +#if (CONFIG_CQSPI_DECODER == 1) + if (((cs >= 0) && (cs < CQSPI_DECODER_MAX_CS)) && ((bus >= 0) && + (bus < CQSPI_DECODER_MAX_CS))) { + return 1; + } +#else + if (((cs >= 0) && (cs < CQSPI_NO_DECODER_MAX_CS)) && + ((bus >= 0) && (bus < CQSPI_NO_DECODER_MAX_CS))) { + return 1; + } +#endif + printf("QSPI: Invalid bus or cs. Bus %d cs %d\n", bus, cs); + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + return; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + return; +} + +void spi_init(void) +{ + cadence_qspi_apb_controller_init(); + qspi_is_init = 1; + return; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct cadence_qspi_slave *cadence_qspi; + + debug("%s: bus %d cs %d max_hz %dMHz mode %d\n", __func__, + bus, cs, max_hz/1000000, mode); + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + cadence_qspi = malloc(sizeof(struct cadence_qspi_slave)); + if (!cadence_qspi) { + printf("QSPI: Can't allocate struct cadence_qspi_slave. " + "Bus %d cs %d\n", bus, cs); + return NULL; + } + + cadence_qspi->slave.bus = bus; + cadence_qspi->slave.cs = cs; + cadence_qspi->mode = mode; + cadence_qspi->max_hz = max_hz; + cadence_qspi->regbase = (void *)QSPI_BASE; + cadence_qspi->ahbbase = (void *)QSPI_AHB_BASE; + + if (!qspi_is_init) + spi_init(); + + return &cadence_qspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave); + free(cadence_qspi); + return; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave); + unsigned int clk_pol = (cadence_qspi->mode & SPI_CPOL) ? 1 : 0; + unsigned int clk_pha = (cadence_qspi->mode & SPI_CPHA) ? 1 : 0; + int err = 0; + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(); + + /* Set Chip select */ + cadence_qspi_apb_chipselect(slave->cs, CONFIG_CQSPI_DECODER); + + /* Set SPI mode */ + cadence_qspi_apb_set_clk_mode(clk_pol, clk_pha); + + /* Set clock speed */ + spi_set_speed(slave, cadence_qspi->max_hz); + + /* calibration required for different SCLK speed or chip select */ + if (qspi_calibrated_hz != cadence_qspi->max_hz || + qspi_calibrated_cs != slave->cs) { + err = spi_calibration(slave); + if (err) + return err; + } + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + return; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, + void *data_in, unsigned long flags) +{ + struct cadence_qspi_slave *cadence_qspi = to_cadence_qspi_slave(slave); + void *ahbbase = cadence_qspi->ahbbase; + u8 *cmd_buf = cadence_qspi->cmd_buf; + size_t data_bytes; + int err = 0; + u32 mode = CQSPI_STIG_WRITE; + + if (flags & SPI_XFER_BEGIN) { + /* copy command to local buffer */ + cadence_qspi->cmd_len = bitlen / 8; + memcpy(cmd_buf, data_out, cadence_qspi->cmd_len); + } + + if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { + /* if start and end bit are set, the data bytes is 0. */ + data_bytes = 0; + } else { + data_bytes = bitlen / 8; + } + + if ((flags & SPI_XFER_END) || (flags == 0)) { + if (cadence_qspi->cmd_len == 0) { + printf("QSPI: Error, command is empty.\n"); + return -1; + } + + if (data_in && data_bytes) { + /* read */ + /* Use STIG if no address. */ + if (!CQSPI_IS_ADDR(cadence_qspi->cmd_len)) + mode = CQSPI_STIG_READ; + else + mode = CQSPI_INDIRECT_READ; + } else if (data_out && !(flags & SPI_XFER_BEGIN)) { + /* write */ + if (!CQSPI_IS_ADDR(cadence_qspi->cmd_len)) + mode = CQSPI_STIG_WRITE; + else + mode = CQSPI_INDIRECT_WRITE; + } + + switch (mode) { + case CQSPI_STIG_READ: + err = cadence_qspi_apb_command_read( + cadence_qspi->cmd_len, cmd_buf, + data_bytes, data_in); + + break; + case CQSPI_STIG_WRITE: + err = cadence_qspi_apb_command_write( + cadence_qspi->cmd_len, cmd_buf, + data_bytes, data_out); + break; + case CQSPI_INDIRECT_READ: + err = cadence_qspi_apb_indirect_read_setup( + QSPI_AHB_BASE, + cadence_qspi->cmd_len, cmd_buf); + if (!err) { + err = cadence_qspi_apb_indirect_read_execute + (ahbbase, data_bytes, data_in); + } + break; + case CQSPI_INDIRECT_WRITE: + err = cadence_qspi_apb_indirect_write_setup + (QSPI_AHB_BASE, + cadence_qspi->cmd_len, cmd_buf); + if (!err) { + err = cadence_qspi_apb_indirect_write_execute + (ahbbase, data_bytes, data_out); + } + break; + default: + err = -1; + break; + } + + if (flags & SPI_XFER_END) { + /* clear command buffer */ + memset(cmd_buf, 0, sizeof(cadence_qspi->cmd_buf)); + cadence_qspi->cmd_len = 0; + } + } + return err; +} + +void spi_enter_xip(struct spi_slave *slave, char xip_dummy) +{ + /* Enter XiP */ + cadence_qspi_apb_enter_xip(xip_dummy); + return; +} + + diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h new file mode 100644 index 0000000..346837e --- /dev/null +++ b/drivers/spi/cadence_qspi.h @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CADENCE_QSPI_H__ +#define __CADENCE_QSPI_H__ + +/* + * Macro required for this driver + * + * #define CONFIG_CQSPI_BASE (SOCFPGA_QSPIREGS_ADDRESS) + * #define CONFIG_CQSPI_AHB_BASE (SOCFPGA_QSPIDATA_ADDRESS) + * -> To specify base address for controller CSR base and AHB data base addr + * + * #define CONFIG_CQSPI_REF_CLK (400000000) + * -> The clock frequency supplied from PLL to the QSPI controller + * + * #define CONFIG_CQSPI_PAGE_SIZE (256) + * -> To define the page size of serial flash in bytes + * + * #define CONFIG_CQSPI_BLOCK_SIZE (16) + * -> To define the block size of serial flash in pages + * + * #define CONFIG_CQSPI_DECODER (0) + * -> To enable the 4-to-16 decoder which enable up to 16 serial flash devices + * + * #define CONFIG_CQSPI_TSHSL_NS (200) + * #define CONFIG_CQSPI_TSD2D_NS (255) + * #define CONFIG_CQSPI_TCHSH_NS (20) + * #define CONFIG_CQSPI_TSLCH_NS (20) + * -> Configure controller based on serial flash device timing characteristic + */ + +#define QSPI_BASE (CONFIG_CQSPI_BASE) +#define QSPI_AHB_BASE (CONFIG_CQSPI_AHB_BASE) +#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) + +struct cadence_qspi_slave { + struct spi_slave slave; + unsigned int mode; + unsigned int max_hz; + void *regbase; + void *ahbbase; + size_t cmd_len; + u8 cmd_buf[32]; + size_t data_len; +}; + +struct cadence_qspi { + u32 cfg; + u32 devrd; + u32 devwr; + u32 delay; + u32 rddatacap; + u32 devsz; + u32 srampart; + u32 indaddrtrig; + u32 dmaper; + u32 remapaddr; + u32 modebit; + u32 sramfill; + u32 txthresh; + u32 rxthresh; + u32 _pad_0x38_0x3f[2]; + u32 irqstat; + u32 irqmask; + u32 _pad_0x48_0x4f[2]; + u32 lowwrprot; + u32 uppwrprot; + u32 wrprot; + u32 _pad_0x5c_0x5f; + u32 indrd; + u32 indrdwater; + u32 indrdstaddr; + u32 indrdcnt; + u32 indwr; + u32 indwrwater; + u32 indwrstaddr; + u32 indwrcnt; + u32 _pad_0x80_0x8f[4]; + u32 flashcmd; + u32 flashcmdaddr; + u32 _pad_0x98_0x9f[2]; + u32 flashcmdrddatalo; + u32 flashcmdrddataup; + u32 flashcmdwrdatalo; + u32 flashcmdwrdataup; + u32 _pad_0xb0_0xfb[19]; + u32 moduleid; +}; + +/* Controller's configuration and status register */ +#define CQSPI_REG_CONFIG_CLK_POL_LSB 1 +#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2 +#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0) +#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7) +#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9) +#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18) +#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 +#define CQSPI_REG_CONFIG_BAUD_LSB 19 +#define CQSPI_REG_CONFIG_IDLE_LSB 31 +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF +#define CQSPI_REG_CONFIG_BAUD_MASK 0xF +#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 +#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 +#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 +#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F +#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 +#define CQSPI_REG_DELAY_TSLCH_LSB 0 +#define CQSPI_REG_DELAY_TCHSH_LSB 8 +#define CQSPI_REG_DELAY_TSD2D_LSB 16 +#define CQSPI_REG_DELAY_TSHSL_LSB 24 +#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF +#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF +#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF +#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF +#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS_LSB 0 +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1 +#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF +#define CQSPI_REG_SIZE_ADDRESS_LSB 0 +#define CQSPI_REG_SIZE_PAGE_LSB 4 +#define CQSPI_REG_SIZE_BLOCK_LSB 16 +#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF +#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF +#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F +#define CQSPI_REG_SRAMLEVEL_RD_LSB 0 +#define CQSPI_REG_SRAMLEVEL_WR_LSB 16 +#define CQSPI_REG_SRAMLEVEL_RD_MASK 0xFFFF +#define CQSPI_REG_SRAMLEVEL_WR_MASK 0xFFFF +#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0) +#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1) +#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2) +#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5) +#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0) +#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1) +#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 +#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 +#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 +#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 +#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 +#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 +#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 +#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 +#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF +#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0) +#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1) +#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2) +#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5) + +/* Transfer type */ +#define CQSPI_STIG_READ 0 +#define CQSPI_STIG_WRITE 1 +#define CQSPI_INDIRECT_READ 2 +#define CQSPI_INDIRECT_WRITE 3 + +/* Transfer mode */ +#define CQSPI_INST_TYPE_SINGLE (0) +#define CQSPI_INST_TYPE_DUAL (1) +#define CQSPI_INST_TYPE_QUAD (2) + +/* controller operation setting */ +#define CQSPI_NO_DECODER_MAX_CS (4) +#define CQSPI_DECODER_MAX_CS (16) +#define CQSPI_READ_CAPTURE_MAX_DELAY (16) +#define CQSPI_REG_POLL_US (1) +#define CQSPI_REG_RETRY (10000) +#define CQSPI_POLL_IDLE_RETRY (3) +#define CQSPI_FIFO_WIDTH (4) +#define CQSPI_STIG_DATA_LEN_MAX (8) +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) +#define CQSPI_DUMMY_CLKS_PER_BYTE (8) +#define CQSPI_DUMMY_BYTES_MAX (4) + +/* Controller sram size in word */ +#define CQSPI_REG_SRAM_SIZE_WORD (128) +#define CQSPI_REG_SRAM_RESV_WORDS (2) +#define CQSPI_REG_SRAM_PARTITION_WR (1) +#define CQSPI_REG_SRAM_PARTITION_RD \ + (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS) +#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) +#define CQSPI_REG_SRAM_FILL_THRESHOLD \ + ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) + +#endif /* __CADENCE_QSPI_H__ */ -- 1.7.9.5

2 2

[U-Boot] [PATCH 1/8] arm/km: drop unneeded define
by Holger Brunck 13 Feb '14

13 Feb '14

CONFIG_BOOTCOUNT_LIMIT is used on all boards from this board series. So remove this unneeded define. Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> --- board/keymile/km_arm/km_arm.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 5620737..946cbed 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -164,7 +164,6 @@ static int initialize_unit_leds(void) return 0; } -#if defined(CONFIG_BOOTCOUNT_LIMIT) static void set_bootcount_addr(void) { uchar buf[32]; @@ -173,7 +172,6 @@ static void set_bootcount_addr(void) sprintf((char *)buf, "0x%x", bootcountaddr); setenv("bootcountaddr", (char *)buf); } -#endif int misc_init_r(void) { @@ -210,9 +208,7 @@ int misc_init_r(void) initialize_unit_leds(); set_km_env(); -#if defined(CONFIG_BOOTCOUNT_LIMIT) set_bootcount_addr(); -#endif return 0; } -- 1.8.0.1

3 15

[U-Boot] [PATCH] ARM: bcm2835: config.mk isn't needed
by Stephen Warren 13 Feb '14

13 Feb '14

The entries in config.mk were needed so that U-Boot could be built with an old version of the Raspberry Pi Foundation's toolchain. Without them, the build would error out with: ...-ld: error: .../libgcc.a(_bswapsi2.o) uses VFP register arguments, u-boot does not However, none of the 3 toolchains in the latest version of their tools.git, nor the Ubuntu/Linaro ARM compilers in at least Ubuntu Quantal or Saucy, need these options set in order to compile a working U-Boot. Hence, remove the options for simplicity. Reported-by: Tom Rini <trini(a)ti.com> Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- arch/arm/cpu/arm1176/bcm2835/config.mk | 19 ------------------- 1 file changed, 19 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/bcm2835/config.mk diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk deleted file mode 100644 index b87ce24..0000000 --- a/arch/arm/cpu/arm1176/bcm2835/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2012 Stephen Warren -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# Don't attempt to override the target CPU/ABI options; -# the Raspberry Pi toolchain does the right thing by default. -PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS)) -PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS)) -- 1.8.3.2

4 8

[U-Boot] [PATCH] ARM: rpi_b: set $fdtfile in default environment
by Stephen Warren 13 Feb '14

13 Feb '14

U-Boot names the Raspberry Pi board rpi_b. This means that the common expression for DTB filename ${soc}-${board}.dtb expands to bcm2835-rpi_b.dtb. However, the DTB generated by the Linux kernel is bcm2835-rpi-b.dtb. Set $fdtfile in U-Boot's environment so that scripts look for the correct DTB filename. An alternative would be to rename the U-Boot board to rpi-b. However, that change would be far more invasive, and end up affecting users (i.e they'd have to change their U-Boot build commands). Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- include/configs/rpi_b.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 0b7add7..976ceaa 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -123,6 +123,7 @@ "scriptaddr=0x00000000\0" \ "kernel_addr_r=0x01000000\0" \ "fdt_addr_r=0x02000000\0" \ + "fdtfile=bcm2835-rpi-b.dtb\0" \ "ramdisk_addr_r=0x02100000\0" \ "boot_targets=mmc0\0" \ \ -- 1.8.3.2

2 4

[U-Boot] [PATCH 01/10] ARM: IXP: Remove actux1 board
by Marek Vasut 13 Feb '14

13 Feb '14

The board is unmaintained, just like the rest of the IXP. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Michael Schwingen <michael(a)schwingen.org> Cc: Tom Rini <trini(a)ti.com> --- board/actux1/Makefile | 8 -- board/actux1/actux1.c | 148 ------------------------------- board/actux1/actux1_hw.h | 41 --------- board/actux1/u-boot.lds | 99 --------------------- boards.cfg | 4 - include/configs/actux1.h | 226 ----------------------------------------------- 6 files changed, 526 deletions(-) delete mode 100644 board/actux1/Makefile delete mode 100644 board/actux1/actux1.c delete mode 100644 board/actux1/actux1_hw.h delete mode 100644 board/actux1/u-boot.lds delete mode 100644 include/configs/actux1.h diff --git a/board/actux1/Makefile b/board/actux1/Makefile deleted file mode 100644 index 05a8669..0000000 --- a/board/actux1/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := actux1.o diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c deleted file mode 100644 index 03ccd93..0000000 --- a/board/actux1/actux1.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael(a)schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr(a)denx.de. - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <asm/arch/ixp425.h> -#include <asm/io.h> -#include <miiphy.h> -#ifdef CONFIG_PCI -#include <pci.h> -#include <asm/arch/ixp425pci.h> -#endif - -#include "actux1_hw.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* CS5: Debug port */ - writel(0x9d520003, IXP425_EXP_CS5); - /* CS6: HwRel */ - writel(0x81860001, IXP425_EXP_CS6); - /* CS7: LEDs */ - writel(0x80900003, IXP425_EXP_CS7); - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); - - /* Setup GPIOs for PCI INTA */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA); - - /* Setup GPIOs for 33MHz clock output */ - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); - writel(0x011001FF, IXP425_GPIO_GPCLKR); - - udelay(533); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); - - ACTUX1_LED1(2); - ACTUX1_LED2(2); - ACTUX1_LED3(0); - ACTUX1_LED4(0); - ACTUX1_LED5(0); - ACTUX1_LED6(0); - ACTUX1_LED7(0); - - ACTUX1_HS(ACTUX1_HS_DCD); - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: AcTux-1 rev."); - putc(ACTUX1_BOARDREL + 'A' - 1); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = reserved - * 1 = Rev. A - * 2 = Rev. B - *************************************************************************/ -u32 get_board_rev(void) -{ - return ACTUX1_BOARDREL; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); - return 0; -} - - -#ifdef CONFIG_PCI -struct pci_controller hose; - -void pci_init_board(void) -{ - pci_ixp_init(&hose); -} -#endif - -void reset_phy(void) -{ - u16 id1, id2; - - /* initialize the PHY */ - miiphy_reset("NPE0", CONFIG_PHY_ADDR); - - miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); - miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); - - id2 &= 0xFFF0; /* mask out revision bits */ - - if (id1 == 0x13 && id2 == 0x78e0) { - /* - * LXT971/LXT972 PHY: set LED outputs: - * LED1(green) = Link/ACT, - * LED2 (unused) = LINK, - * LED3(red) = Coll - */ - miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); - } else if (id1 == 0x143 && id2 == 0xbc30) { - /* BCM5241: default values are OK */ - } else - printf("unknown ethernet PHY ID: %x %x\n", id1, id2); -} diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h deleted file mode 100644 index 5627f24..0000000 --- a/board/actux1/actux1_hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael(a)schwingen.org - * - * hardware register definitions for the AcTux-1 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ACTUX1_HW_H -#define _ACTUX1_HW_H - -/* 0 = LED off,1 = green, 2 = red, 3 = orange */ -#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) -#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) -#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) -#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3) -#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4) -#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5) -#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) -#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) -#define ACTUX1_HS_DCD 0x01 -#define ACTUX1_HS_DSR 0x02 - -#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS -#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) - -/* GPIO settings */ -#define CONFIG_SYS_GPIO_PCI1_INTA 2 -#define CONFIG_SYS_GPIO_PCI2_INTA 3 -#define CONFIG_SYS_GPIO_I2C_SDA 4 -#define CONFIG_SYS_GPIO_I2C_SCL 5 -#define CONFIG_SYS_GPIO_DBGJUMPER 9 -#define CONFIG_SYS_GPIO_BUTTON1 10 -#define CONFIG_SYS_GPIO_DBGSENSE 11 -#define CONFIG_SYS_GPIO_DTR 12 -#define CONFIG_SYS_GPIO_IORST 13 /* Out */ -#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ -#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ - -#endif diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds deleted file mode 100644 index 4716e4f..0000000 --- a/board/actux1/u-boot.lds +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH (arm) -ENTRY (_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN (4); - .text : { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - net/built-in.o(.text*) - board/actux1/built-in.o(.text*) - arch/arm/cpu/ixp/built-in.o(.text*) - drivers/input/built-in.o(.text*) - - . = env_offset; - common/env_embedded.o(.ppcenv) - *(.text*) - } - - . = ALIGN(4); - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - . = ALIGN(4); - .data : { - *(.data*) - } - . = ALIGN(4); - .got : { - *(.got) - } - . =.; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN (4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/boards.cfg b/boards.cfg index 2dfd2b4..b3faeb4 100644 --- a/boards.cfg +++ b/boards.cfg @@ -381,10 +381,6 @@ Active arm ixp - - - Active arm ixp - - - actux3 - Michael Schwingen <michael(a)schwingen.org> Active arm ixp - - - actux4 - Michael Schwingen <michael(a)schwingen.org> Active arm ixp - - - dvlhost - Michael Schwingen <michael(a)schwingen.org> -Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen <michael(a)schwingen.org> -Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen <michael(a)schwingen.org> -Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen <michael(a)schwingen.org> -Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen <michael(a)schwingen.org> Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut(a)gmail.com> Active arm pxa - - - h2200 - Lukasz Dalek <luk0104(a)gmail.com> Active arm pxa - - - palmld - Marek Vasut <marek.vasut(a)gmail.com> diff --git a/include/configs/actux1.h b/include/configs/actux1.h deleted file mode 100644 index 9b8bd78..0000000 --- a/include/configs/actux1.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (C) Copyright 2007 - * Michael Schwingen, michael(a)schwingen.org - * - * Configuration settings for the AcTux-1 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_IXP425 1 -#define CONFIG_ACTUX1 1 - -#define CONFIG_MACH_TYPE 1479 - -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_IXP_SERIAL -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds" - -/*************************************************************** - * U-boot generic defines start here. - ***************************************************************/ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ELF -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCI_PNP -#define CONFIG_IXP_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI_ENUM -#endif - -#define CONFIG_BOOTCOMMAND "run boot_flash" -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -/* timer clock - 2* OSC_IN system clock */ -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400 } -#define CONFIG_SERIAL_RTS_ACTIVE 1 - -/* Expansion bus settings */ -#define CONFIG_SYS_EXP_CS0 0xbd113842 - -/* SDRAM settings */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#ifdef CONFIG_RAM_32MB -# define CONFIG_SYS_SDR_CONFIG 0x18 -# define PHYS_SDRAM_1_SIZE 0x02000000 -# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -# define CONFIG_SYS_DRAM_SIZE 0x02000000 -#else /* 16MB SDRAM */ -# define CONFIG_SYS_SDR_CONFIG 0x3A -# define PHYS_SDRAM_1_SIZE 0x01000000 -# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a -# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -# define CONFIG_SYS_DRAM_SIZE 0x01000000 -#endif - -/* FLASH organization */ -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#ifdef CONFIG_FLASH2X2 -# define CONFIG_SYS_MAX_FLASH_BANKS 2 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 40 -# define PHYS_FLASH_1 0x50000000 -# define PHYS_FLASH_2 0x50200000 -# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } -#endif -#ifdef CONFIG_FLASH1X8 -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 140 -# define PHYS_FLASH_1 0x50000000 -# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } -#endif - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_BOARD_SIZE_LIMIT 262144 - -/* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -/* no byte writes on IXP4xx */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Ethernet */ - -/* include IXP4xx NPE support */ -#define CONFIG_IXP4XX_NPE 1 -/* NPE0 PHY address */ -#define CONFIG_PHY_ADDR 0 -/* NPE1 PHY address (HW Release E only) */ -#define CONFIG_PHY1_ADDR 1 -/* MII PHY management */ -#define CONFIG_MII 1 -/* Number of ethernet rx buffers & descriptors */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RESET_PHY_R 1 - -#define CONFIG_HAS_ETH1 1 - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#undef CONFIG_CMD_NFS - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * environment organization: - * one flash sector, embedded in uboot area (bottom bootblock flash) - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) -#define CONFIG_SYS_USE_PPCENV 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "npe_ucode=50040000\0" \ - "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ - "kerneladdr=50050000\0" \ - "kernelfile=actux1/uImage\0" \ - "rootfile=actux1/rootfs\0" \ - "rootaddr=50170000\0" \ - "loadaddr=10000\0" \ - "updateboot_ser=mw.b 10000 ff 40000;" \ - " loady ${loadaddr};" \ - " run eraseboot writeboot\0" \ - "updateboot_net=mw.b 10000 ff 40000;" \ - " tftp ${loadaddr} actux1/u-boot.bin;" \ - " run eraseboot writeboot\0" \ - "eraseboot=protect off 50000000 50003fff;" \ - " protect off 50006000 5003ffff;" \ - " erase 50000000 50003fff;" \ - " erase 50006000 5003ffff\0" \ - "writeboot=cp.b 10000 50000000 4000;" \ - " cp.b 16000 50006000 3a000\0" \ - "updateucode=loady;" \ - " era ${npe_ucode} +${filesize};" \ - " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ - "updateroot=tftp ${loadaddr} ${rootfile};" \ - " era ${rootaddr} +${filesize};" \ - " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ - "updatekern=tftp ${loadaddr} ${kernelfile};" \ - " era ${kerneladdr} +${filesize};" \ - " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ - "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ - " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ - "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ - "boot_flash=run flashargs addtty addeth;" \ - " bootm ${kerneladdr}\0" \ - "boot_net=run netargs addtty addeth;" \ - " tftpboot ${loadaddr} ${kernelfile};" \ - " bootm\0" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ -- 1.8.5.2

3 17

[U-Boot] Improve upstream support for Snowball board (v2)
by Roy Spliet 13 Feb '14

13 Feb '14

Patches are loosely based on the tree maintained by Calao. FDT confirmed working, LAN is successfully detected by u-boot (but lacking a proper tftp setup this is untested). Upstream U-Boot still has one bug that prevents booting from eMMC. Easiest workaround is to revert e95504497ecac46907204b0ee3460b708a2981ac mmc: Split device init to decouple OCR-polling delay until I (or someone else) has time to device a proper fix. This doesn't prevent anyone from pushing these two patches though. v2: Split up networking patch into one for driver and one for board. Fix checkpatch errors. Three warnings are still reported by checkstyle.pl, related to the use of the volatile keyword. These warning are not justified or relevant for MMIO register reads as far as I know, so could be ignored.

2 5

[U-Boot] [PATCH] arm: Remove unused !CONFIG_SPL_BUILD code in board_init_f()
by Tom Rini 13 Feb '14

13 Feb '14

Some code in board_init_f that dates back to the initial relocation support had if/else for PRELOADER (which became SPL_BUILD) about setting the stack pointer. But, board.c is never built for CONFIG_SPL_BUILD now, so this really makes no sense. Drop this section. Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/lib/board.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 34f50b0..3c519a8 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -377,7 +377,6 @@ void board_init_f(ulong bootflag) debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr); -#ifndef CONFIG_SPL_BUILD /* * reserve memory for malloc() arena */ @@ -431,10 +430,6 @@ void board_init_f(ulong bootflag) /* 8-byte alignment for ABI compliance */ addr_sp &= ~0x07; -#else - addr_sp += 128; /* leave 32 words for abort-stack */ - gd->irq_sp = addr_sp; -#endif interrupt_init(); debug("New Stack Pointer is: %08lx\n", addr_sp); -- 1.7.9.5

4 5

[U-Boot] [PATCH 1/3] mpc85xx: Add support for the supplement configuration unit register
by Tang Yuantian 13 Feb '14

13 Feb '14

From: Tang Yuantian <yuantian.tang(a)freescale.com> The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- arch/powerpc/include/asm/immap_85xx.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 68c3c82..71d803b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3113,4 +3113,26 @@ struct dcsr_dcfg_regs { #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ }; + +#define CONFIG_SYS_MPC85xx_SCFG \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET) +#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 +/* The supplement configuration unit register */ +struct ccsr_scfg { + u32 dpslpcr; /* 0x000 Deep Sleep Control register */ + u32 usb1dpslpcsr; /* 0x004 USB1 Deep Sleep Control Status register */ + u32 usb2dpslpcsr; /* 0x008 USB2 Deep Sleep Control Status register */ + u32 fmclkdpslpcr; /* 0x00c FM Clock Deep Sleep Control register */ + u32 res1[4]; + u32 esgmiiselcr; /* 0x020 Ethernet Switch SGMII Select Control register */ + u32 res2; + u32 pixclkcr; /* 0x028 Pixel Clock Control register */ + u32 res3[245]; + u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */ + u32 emiiocr; /* 0x404 EMI MDIO Control Register */ + u32 sdhciovselcr; /* 0x408 SDHC IO VSEL Control register */ + u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */ + u32 res4[60]; + u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */ +}; #endif /*__IMMAP_85xx__*/ -- 1.8.0

2 3

[U-Boot] tlb15_entry is set wrong in the 4K code when the MPC8572DS boots from nand flash
by Y fan 13 Feb '14

13 Feb '14

Hello, The memory of the MPC8572DS can't be read correctly after the setup of the tlb1_entry in the 4K boot code. And also in the create_init_ram code, the tlb1_entry15&14 are set to be in the address space 0 which are supposed to be used in the address space 1. There seems somthing wrong with the writing of the TLB entry. But I don't know why. Do anyone know the reason? Thank you very much. Y.Fan

2 3