January 2014 - U-Boot

[U-Boot] [PATCH] mx6: Distinguish mx6dual from mx6quad
by Fabio Estevam 16 Jan '14

16 Jan '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> Currently when we boot a mx6dual U-boot reports that it is a mx6quad. Report it as MX6D instead: CPU: Freescale i.MX6D rev1.2 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> Tested-by: Otavio Salvador <otavio(a)ossystems.com.br> --- arch/arm/cpu/armv7/mx6/soc.c | 14 +++++++++++--- arch/arm/imx-common/cpu.c | 2 ++ arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 009a644..a6fb6ab 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -43,14 +43,19 @@ u32 get_cpu_rev(void) if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + u32 cfg = readl(&scu->config) & 3; type = ((reg >> 16) & 0xff); if (type == MXC_CPU_MX6DL) { - struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - u32 cfg = readl(&scu->config) & 3; - if (!cfg) type = MXC_CPU_MX6SOLO; } + + if (type == MXC_CPU_MX6Q) { + if (cfg == 1) + type = MXC_CPU_MX6D; + } + } reg &= 0xff; /* mx6 silicon revision */ return (type << 12) | (reg + 0x10); @@ -64,6 +69,9 @@ u32 __weak get_board_rev(void) if (type == MXC_CPU_MX6SOLO) cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); + if (type == MXC_CPU_MX6D) + cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); + return cpurev; } #endif diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 9231649..a77c4de 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype) switch (imxtype) { case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ + case MXC_CPU_MX6D: + return "6D"; /* Dual-core version of the mx6 */ case MXC_CPU_MX6DL: return "6DL"; /* Dual Lite version of the mx6 */ case MXC_CPU_MX6SOLO: diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 17125a6..eda779e 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -16,6 +16,7 @@ #define MXC_CPU_MX6DL 0x61 #define MXC_CPU_MX6SOLO 0x62 #define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6D 0x64 #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); -- 1.8.1.2

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[U-Boot] [RFC v2] implementation of generic distro configs
by Dennis Gilmore 16 Jan '14

16 Jan '14

>From V2 ive added support to cmd_pxe.c for any filesystem and added generic suppport to the distro config, the result is /boot can be vfat or ext and will just work. I have fixed up the arch in pxe so taht it is only represented as armv7 on v7 builds Left to go is to deal with memory addresses correctly in the most flexible way, and Wolfgang's objections to the use of fdt_addr to have u-boot load a dtb automatically without the need to pass in a fdt line in the extlinux.conf the patches are all posted at http://fedorapeople.org/cgit/ausil/public_git/u-boot.git/ as well Dennis

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[U-Boot] [ANN] v2014.01-rc3
by Tom Rini 16 Jan '14

16 Jan '14

Hey all, I've put v2014.01-rc3 out and we should have a tarball soon. Here's where we're at, I feel. We got some big changes in, which had been due for a while, on Friday. I don't think it's a good idea to release today, so I'm going to push things out a week. Here's what I expect for the release, change-wise: - Any regressions people report - Either removal of mini2440 and mx1ads or CONFIG_SYS_HZ fixes for them (Albert is working a removal patch now, or soon). - Fixes for i.mx platforms using hardfp toolchains (which means do_div being called instead). The patch exists, lets get this through please. Thanks all! -- Tom

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[U-Boot] [PATCH 1/2] env_mmc: make board configurable the partition for the environment
by Hector Palacios 16 Jan '14

16 Jan '14

This complements commit 9404a5fc7cb58 "env_mmc: allow environment to be in an eMMC partition" by allowing boards to accommodate the partition to use for the environment in different scenarios (similarly to what is done with the mmc dev number). Depending on the detected boot media, boards may decide to store the environment in a different partition. The __weak function also allows to remove some ifdefs from the code. If CONFIG_SYS_MMC_ENV_PART is not defined, partition 0 is assumed (default value for U-Boot when a partition is not provided). Signed-off-by: Hector Palacios <hector.palacios(a)digi.com> CC: Stephen Warren <swarren(a)nvidia.com> CC: Andy Fleming <afleming(a)freescale.com> --- common/env_mmc.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/common/env_mmc.c b/common/env_mmc.c index 78c2bc7a1f08..d569b070e005 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -64,6 +64,13 @@ __weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) __weak int mmc_get_env_devno(void) { return CONFIG_SYS_MMC_ENV_DEV; + +__weak int mmc_get_env_partno(void) +{ +#ifdef CONFIG_SYS_MMC_ENV_PART + return CONFIG_SYS_MMC_ENV_PART; +#endif + return 0; } int env_init(void) @@ -77,6 +84,9 @@ int env_init(void) static int init_mmc_for_env(struct mmc *mmc) { + int mmc_env_devno = mmc_get_env_devno(); + int mmc_env_partno = mmc_get_env_partno(); + if (!mmc) { puts("No MMC card found\n"); return -1; @@ -87,30 +97,23 @@ static int init_mmc_for_env(struct mmc *mmc) return -1; } -#ifdef CONFIG_SYS_MMC_ENV_PART - if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) { - int mmc_env_devno = mmc_get_env_devno(); - - if (mmc_switch_part(mmc_env_devno, - CONFIG_SYS_MMC_ENV_PART)) { + if (mmc_env_partno != mmc->part_num) { + if (mmc_switch_part(mmc_env_devno, mmc_env_partno)) { puts("MMC partition switch failed\n"); return -1; } } -#endif return 0; } static void fini_mmc_for_env(struct mmc *mmc) { -#ifdef CONFIG_SYS_MMC_ENV_PART int mmc_env_devno = mmc_get_env_devno(); + int mmc_env_partno = mmc_get_env_partno(); - if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) - mmc_switch_part(mmc_env_devno, - mmc->part_num); -#endif + if (mmc_env_partno != mmc->part_num) + mmc_switch_part(mmc_env_devno, mmc->part_num); } #ifdef CONFIG_CMD_SAVEENV

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[U-Boot] [PATCH] mx6: Revert "mx6: soc: Disable VDDPU regulator"
by Fabio Estevam 16 Jan '14

16 Jan '14

Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: Otavio Salvador <otavio(a)ossystems.com.br> Reported-by: Pierre Aubert <p.aubert(a)staubli.com> Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Stefano, I will provide a proper fix after 2014.01 is out, but to allow people to use mainline U-boot with FSL kernels, it would be better to revert it for now. Thanks arch/arm/cpu/armv7/mx6/soc.c | 41 -------------------------------- arch/arm/include/asm/arch-mx6/crm_regs.h | 1 - arch/arm/include/asm/arch-mx6/imx-regs.h | 23 ------------------ 3 files changed, 65 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 009a644..0208cba 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -19,8 +19,6 @@ #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> -#define VDDPU_MASK (0x1f << 9) - enum ldo_reg { LDO_ARM, LDO_SOC, @@ -179,50 +177,11 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } -static void imx_set_vddpu_power_down(void) -{ - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR; - - u32 reg; - - /* - * Disable the brown out detection since we are going to be - * disabling the LDO. - */ - reg = readl(&anatop->ana_misc2); - reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN; - writel(reg, &anatop->ana_misc2); - - /* need to power down xPU in GPC before turning off PU LDO */ - reg = readl(&gpc->gpu_ctrl); - writel(reg | 0x1, &gpc->gpu_ctrl); - - reg = readl(&gpc->ctrl); - writel(reg | 0x1, &gpc->ctrl); - while (readl(&gpc->ctrl) & 0x1) - ; - - /* Mask the ANATOP brown out interrupt in the GPC. */ - reg = readl(&gpc->imr4); - reg |= 0x80000000; - writel(reg, &gpc->imr4); - - /* disable VDDPU */ - writel(VDDPU_MASK, &anatop->reg_core_clr); - - /* Clear the BO interrupt in the ANATOP. */ - reg = readl(&anatop->ana_misc1); - reg |= 0x80000000; - writel(reg, &anatop->ana_misc1); -} - int arch_cpu_init(void) { init_aips(); imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ - imx_set_vddpu_power_down(); #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index aede126..7202073 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -890,5 +890,4 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) -#define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13) #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 7f89865..f2ad6e9 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -663,28 +663,5 @@ struct wdog_regs { u16 wmcr; /* Miscellaneous Control */ }; -struct gpc_regs { - u32 ctrl; /* 0x000 */ - u32 pgr; /* 0x004 */ - u32 imr1; /* 0x008 */ - u32 imr2; /* 0x00c */ - u32 imr3; /* 0x010 */ - u32 imr4; /* 0x014 */ - u32 isr1; /* 0x018 */ - u32 isr2; /* 0x01c */ - u32 isr3; /* 0x020 */ - u32 isr4; /* 0x024 */ - u32 reserved1[0x86]; - u32 gpu_ctrl; /* 0x260 */ - u32 gpu_pupscr; /* 0x264 */ - u32 gpu_pdnscr; /* 0x268 */ - u32 gpu_sr; /* 0x26c */ - u32 reserved2[0xc]; - u32 cpu_ctrl; /* 0x2a0 */ - u32 cpu_pupscr; /* 0x2a4 */ - u32 cpu_pdnscr; /* 0x2a8 */ - u32 cpu_sr; /* 0x2ac */ -}; - #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ -- 1.8.1.2

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[U-Boot] [PATCH] sf: Fix entries for S25FL256S_256K and S25FL512S_256K
by Marek Vasut 16 Jan '14

16 Jan '14

Both of these chips have 256kB big sectors, thus the _256K suffix, compared to their _64K counterparts, which have 64kB sectors. Also, they have four times less sectors than their _64K counterparts. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- drivers/mtd/spi/sf_params.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Note: Would be nice if someone actually tested this fix as I go by the datasheet and by the old code that _was_ in U-Boot before the rework. diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index daf8fe7..5f63023 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -55,9 +55,9 @@ const struct spi_flash_params spi_flash_params_table[] = { {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP}, + {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP}, {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, - {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, RD_FULL, WR_QPP}, + {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP}, {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ -- 1.8.5.2

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[U-Boot] Prefetch abort exception
by Parimala Baggiri 16 Jan '14

16 Jan '14

Hello, I have added interrupt support for armv7 platform, by implementing the do_irq and irq_install_handler and arch_interrupt_init functions. Initially default_isr is the handler function installed for all the interrupts. >From my standalone application, I am enabling the interrupts and installing the handler to be called for my peripheral interrupt. If I don't install my handler, U-Boot executes default_isr successfully. If I use my handler, when the interrupt occurs I am getting the prefetch abort exception with the following dump prefetch abort pc : [<ebd78002>] lr : [<bff8f720>] sp : bfeef200 ip : bfeef358 fp : bfef1d48 r10: bfef1d78 r9 : 00000002 r8 : bfeeff58 r7 : bffac284 r6 : 60000153 r5 : bffbb5c0 r4 : 00000000 r3 : bffab29c r2 : 00000000 r1 : 000003e8 r0 : 8500178c Flags: nZCv IRQs off FIQs off Mode IRQ_32 Resetting CPU ... resetting ... U-Boot SPL 2013.01.-rc1-00003-g43ee87a-dirty (Jan 10 2014 - 16:04:35) OMAP4460 ES1.1 OMAP SD/MMC: 0 reading u-boot.img reading u-boot.img Can any one please help me to solve this?

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[U-Boot] [PATCH v2 1/6] mx6: soc: Staticize set_vddsoc()
by Fabio Estevam 16 Jan '14

16 Jan '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - None arch/arm/cpu/armv7/mx6/soc.c | 2 +- arch/arm/include/asm/arch-mx6/sys_proto.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index a390296..6cbade7 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -101,7 +101,7 @@ void init_aips(void) * Possible values are from 0.725V to 1.450V in steps of * 0.025V (25mV). */ -void set_vddsoc(u32 mv) +static void set_vddsoc(u32 mv) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 val, reg = readl(&anatop->reg_core); diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 8c21364..17125a6 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -29,8 +29,6 @@ u32 get_cpu_rev(void); const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); -void set_vddsoc(u32 mv); - /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() -- 1.8.1.2

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[U-Boot] Pull request v2: u-boot-sh/rmobile into u-boot-arm/master
by Nobuhiro Iwamatsu 16 Jan '14

16 Jan '14

Dear Albert Aribaud, Please pull u-boot-sh/rmobile into u-boot-arm/master. "spi: sh_qspi: Add header file that defines the address of registers" is SPI stuff. But I have permission to take from arm repository directly from Jagan is the maintainer of SPI. The following changes since commit bf46e7d8d134521301ff02b6d97e8998aa10a83d: Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' (2014-01-15 15:18:04 +0100) are available in the git repository at: git://git.denx.de/u-boot-sh.git rmobile for you to fetch changes up to c71b4dd2da0dcddabd7c29e6c3dc8a495d4bd928: arm: koelsch: Add support QSPI device and enable boot from SPI flash (2014-01-16 08:07:20 +0900) ---------------------------------------------------------------- Nobuhiro Iwamatsu (6): arm: koelsch: Disable TMU0 before OS boot arm: lager: Disable TMU0 before OS boot arm: rmobile: Add SH QSPI base register address spi: sh_qspi: Add header file that defines the address of registers arm: lager: Add support QSPI device and enable boot from SPI flash arm: koelsch: Add support QSPI device and enable boot from SPI flash arch/arm/include/asm/arch-rmobile/r8a7790.h | 1 + arch/arm/include/asm/arch-rmobile/r8a7791.h | 1 + board/renesas/koelsch/koelsch.c | 6 ++++++ board/renesas/lager/lager.c | 6 ++++++ drivers/spi/sh_qspi.c | 3 ++- include/configs/koelsch.h | 32 ++++++++++++++++++++++++++++---- include/configs/lager.h | 33 +++++++++++++++++++++++++++++---- -- Nobuhiro Iwamatsu iwamatsu at {nigauri.org / debian.org} GPG ID: 40AD1FA6

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[U-Boot] [PATCH v2] arm: exynos: change to use clrbits macro instead of readl/writel function
by Inha Song 16 Jan '14

16 Jan '14

Use setbits/clrbits macro instead of readl/writel function Signed-off-by: Inha Song <ideal.song(a)samsung.com> Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> Tested-by: Przemyslaw Marczak <p.marczak(a)samsung.com> --- Changes for v2: - Coding Style cleanup - add signed-off-by arch/arm/cpu/armv7/exynos/clock.c | 82 +++++++++---------------------------- 1 file changed, 20 insertions(+), 62 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 5bde9d1..6c589c9 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos4x12: set the mmc clock */ @@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) struct exynos4x12_clock *clk = (struct exynos4x12_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos5: set the mmc clock */ @@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos5: set the mmc clock */ @@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) struct exynos5420_clock *clk = (struct exynos5420_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val, shift; + unsigned int shift; /* * CLK_DIV_FSYS1 @@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) addr = (unsigned int)&clk->div_fsys1; shift = dev_index * 10; - val = readl(addr); - val &= ~(0x3ff << shift); - val |= (div & 0x3ff) << shift; - writel(val, addr); + clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); } /* get_lcd_clk: return lcd clock frequency */ @@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf); - cfg |= 0x6; - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0x9, 0x6); /* * CLK_GATE_IP_LCD0 @@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 0); /* * CLK_DIV_LCD0 @@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x1; - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xe, 0x1); } void exynos5_set_lcd_clk(void) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_disp1_0); - cfg &= ~(0xf); - cfg |= 0x6; - writel(cfg, &clk->src_disp1_0); + clrsetbits_le32(&clk->src_disp1_0, 0x9, 0x6); /* * CLK_GATE_IP_LCD0 @@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_disp1); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_disp1); + setbits_le32(&clk->gate_ip_disp1, 1 << 0); /* * CLK_DIV_LCD0 @@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x0; - writel(cfg, &clk->div_disp1_0); + clrbits_le32(&clk->div_disp1_0, 0xf); } void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_SRC_LCD0 @@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_SEL [12:15] * set mipi0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf << 12); - cfg |= (0x6 << 12); - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0x9 << 12, 0x6 << 12); /* * CLK_SRC_MASK_LCD0 @@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_MASK [12] * set src mask mipi0 0x1: Unmask */ - cfg = readl(&clk->src_mask_lcd0); - cfg |= (0x1 << 12); - writel(cfg, &clk->src_mask_lcd0); + setbits_le32(&clk->src_mask_lcd0, 0x1 << 12); /* * CLK_GATE_IP_LCD0 @@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for MIPI0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 3; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 3); /* * CLK_DIV_LCD0 @@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_PRE_RATIO [23:20] * set mipi ratio */ - cfg &= ~(0xf << 16); - cfg |= (0x1 << 16); - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xe << 16, 0x1 << 16); } /* -- 1.7.9.5

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