January 2014 - U-Boot

[U-Boot] [PATCH 3/3] sf: Use shortcut names
by Jagannadha Sutradharudu Teki 20 Jan '14

20 Jan '14

- SPI_FLASH -> SF - ARRAY_SLOW -> AS - ARRAY_FAST -> AF - DUAL_OUTPUT_FAST -> DOF - DUAL_IO_FAST - DIOF - QUAD_OUTPUT_FAST - QOF - QUAD_IO_FAST - QIOF Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> Cc: Marek Vasut <marex(a)denx.de> --- drivers/mtd/spi/sf_internal.h | 44 +++++++++++++++++++++---------------------- drivers/mtd/spi/sf_ops.c | 25 ++++++++++++------------ drivers/mtd/spi/sf_probe.c | 44 +++++++++++++++++++++---------------------- include/spi_flash.h | 14 +++++++------- 4 files changed, 63 insertions(+), 64 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 6bcd522..f959262 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -10,15 +10,15 @@ #ifndef _SF_INTERNAL_H_ #define _SF_INTERNAL_H_ -#define SPI_FLASH_3B_ADDR_LEN 3 -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) -#define SPI_FLASH_16MB_BOUN 0x1000000 +#define SF_INST_3BADDR 3 +#define SF_CMD_LEN (1 + SF_INST_3BADDR) +#define SF_16MB_BOUN 0x1000000 /* CFI Manufacture ID's */ -#define SPI_FLASH_CFI_MFR_SPANSION 0x01 -#define SPI_FLASH_CFI_MFR_STMICRO 0x20 -#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 -#define SPI_FLASH_CFI_MFR_WINBOND 0xef +#define SF_CFI_MFR_SPANSION 0x01 +#define SF_CFI_MFR_STMICRO 0x20 +#define SF_CFI_MFR_MACRONIX 0xc2 +#define SF_CFI_MFR_WINBOND 0xef /* Erase commands */ #define CMD_ERASE_4K 0x20 @@ -28,22 +28,22 @@ /* Write commands */ #define CMD_WRITE_STATUS 0x01 -#define CMD_PAGE_PROGRAM 0x02 +#define CMD_WRITE_PP 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 -#define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_WRITE_QPP 0x32 #define CMD_READ_STATUS1 0x35 #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 /* Read commands */ -#define CMD_READ_ARRAY_SLOW 0x03 -#define CMD_READ_ARRAY_FAST 0x0b -#define CMD_READ_DUAL_OUTPUT_FAST 0x3b -#define CMD_READ_DUAL_IO_FAST 0xbb -#define CMD_READ_QUAD_OUTPUT_FAST 0x6b -#define CMD_READ_QUAD_IO_FAST 0xeb +#define CMD_READ_AS 0x03 +#define CMD_READ_AF 0x0b +#define CMD_READ_DOF 0x3b +#define CMD_READ_DIOF 0xbb +#define CMD_READ_QOF 0x6b +#define CMD_READ_QIOF 0xeb #define CMD_READ_ID 0x9f /* Bank addr access commands */ @@ -55,15 +55,15 @@ #endif /* Common status */ -#define STATUS_WIP (1 << 0) -#define STATUS_QEB_WINSPAN (1 << 1) -#define STATUS_QEB_MXIC (1 << 6) -#define STATUS_PEC (1 << 7) +#define STATUS_WIP 1 << 0 +#define STATUS_QEB_WINSPAN 1 << 1 +#define STATUS_QEB_MXIC 1 << 6 +#define STATUS_PEC 1 << 7 /* Flash timeout values */ -#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) -#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) -#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) +#define SF_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) +#define SF_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) +#define SF_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) /* SST specific */ #ifdef CONFIG_SPI_FLASH_SST diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 0d87e1b..e8e70bb 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -119,7 +119,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) u8 bank_sel; int ret; - bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); + bank_sel = offset / (SF_16MB_BOUN << flash->shift); ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); if (ret) { @@ -207,11 +207,11 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, size_t cmd_len, const void *buf, size_t buf_len) { struct spi_slave *spi = flash->spi; - unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; + unsigned long timeout = SF_PROG_TIMEOUT; int ret; if (buf == NULL) - timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; + timeout = SF_PAGE_ERASE_TIMEOUT; ret = spi_claim_bus(flash->spi); if (ret) { @@ -233,9 +233,8 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, ret = spi_flash_cmd_wait_ready(flash, timeout); if (ret < 0) { - debug("SF: write %s timed out\n", - timeout == SPI_FLASH_PROG_TIMEOUT ? - "program" : "page erase"); + debug("SF: write %s timed out\n", buf != NULL ? + "program" : "page erase"); return ret; } @@ -247,7 +246,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { u32 erase_size, erase_addr; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SF_CMD_LEN]; int ret = -1; erase_size = flash->erase_size; @@ -293,7 +292,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, unsigned long byte_addr, page_size; u32 write_addr; size_t chunk_len, actual; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SF_CMD_LEN]; int ret = -1; page_size = flash->page_size; @@ -380,7 +379,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return 0; } - cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + cmdsz = SF_CMD_LEN + flash->dummy_byte; cmd = calloc(1, cmdsz); cmd[0] = flash->read_cmd; @@ -396,8 +395,8 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, if (bank_sel < 0) return ret; #endif - remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * - (bank_sel + 1)) - offset; + remain_len = ((SF_16MB_BOUN << flash->shift) * (bank_sel + 1)) - + offset; if (len < remain_len) read_len = len; else @@ -441,7 +440,7 @@ static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) if (ret) return ret; - return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + return spi_flash_cmd_wait_ready(flash, SF_PROG_TIMEOUT); } int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, @@ -488,7 +487,7 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, break; } - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + ret = spi_flash_cmd_wait_ready(flash, SF_PROG_TIMEOUT); if (ret) break; diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 003f635..ae11999 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -21,11 +21,11 @@ DECLARE_GLOBAL_DATA_PTR; /* Read commands array */ static u8 spi_read_cmds_array[] = { - CMD_READ_ARRAY_SLOW, - CMD_READ_DUAL_OUTPUT_FAST, - CMD_READ_DUAL_IO_FAST, - CMD_READ_QUAD_OUTPUT_FAST, - CMD_READ_QUAD_IO_FAST, + CMD_READ_AS, + CMD_READ_DOF, + CMD_READ_DIOF, + CMD_READ_QOF, + CMD_READ_QIOF, }; #ifdef CONFIG_SPI_FLASH_MACRONIX @@ -76,16 +76,16 @@ static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { #ifdef CONFIG_SPI_FLASH_MACRONIX - case SPI_FLASH_CFI_MFR_MACRONIX: + case SF_CFI_MFR_MACRONIX: return spi_flash_set_qeb_mxic(flash); #endif #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) - case SPI_FLASH_CFI_MFR_SPANSION: - case SPI_FLASH_CFI_MFR_WINBOND: + case SF_CFI_MFR_SPANSION: + case SF_CFI_MFR_WINBOND: return spi_flash_set_qeb_winspan(flash); #endif #ifdef CONFIG_SPI_FLASH_STMICRO - case SPI_FLASH_CFI_MFR_STMICRO: + case SF_CFI_MFR_STMICRO: debug("SF: QEB is volatile for %02x flash\n", idcode0); return 0; #endif @@ -141,13 +141,13 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->dual_flash = SF_PARALLEL; #endif /* Assign spi_flash ops */ + flash->read = spi_flash_cmd_read_ops; + flash->erase = spi_flash_cmd_erase_ops; flash->write = spi_flash_cmd_write_ops; #ifdef CONFIG_SPI_FLASH_SST if (params->flags & SST_WP) flash->write = sst_write_wp; #endif - flash->erase = spi_flash_cmd_erase_ops; - flash->read = spi_flash_cmd_read_ops; /* Compute the flash size */ flash->shift = (flash->dual_flash & SF_PARALLEL) ? 1 : 0; @@ -178,20 +178,20 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->read_cmd = cmd; } else { /* Go for default supported read cmd */ - flash->read_cmd = CMD_READ_ARRAY_FAST; + flash->read_cmd = CMD_READ_AF; } /* Not require to look for fastest only two write cmds yet */ if (params->flags & WR_QPP && flash->spi->mode_bits & SPI_TX_QPP) - flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; + flash->write_cmd = CMD_WRITE_QPP; else /* Go for default supported write cmd */ - flash->write_cmd = CMD_PAGE_PROGRAM; + flash->write_cmd = CMD_WRITE_PP; /* Set the quad enable bit - only for quad commands */ - if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || - (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || - (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { + if ((flash->read_cmd == CMD_READ_QOF) || + (flash->read_cmd == CMD_READ_QIOF) || + (flash->write_cmd == CMD_WRITE_QPP)) { if (spi_flash_set_qeb(flash, idcode[0])) { debug("SF: Fail to set QEB for %02x\n", idcode[0]); return NULL; @@ -207,10 +207,10 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, * data all go on single line irrespective of command. */ switch (flash->read_cmd) { - case CMD_READ_QUAD_IO_FAST: + case CMD_READ_QIOF: flash->dummy_byte = 2; break; - case CMD_READ_ARRAY_SLOW: + case CMD_READ_AS: flash->dummy_byte = 0; break; default: @@ -227,7 +227,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, /* Configure the BAR - discover bank cmds and read current bank */ #ifdef CONFIG_SPI_FLASH_BAR u8 curr_bank = 0; - if (flash->size > SPI_FLASH_16MB_BOUN) { + if (flash->size > SF_16MB_BOUN) { flash->bank_read_cmd = (idcode[0] == 0x01) ? CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR; flash->bank_write_cmd = (idcode[0] == 0x01) ? @@ -335,9 +335,9 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi) #endif #ifndef CONFIG_SPI_FLASH_BAR if (((flash->dual_flash == SF_SINGLE) && - (flash->size > SPI_FLASH_16MB_BOUN)) || + (flash->size > SF_16MB_BOUN)) || ((flash->dual_flash > SF_SINGLE) && - (flash->size > SPI_FLASH_16MB_BOUN << 1))) { + (flash->size > SF_16MB_BOUN << 1))) { puts("SF: Warning - Only lower 16MiB accessible,"); puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } diff --git a/include/spi_flash.h b/include/spi_flash.h index b4b2f9b..283c569 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -27,14 +27,14 @@ /* Enum list - Full read commands */ enum spi_read_cmds { - ARRAY_SLOW = 1 << 0, - DUAL_OUTPUT_FAST = 1 << 1, - DUAL_IO_FAST = 1 << 2, - QUAD_OUTPUT_FAST = 1 << 3, - QUAD_IO_FAST = 1 << 4, + SF_AS = 1 << 0, + SF_DOF = 1 << 1, + SF_DIOF = 1 << 2, + SF_QOF = 1 << 3, + SF_QIOF = 1 << 4, }; -#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST -#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST +#define RD_EXTN SF_AS | SF_DOF | SF_DIOF +#define RD_FULL RD_EXTN | SF_QOF | SF_QIOF /* Dual SPI flash memories */ enum spi_dual_flash { -- 1.8.3

4 3

[U-Boot] [PATCH] ARM: tegra20: Add a missing entry in the pullid enum
by Alban Bedel 20 Jan '14

20 Jan '14

It seems two entries were merged in one when this file has been created. The GPSLXAU entries is obviously a mix of GPU and SLXA which are next to each other according to the datasheet. Moreover it can be noticed because the APB_MISC_PP_PULLUPDOWN_REG_B_0 register only have 15 entries instead of 16. Also fix the pin group descriptions that were using these buggy entries. In particular SLXA that needed to used CRTP to actually write the SLXA register. Signed-off-by: Alban Bedel <alban.bedel(a)avionic-design.de> --- arch/arm/cpu/tegra20-common/pinmux.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c index a65e991..5c80ed9 100644 --- a/arch/arm/cpu/tegra20-common/pinmux.c +++ b/arch/arm/cpu/tegra20-common/pinmux.c @@ -190,7 +190,8 @@ enum pmux_pullid { PUCTL_SPDI, PUCTL_SPDO, - PUCTL_GPSLXAU, + PUCTL_GPU, + PUCTL_SLXA, PUCTL_CRTP, PUCTL_SLXC, PUCTL_SLXD, @@ -333,8 +334,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1), PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1), - PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, - GPSLXAU), + PIN(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4), PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE), PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4), PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB), @@ -356,7 +356,7 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = { PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC), PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM), PIN_RESERVED, - PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP), + PIN(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE), PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4), PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4), PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE), -- 1.8.5.2

2 2

[U-Boot] [PATCH v2] board_r - fixup functions table after relocation
by Alexey Brodkin 20 Jan '14

20 Jan '14

This is only required for "PIC" relocation and doesn't apply to modern "PIE" relocation which does data relocation as well as code. "init_sequence_r" is just an array that consists of compile-time adresses of init functions. Since this is basically an array of integers (pointers to "void" to be more precise) it won't be modified during relocation - it will be just copied to new location as it is. As a consequence on execution after relocation "initcall_run_list" will be jumping to pre-relocation addresses. As long as we don't overwrite pre-relocation memory area init calls are executed correctly. But still it is dangerous because after relocation we don't expect initially used memory to stay untouched. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Tom Rini <trini(a)ti.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Doug Anderson <dianders(a)chromium.org> Cc: Thomas Langer <thomas.langer(a)lantiq.com> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Changes to v1: * Added CONFIG_NEEDS_MANUAL_RELOC wrapper so this change only applies to "PIC" relocation. --- common/board_r.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/common/board_r.c b/common/board_r.c index 86ca1cb..3462590 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -903,9 +903,16 @@ init_fnc_t init_sequence_r[] = { void board_init_r(gd_t *new_gd, ulong dest_addr) { + int i; #ifndef CONFIG_X86 gd = new_gd; #endif + +#ifdef CONFIG_NEEDS_MANUAL_RELOC + for (i = 0; i < sizeof(init_sequence_r)/sizeof(void *); i++) + init_sequence_r[i] += gd->reloc_off; +#endif + if (initcall_run_list(init_sequence_r)) hang(); -- 1.8.4.2

2 1

[U-Boot] [PATCH 1/2][v2] powerpc/mpc85xx: SECURE BOOT- add version info for ISBC
by Aneesh Bansal 20 Jan '14

20 Jan '14

T4/B4 SoC's have a different version of ISBC. The secure boot functionality is different with the new version of ISBC compared to the earlier SoC's. So the version information is added in file config_mpc85xx.h Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- README | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 9 +++++++++ 2 files changed, 12 insertions(+) Changes from v1: Updated the commit message diff --git a/README b/README index aea82be..6c3a8d1 100644 --- a/README +++ b/README @@ -423,6 +423,9 @@ The following options need to be configured: CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. + CONFIG_SYS_FSL_ISBC_VER + This value indicates the major ISBC version on the platform. + CONFIG_SYS_FSL_SINGLE_SOURCE_CLK Single Source Clock is clocking mode present in some of FSL SoC's. In this mode, a single differential clock is used to supply diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 54ce2f0..ba5b6fe 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -151,6 +151,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ISBC_VER 1 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 /* P1011 is single core version of P1020 */ @@ -383,6 +384,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004849 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -421,6 +423,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005812 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -470,6 +473,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005812 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -504,6 +508,7 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_P5040) #define CONFIG_SYS_PPC64 @@ -536,6 +541,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #define CONFIG_SYS_FSL_ERRATUM_A005812 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_BSC9131) #define CONFIG_MAX_CPUS 1 @@ -575,6 +581,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define CONFIG_E6500 @@ -631,6 +638,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X +#define CONFIG_SYS_FSL_ISBC_VER 2 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) #define CONFIG_E6500 @@ -657,6 +665,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ISBC_VER 2 #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 -- 1.8.1.4

2 1

[U-Boot] Uboot_Header_Modification_by_CVS
by Arun K. Varghese 20 Jan '14

20 Jan '14

Hi, Issue. ------- 1) Downloaded u-boot-2010.09 source code. (u-boot-2010.09.tar.bz2<http://ftp.denx.de/pub/u-boot/u-boot-2010.09.tar.bz2>) 2) Some files, have version & header information along with the source code. Ex: 1) In u-boot-2010.09/arch/arm/cpu/ixp/npe/include/IxI2cDrv.h * @version $Revision: 0.1 $ 2) In u-boot-2010.09/arch/i386/cpu/sc520/sc520_asm.S * $Revision: 1.2 $ * $Date: 1999/09/22 12:49:33 $ * $Author: chipf $ 3) When I do a check in for these files, using CVS, these header information is changed. CVS is automatically modifying these headers. Eg : In u-boot-2010.09/arch/i386/cpu/sc520/sc520_asm.S * $Revision: 1.2 $ * $Date: 1999/09/22 12:49:33 $ * $Author: chipf $ If I do a check in, it will be changed to * $Revision: 1.1.1.2 $ * $Date: 2013/12/16 12:49:33 $ * $Author: Arun $ Doubts --------- 1. Why only few files have these kind of header information in Uboot repository ? 2. If I do a check in via CVS, the headers will be modified, So will it be a violation to GPL ? 3. If it is a Violation , please help me with a solution . Thanks & Regards, Arun

3 2

[U-Boot] [PATCH v1 1/2] i2c: zynq: Support for 0-length register address
by Michal Simek 20 Jan '14

20 Jan '14

From: Michael Burr <michael.burr(a)logicpd.com> Fixed bug with alen == 0 in 'i2c_write', 'i2c_read' Further minor corrections: - Write 'address' register before 'data' register. - Write 'transfer_size' register before 'address' register. Signed-off-by: Michael Burr <michael.burr(a)logicpd.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v1: - Based on original thread from Michael Burr http://lists.denx.de/pipermail/u-boot/2013-October/165060.html - MS rebase on latest&greatest drivers/i2c/zynq_i2c.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index 70a9aea..a9df838 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -189,20 +189,37 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, * Temporarily disable restart (by clearing hold) * It doesn't seem to work. */ + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); + writel(0xFF, &zynq_i2c->interrupt_status); + if (alen) { + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); + writel(dev, &zynq_i2c->address); + while (alen--) + writel(addr >> (8*alen), &zynq_i2c->data); + + /* Wait for the address to be sent */ + if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + /* Release the bus */ + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + debug("Device acked address\n"); + } + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW | ZYNQ_I2C_CONTROL_HOLD); writel(0xFF, &zynq_i2c->interrupt_status); - while (alen--) - writel(addr >> (8*alen), &zynq_i2c->data); - writel(dev, &zynq_i2c->address); - - /* Wait for the address to be sent */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; + if (alen) { + while (alen--) + writel(addr >> (8*alen), &zynq_i2c->data); + /* Start the tranfer */ + if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + /* Release the bus */ + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + debug("Device acked address\n"); } - debug("Device acked address\n"); setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | ZYNQ_I2C_CONTROL_RW); -- 1.8.2.3

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[U-Boot] [PATCH 2/2] SECURE BOOT: Add secure boot target for B4860QDS
by Aneesh Bansal 20 Jan '14

20 Jan '14

Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 28 +++++++++++++++++++++++----- arch/powerpc/cpu/mpc85xx/start.S | 3 ++- arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++++++ boards.cfg | 1 + 4 files changed, 32 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b31efb7..de1116b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -125,17 +125,15 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) #endif #ifdef CONFIG_SYS_FSL_CPC -static void enable_cpc(void) + +#ifdef CONFIG_RAMBOOT_PBL || defined(CONFIG_SECURE_HKAREA_CPC) +static void disable_cpc_sram(void) { int i; - u32 size = 0; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { - u32 cpccfg0 = in_be32(&cpc->cpccfg0); - size += CPC_CFG0_SZ_K(cpccfg0); -#ifdef CONFIG_RAMBOOT_PBL if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); @@ -150,8 +148,21 @@ static void enable_cpc(void) out_be32(&cpc->cpccsr0, 0); out_be32(&cpc->cpcsrcr0, 0); } + } +} #endif +static void enable_cpc(void) +{ + int i; + u32 size = 0; + + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + u32 cpccfg0 = in_be32(&cpc->cpccfg0); + size += CPC_CFG0_SZ_K(cpccfg0); + #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); #endif @@ -250,6 +261,10 @@ void cpu_init_f (void) law = find_law(CONFIG_SYS_PBI_FLASH_BASE); if (law.index != -1) disable_law(law.index); + +#if defined(CONFIG_SECURE_HKAREA_CPC) + disable_cpc_sram(); +#endif #endif #ifdef CONFIG_CPM2 @@ -550,6 +565,9 @@ skip_l2: puts("disabled\n"); #endif +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif enable_cpc(); #ifndef CONFIG_SYS_FSL_NO_SERDES diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index db84d10..5440bf5 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -117,7 +117,8 @@ _start_e500: #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ + !defined(CONFIG_E6500) /* ISBC uses L2 as stack. * Disable L2 cache here so that u-boot can enable it later * as part of it's normal flow diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 4c7f0b1..db124df 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -15,5 +15,11 @@ #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#if CONFIG_SYS_FSL_ISBC_VER > 1 +#define CONFIG_SECURE_HKAREA_CPC +#undef CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif + #endif #endif diff --git a/boards.cfg b/boards.cfg index 928e222..1d6a14c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -780,6 +780,7 @@ Active powerpc mpc85xx - freescale b4860qds Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - -- 1.8.1.4

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[U-Boot] changing default serial console from UART0 to UART 1
by pshambhu 20 Jan '14

20 Jan '14

Hi, I am interested in changing the default serial console from UART 0 to UART 1, which are the files need to be changed in u-boot code and what changes are done , so that with new u-boot , the console should be on UART1. Thanks in advance. Thanks and Regards Pradeep S -- View this message in context: http://u-boot.10912.n7.nabble.com/changing-default-serial-console-from-UART… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] imx6 Solo and LAN8720
by Andy Ng 19 Jan '14

19 Jan '14

Dear colleagues, I have setup a LAN8720 phy for my imx6Solo/DL custom board but no packets coming out. I can see 50MHz going into the phy from the REF_OUT Pin of the SOLO, I can read the phy ID using the u-boot MDIO commands but when I do ftp or ping nothing comes out. mx6s > mdio list FEC: 0 - SMSC LAN8710/LAN8720 <--> FEC For this design I am using ENET_ANATOP_ETHERNET_REF_OUT. Have you used LAN8720 in a similar configuration: The pinmux i have is the following: /* * Ethernet PINS for LAN8720 */ static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), /* LAN8720 PHY Reset */ MX6_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL), /* Note: The INT is not handled */ MX6_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL), }; Where ENET_PAT_CTRL is set as: #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) And the Ethernet configuration in the config file as follows: /* Ethernet Configuration */ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_FEC_MXC #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC In the board file: #ifdef CONFIG_FEC_MXC /* * Initialise the pins, and reset the PHY */ static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); /* Reset LAN8720 PHY */ gpio_direction_output(ETH_PHY_RESET, 1); udelay(150); gpio_set_value(ETH_PHY_RESET, 0); udelay(150); gpio_set_value(ETH_PHY_RESET, 1); udelay(200); } int enable_fec_anatop_clock(void) { u32 reg = 0; s32 timeout = 100000; struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; reg = readl(&anatop->pll_enet); if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; writel(reg, &anatop->pll_enet); while (timeout--) { if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) break; } if (timeout < 0) return -ETIMEDOUT; } /* Enable FEC clock */ reg |= BM_ANADIG_PLL_ENET_ENABLE; reg &= ~BM_ANADIG_PLL_ENET_BYPASS; writel(reg, &anatop->pll_enet); return 0; } int board_eth_init(bd_t *bis) { int ret; setup_iomux_enet(); ret = cpu_eth_init(bis); if (ret) { printf("FEC MXC: %s:failed\n", __func__); return ret; } return 0; } static int setup_fec(void) { struct iomuxc_base_regs *iomuxc_regs = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; int ret; /* set gpr1[21] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK, 1 << 21); ret = enable_fec_anatop_clock(); if (ret) return ret; return 0; } #endif int board_late_init(void) { #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif return 0; } int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; /* Read the board ID */ /* Setup the FEC clock */ #ifdef CONFIG_FEC_MXC setup_fec(); #endif return 0; } The clock gating are as: /* set the default clock gate to save power */ DATA 4, CCM_CCGR0, 0x00C03F3F DATA 4, CCM_CCGR1, 0x0030FC03 DATA 4, CCM_CCGR2, 0x0FFFC000 DATA 4, CCM_CCGR3, 0x3FF00000 DATA 4, CCM_CCGR4, 0x00FFF300 DATA 4, CCM_CCGR5, 0x0F0000C3 DATA 4, CCM_CCGR6, 0x000003FF /* enable AXI cache for VDOA/VPU/IPU */ DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4, MX6_IOMUXC_GPR6, 0x007F007F DATA 4, MX6_IOMUXC_GPR7, 0x007F007F /* * Setup CCM_CCOSR register as follows: * * cko1_en = 1 --> CKO1 enabled * cko1_div = 111 --> divide by 8 * cko1_sel = 1011 --> ahb_clk_root * * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz */ DATA 4, CCM_CCOSR, 0x000000fb The ethaddr: ethaddr=02:24:08:32:68:08 Any assistance will be very much appreciated. Thank you. A

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[U-Boot] [PATCH 0/3] arm: vf610: Add QSPI support for VF610
by Alison Wang 19 Jan '14

19 Jan '14

This series contain QSPI support for Freescale Vybrid VF610. The QSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. QSPI has a Look-update-table(LUT) which consists of a number of pre-programmed sequences. Each sequence is basically a sequence of instruction-operand pairs which when executed sequentially generates a valid serial flash transaction. This driver has been tested on VF610TWR. ---------------------------------------------------------------- Alison Wang (3): arm: imx: Add two macros for VF610 in IOMUX_PAD structure arm: vf610: Add QSPI support for VF610TWR arm: vf610: Add QSPI driver support arch/arm/include/asm/arch-vf610/crm_regs.h | 11 ++- arch/arm/include/asm/arch-vf610/imx-regs.h | 4 +- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 14 +++ arch/arm/include/asm/imx-common/iomux-v3.h | 2 + board/freescale/vf610twr/vf610twr.c | 29 ++++++- drivers/spi/Makefile | 1 + drivers/spi/fsl_qspi.c | 482 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/fsl_qspi.h | 127 +++++++++++++++++++++++++++ include/configs/vf610twr.h | 11 +++ 9 files changed, 677 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/fsl_qspi.c create mode 100644 drivers/spi/fsl_qspi.h

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