January 2014 - U-Boot

[U-Boot] [PATCH v2] Remove obsolete _LINUX_CONFIG_H macro
by Masahiro Yamada 27 Jan '14

27 Jan '14

Commit 643aae1406c93ddc64fcf8c136b47cdffd9c8ccd deleted include/linux/config.h but missed to delete _LINUX_CONFIG_H macro. It is no longer used at all. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- Changes in v2: - Fix a typo in the subject: s/obsolte/obsolete/ arch/powerpc/cpu/mpc5xx/start.S | 1 - arch/powerpc/cpu/mpc5xxx/start.S | 1 - arch/powerpc/cpu/mpc824x/start.S | 2 -- arch/powerpc/cpu/mpc8260/kgdb.S | 1 - arch/powerpc/cpu/mpc8260/start.S | 1 - arch/powerpc/cpu/mpc83xx/start.S | 1 - arch/powerpc/cpu/mpc85xx/release.S | 2 -- arch/powerpc/cpu/mpc85xx/start.S | 2 -- arch/powerpc/cpu/mpc8xx/kgdb.S | 1 - arch/powerpc/cpu/mpc8xx/start.S | 1 - arch/powerpc/cpu/ppc4xx/dcr.S | 2 -- arch/powerpc/cpu/ppc4xx/kgdb.S | 1 - arch/powerpc/cpu/ppc4xx/start.S | 2 -- board/cray/L1/init.S | 2 -- board/csb272/init.S | 2 -- board/csb472/init.S | 2 -- board/mpl/mip405/init.S | 1 - board/mpl/pip405/init.S | 1 - board/sc3/init.S | 2 -- board/w7o/init.S | 2 -- board/w7o/post1.S | 2 -- include/common.h | 3 --- 22 files changed, 35 deletions(-) diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S index 92f956d..22fb274 100644 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ b/arch/powerpc/cpu/mpc5xx/start.S @@ -20,7 +20,6 @@ #include <version.h> #define CONFIG_5xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 517b580..84ab41e 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -15,7 +15,6 @@ #include <version.h> #define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index 6f397a4..b1fb062 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -26,8 +26,6 @@ #include <mpc824x.h> #include <version.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S index 5a298f9..dd04d6b 100644 --- a/arch/powerpc/cpu/mpc8260/kgdb.S +++ b/arch/powerpc/cpu/mpc8260/kgdb.S @@ -10,7 +10,6 @@ #include <version.h> #define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index 1269291..65510fa 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -15,7 +15,6 @@ #include <version.h> #define CONFIG_8260 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index b4fafe6..a487bcc 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -20,7 +20,6 @@ #include <version.h> #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index c15e83b..fcfba7e 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -10,8 +10,6 @@ #include <mpc85xx.h> #include <version.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index db84d10..dbbd8e5 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -17,8 +17,6 @@ #include <mpc85xx.h> #include <version.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S index ea27d59..ac1fe8f 100644 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ b/arch/powerpc/cpu/mpc8xx/kgdb.S @@ -10,7 +10,6 @@ #include <version.h> #define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 9869bbd..99cafbd 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -27,7 +27,6 @@ #include <version.h> #define CONFIG_8xx 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S index 0d99391..6b13528 100644 --- a/arch/powerpc/cpu/ppc4xx/dcr.S +++ b/arch/powerpc/cpu/ppc4xx/dcr.S @@ -10,8 +10,6 @@ #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S index dbc4a6c..f274c5d 100644 --- a/arch/powerpc/cpu/ppc4xx/kgdb.S +++ b/arch/powerpc/cpu/ppc4xx/kgdb.S @@ -10,7 +10,6 @@ #include <version.h> #define CONFIG_405GP 1 /* needed for Linux kernel header files */ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 38bbc5a..e72c37c 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -31,8 +31,6 @@ #include <asm/ppc4xx.h> #include <version.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index 44c688d..d4723c7 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -22,8 +22,6 @@ /*-----------------------------------------------------------------------------#include <config.h> */ #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/csb272/init.S b/board/csb272/init.S index 5961978..bf1d986 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -4,8 +4,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/csb472/init.S b/board/csb472/init.S index 1ebc9ea..7383a70 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -4,8 +4,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 642f17c..2ea2e29 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -19,7 +19,6 @@ * Bank 6 - not used * Bank 7 - PLD Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <configs/MIP405.h> #include <ppc_asm.tmpl> diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 95fed34..292393e 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -19,7 +19,6 @@ * Bank 6 - used to switch on the 12V for the Multipurpose socket * Bank 7 - Config Register *-----------------------------------------------------------------------------*/ -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <configs/PIP405.h> #include <ppc_asm.tmpl> diff --git a/board/sc3/init.S b/board/sc3/init.S index 46323d2..097aa4a 100644 --- a/board/sc3/init.S +++ b/board/sc3/init.S @@ -4,8 +4,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/w7o/init.S b/board/w7o/init.S index 54eda32..dfde149 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -4,8 +4,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/w7o/post1.S b/board/w7o/post1.S index 7a411a4..aae5387 100644 --- a/board/w7o/post1.S +++ b/board/w7o/post1.S @@ -13,8 +13,6 @@ #include <config.h> #include <asm/ppc4xx.h> -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/include/common.h b/include/common.h index d49c514..d5ebb25 100644 --- a/include/common.h +++ b/include/common.h @@ -8,9 +8,6 @@ #ifndef __COMMON_H_ #define __COMMON_H_ 1 -#undef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - #ifndef __ASSEMBLY__ /* put C only stuff in this section */ typedef unsigned char uchar; -- 1.8.3.2

2 1

[U-Boot] [PATCH] cosmetic: tools/scripts/README: insert only one space between words
by Masahiro Yamada 27 Jan '14

27 Jan '14

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- tools/scripts/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/scripts/README b/tools/scripts/README index dbc4425..c3b491a 100644 --- a/tools/scripts/README +++ b/tools/scripts/README @@ -8,7 +8,7 @@ This directory contains scripts that help to perform certain actions that need to be done frequently when working with U-Boot. -They are meant as EXAMPLE code, so it is very likely that you will +They are meant as EXAMPLE code, so it is very likely that you will have to modify them before use. -- 1.8.3.2

2 2

[U-Boot] [PATCH] tools: move kermit files to tools/kermit directory
by Masahiro Yamada 27 Jan '14

27 Jan '14

The script files, define2mk.sed and make-asm-offsets are used to create autoconf.mk and asm-offsets.h while build. Whereas README, dot.kermrc, flash_param, send_cmd, send_image are files useful for kermit. We should not put files which have the totally different purpose into the same directory. This commit creates a new directory, tools/kermit, and move kermit files into it. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Wolfgang Denk <wd(a)denx.de> --- Please apply the following first to avoid a conflict: cosmetic: tools/scripts/README: insert only one space between words http://patchwork.ozlabs.org/patch/304887/ (I should have posted a patch series. Sorry.) tools/{scripts => kermit}/README | 0 tools/{scripts => kermit}/dot.kermrc | 0 tools/{scripts => kermit}/flash_param | 0 tools/{scripts => kermit}/send_cmd | 0 tools/{scripts => kermit}/send_image | 0 5 files changed, 0 insertions(+), 0 deletions(-) rename tools/{scripts => kermit}/README (100%) rename tools/{scripts => kermit}/dot.kermrc (100%) rename tools/{scripts => kermit}/flash_param (100%) rename tools/{scripts => kermit}/send_cmd (100%) rename tools/{scripts => kermit}/send_image (100%) diff --git a/tools/scripts/README b/tools/kermit/README similarity index 100% rename from tools/scripts/README rename to tools/kermit/README diff --git a/tools/scripts/dot.kermrc b/tools/kermit/dot.kermrc similarity index 100% rename from tools/scripts/dot.kermrc rename to tools/kermit/dot.kermrc diff --git a/tools/scripts/flash_param b/tools/kermit/flash_param similarity index 100% rename from tools/scripts/flash_param rename to tools/kermit/flash_param diff --git a/tools/scripts/send_cmd b/tools/kermit/send_cmd similarity index 100% rename from tools/scripts/send_cmd rename to tools/kermit/send_cmd diff --git a/tools/scripts/send_image b/tools/kermit/send_image similarity index 100% rename from tools/scripts/send_image rename to tools/kermit/send_image -- 1.8.3.2

2 1

[U-Boot] [PATCH] lib: fix return codes when CONFIG_SYS_VSNPRINTF is enabled
by Darwin Rambo 27 Jan '14

27 Jan '14

When CONFIG_SYS_VSNPRINTF is enabled, it protects print operations such as sprintf, snprintf, vsnprintf, etc., from buffer overflows. But vsnprintf_internal includes the terminating NULL character in the calculation of number of characters written. This affects sprintf and snprintf return values. Fix this issue by setting pointer 'str' back to the location of the '\0'. Signed-off-by: Darwin Rambo <drambo(a)broadcom.com> Reviewed-by: Steve Rae <srae(a)broadcom.com> --- lib/vsprintf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 82e5c13..60874da 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -750,6 +750,7 @@ repeat: ADDCH(str, '\0'); if (str > end) end[-1] = '\0'; + --str; } #else *str = '\0'; -- 1.7.9.5

2 1

[U-Boot] [PATCH] lib: time: add weak timer_init() function
by Darwin Rambo 27 Jan '14

27 Jan '14

If timer_init() is made a weak stub function, then it allows us to remove several empty timer_init functions for those boards that already have a timer initialized when u-boot starts. Architectures that use the timer framework may also remove the need for timer.c. Signed-off-by: Darwin Rambo <drambo(a)broadcom.com> Reviewed-by: Tim Kryger <tim.kryger(a)linaro.org> --- arch/arm/cpu/arm1176/bcm2835/timer.c | 5 ----- arch/arm/cpu/sa1100/timer.c | 5 ----- board/armltd/vexpress/vexpress_common.c | 5 ----- board/nvidia/common/board.c | 11 ----------- board/sandbox/sandbox/sandbox.c | 5 ----- lib/time.c | 5 +++++ 6 files changed, 5 insertions(+), 31 deletions(-) diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c index 2edd671..017907c 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/cpu/arm1176/bcm2835/timer.c @@ -18,11 +18,6 @@ #include <asm/io.h> #include <asm/arch/timer.h> -int timer_init(void) -{ - return 0; -} - ulong get_timer_us(ulong base) { struct bcm2835_timer_regs *regs = diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c index 4b981e4..0a0006b 100644 --- a/arch/arm/cpu/sa1100/timer.c +++ b/arch/arm/cpu/sa1100/timer.c @@ -13,11 +13,6 @@ #include <common.h> #include <SA-1100.h> -int timer_init (void) -{ - return 0; -} - ulong get_timer (ulong base) { return get_timer_masked (); diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index da5cb01..cb2de2f 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -119,11 +119,6 @@ void dram_init_banksize(void) get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); } -int timer_init(void) -{ - return 0; -} - /* * Start timer: * Setup a 32 bit timer, running at 1KHz diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 1972527..e650fed 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -48,17 +48,6 @@ const struct tegra_sysinfo sysinfo = { CONFIG_TEGRA_BOARD_STRING }; -#ifndef CONFIG_SPL_BUILD -/* - * Routine: timer_init - * Description: init the timestamp and lastinc value - */ -int timer_init(void) -{ - return 0; -} -#endif - void __pin_mux_usb(void) { } diff --git a/board/sandbox/sandbox/sandbox.c b/board/sandbox/sandbox/sandbox.c index 65dcce8..95efaff 100644 --- a/board/sandbox/sandbox/sandbox.c +++ b/board/sandbox/sandbox/sandbox.c @@ -23,11 +23,6 @@ unsigned long timer_read_counter(void) return os_get_nsec() / 1000; } -int timer_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; diff --git a/lib/time.c b/lib/time.c index 8085aa4..73c3b6a 100644 --- a/lib/time.c +++ b/lib/time.c @@ -60,6 +60,11 @@ static unsigned long long notrace tick_to_time(uint64_t tick) return tick; } +int __weak timer_init(void) +{ + return 0; +} + ulong __weak get_timer(ulong base) { return tick_to_time(get_ticks()) - base; -- 1.7.9.5

2 1

[U-Boot] [PATCH v2] boards.cfg: Keep the entries sorted
by Fabio Estevam 27 Jan '14

27 Jan '14

From: Fabio Estevam <fabio.estevam(a)freescale.com> Run "tools/reformat.py -i -d '-' -s 8 <boards.cfg >boards0.cfg && mv boards0.cfg boards.cfg" in order to keep the entries sorted. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v2: - Rebased against top of head master boards.cfg | 56 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/boards.cfg b/boards.cfg index 07ae05b..2dfd2b4 100644 --- a/boards.cfg +++ b/boards.cfg @@ -43,6 +43,7 @@ # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers ########################################################################################################### +Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua(a)phytium.com.cn> Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij(a)linaro.org> Active arm arm1136 mx31 - - imx31_phycore - - Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd(a)denx.de> @@ -136,11 +137,11 @@ Active arm arm926ejs at91 eukrea cpu9260 Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev <iliev(a)ronetix.at> Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev <iliev(a)ronetix.at> Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev(a)ronetix.at> -Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig(a)imko.de> -Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig(a)imko.de> -Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs(a)denx.de> Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher <hs(a)denx.de> +Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs(a)denx.de> Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher <hs(a)denx.de> +Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig(a)imko.de> +Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig(a)imko.de> Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx cam_enc_4xx Heiko Schocher <hs(a)denx.de> Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs(a)denx.de> Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson(a)gefanuc.com> @@ -168,8 +169,8 @@ Active arm arm926ejs kirkwood d-link - Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka(a)openwrt.org> Active arm arm926ejs kirkwood karo tk71 tk71 - - Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp(a)keymile.com> -Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp(a)keymile.com> Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp <valentin.longchamp(a)keymile.com> +Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp(a)keymile.com> Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp(a)keymile.com> Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp(a)keymile.com> Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp(a)keymile.com> @@ -275,7 +276,7 @@ Active arm armv7 exynos samsung arndale Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander(a)samsung.com> Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander(a)samsung.com> Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s(a)samsung.com> -Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s(a)samsung.com> +Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s(a)samsung.com> Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander(a)samsung.com> Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski(a)samsung.com> Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek(a)samsung.com> @@ -291,10 +292,11 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic(a)denx.de> -Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam(a)freescale.com> +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam(a)freescale.com> +Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr(a)denx.de> Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson(a)boundarydevices.com> Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson(a)boundarydevices.com> Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson(a)boundarydevices.com> @@ -308,8 +310,7 @@ Active arm armv7 mx6 freescale mx6qsabreauto Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam(a)freescale.com> -Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr(a)denx.de> -Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton(a)gmail.com> +Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton(a)gmail.com> Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman(a)gmail.com> Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas(a)gmail.com> Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph(a)8d.com> @@ -346,27 +347,26 @@ Active arm armv7 omap5 ti dra7xx Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com>:Tetsuyuki Kobayashi <koba(a)kmckk.co.jp> -Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> -Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> +Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> +Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega(a)samsung.com> Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang(a)samsung.com> Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier(a)linaro.org> Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965(a)freescale.com> -Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> -Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> -Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> -Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> -Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> -Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> +Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> +Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> +Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> +Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> +Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> +Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren(a)nvidia.com> Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel(a)avionic-design.de> Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel(a)avionic-design.de> Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel(a)avionic-design.de> -Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel(a)avionic-design.de> Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren(a)nvidia.com>:Stephen Warren <swarren(a)nvidia.com> Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren(a)nvidia.com>:Stephen Warren <swarren(a)nvidia.com> Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren(a)nvidia.com> @@ -374,6 +374,7 @@ Active arm armv7:arm720t tegra20 nvidia seaboard Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren <twarren(a)nvidia.com>:Stephen Warren <swarren(a)nvidia.com> Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren <twarren(a)nvidia.com>:Stephen Warren <swarren(a)nvidia.com> Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach <dev(a)lynxeye.de> +Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel(a)avionic-design.de> Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren(a)nvidia.com>:Stephen Warren <swarren(a)nvidia.com> Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren(a)nvidia.com> Active arm ixp - - - actux2 - Michael Schwingen <michael(a)schwingen.org> @@ -400,7 +401,6 @@ Active arm pxa - - vpac270 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich(a)gmail.com> Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut(a)gmail.com> Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson(a)gmail.com> -Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua(a)phytium.com.cn> Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel(a)googlemail.com> Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> @@ -797,8 +797,8 @@ Active powerpc mpc85xx - freescale bsc9132qds Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi(a)freescale.com> Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi(a)freescale.com> Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu(a)freescale.com> +Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu(a)freescale.com> Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu(a)freescale.com> -Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu(a)freescale.com> Active powerpc mpc85xx - freescale corenet_ds P3041DS - - Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - @@ -969,23 +969,23 @@ Active powerpc mpc85xx - freescale p2041rdb Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT - Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> +Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 - +Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun(a)freescale.com> Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - -Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - -Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> -Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> -Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal(a)freescale.com> -Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach(a)gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach(a)gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach(a)gdsys.de> -- 1.8.1.2

2 1

[U-Boot] POST in u-boot for P2020 process
by pshambhu 27 Jan '14

27 Jan '14

Hi, I am interested in performing POST (Power On Self Test ) operation in u-boot. As soon as the system starts booting , it should perform some basic functionality Testing, - Cache test - Memory Test - RAM test - I2C test - SPI Test - Ethernet Test - UART test - Watch Dog Timer Test Please let me know the changes required in U-boot Code to perform POST operation while System bootup. Thanks & Regards Pradeep S -- View this message in context: http://u-boot.10912.n7.nabble.com/POST-in-u-boot-for-P2020-process-tp172115… Sent from the U-Boot mailing list archive at Nabble.com.

2 9

[U-Boot] [RFC PATCH 1/1] Add support for pengwyn board
by micro1183 27 Jan '14

27 Jan '14

This patch adds support for the silica pengwyn board with AM335x SoC Signed-off-by: Lothar Felten <lothar.felten(a)gmail.com> --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 16 ++ board/silica/pengwyn/Makefile | 13 + board/silica/pengwyn/board.c | 245 +++++++++++++++++++ board/silica/pengwyn/board.h | 22 ++ board/silica/pengwyn/mux.c | 109 +++++++++ boards.cfg | 1 + include/configs/pengwyn.h | 340 +++++++++++++++++++++++++++ 7 files changed, 746 insertions(+) diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index c1777df..60cb098 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -58,6 +58,22 @@ #define MT41J128MJT125_PHY_FIFO_WE 0x100 #define MT41J128MJT125_IOCTRL_VALUE 0x18B +/* Micron MT41K128M16JT-187E */ +#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 +#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB +#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA +#define MT41K128MJT187E_EMIF_TIM3 0x501F830F +#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 +#define MT41K128MJT187E_EMIF_SDREF 0x0000093B +#define MT41K128MJT187E_ZQ_CFG 0x50074BE4 +#define MT41K128MJT187E_RATIO 0x40 +#define MT41K128MJT187E_INVERT_CLKOUT 0x1 +#define MT41K128MJT187E_RD_DQS 0x3B +#define MT41K128MJT187E_WR_DQS 0x85 +#define MT41K128MJT187E_PHY_WR_DATA 0xC1 +#define MT41K128MJT187E_PHY_FIFO_WE 0x100 +#define MT41K128MJT187E_IOCTRL_VALUE 0x18B + /* Micron MT41J64M16JT-125 */ #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile new file mode 100644 index 0000000..c8b4f9a --- /dev/null +++ b/board/silica/pengwyn/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c new file mode 100644 index 0000000..e6f59d4 --- /dev/null +++ b/board/silica/pengwyn/board.c @@ -0,0 +1,245 @@ +/* + * board.c + * + * Copyright (C) 2013 Lothar Felten <lothar.felten(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* MII mode defines */ +#define RMII_RGMII2_MODE_ENABLE 0x49 + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + +/* DDR3 RAM timings */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K128MJT187E_RD_DQS, + .datawdsratio0 = MT41K128MJT187E_WR_DQS, + .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE, + .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K128MJT187E_RATIO, + .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd1csratio = MT41K128MJT187E_RATIO, + .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT, + .cmd2csratio = MT41K128MJT187E_RATIO, + .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K128MJT187E_EMIF_SDCFG, + .ref_ctrl = MT41K128MJT187E_EMIF_SDREF, + .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1, + .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2, + .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3, + .zq_config = MT41K128MJT187E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE, + .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr_266 = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_303 = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_400 = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + /* the pengwyn board uses the TPS650250 PMIC without I2C */ + /* interface and will output the following fixed voltages: */ + /* DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu) */ + /* VLDO1=1V8 (IO) VLDO2=1V8(IO) */ + /* Vcore=1V1 is fixed, generated by TPS62231 */ + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* 720MHz cpu, this might change on newer board revisions */ + dpll_mpu_opp100.m = MPUPLL_M_720; + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + /* future configs can return other clock settings */ + return &dpll_ddr_303; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + config_ddr(303, &ddr3_ioregs, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#endif /* if CONFIG_SPL_BUILD */ + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; +#ifdef CONFIG_DRIVER_TI_CPSW + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + printf("<ethaddr> not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + goto try_usbether; + } + + writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +try_usbether: +#endif + +#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) + rv = usb_eth_initialize(bis); + if (rv < 0) + printf("Error %d registering USB_ETHER\n", rv); + else + n += rv; +#endif + return n; +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + return 0; +} +#endif diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h new file mode 100644 index 0000000..0a44218 --- /dev/null +++ b/board/silica/pengwyn/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * Copyright (C) 2013 Lothar Felten <lothar.felten(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); + +#endif diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c new file mode 100644 index 0000000..8b88795 --- /dev/null +++ b/board/silica/pengwyn/mux.c @@ -0,0 +1,109 @@ +/* + * mux.c + * + * Copyright (C) 2013 Lothar Felten <lothar.felten(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include "board.h" + +/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */ +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */ + +/* I2C pins C16(scl)/C17(sda) */ +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */ + {-1}, +}; + +/* MMC0 pins */ +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +/* SPI0 pins A17(sclk),B17(d0),B16(d1),A16(cs0) [C15(cs1)] */ +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | + PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | + PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ + {-1}, +}; + +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */ + {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ + {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ + {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux() +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(nand_pin_mux); +} diff --git a/boards.cfg b/boards.cfg index 07ae05b..fc09fe1 100644 --- a/boards.cfg +++ b/boards.cfg @@ -254,6 +254,7 @@ Active arm armv7 am33xx phytec pcm051 Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier(a)siemens.com> Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier(a)siemens.com> Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier(a)siemens.com> +Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten(a)gmail.com> Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini(a)ti.com> Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini(a)ti.com> Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini(a)ti.com> diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h new file mode 100644 index 0000000..65a1453 --- /dev/null +++ b/include/configs/pengwyn.h @@ -0,0 +1,340 @@ +/* + * pengwyn.h + * + * Copyright (C) 2013 Lothar Felten <lothar.felten(a)gmail.com> + * + * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_PENGWYN_H +#define __CONFIG_PENGWYN_H + +#define CONFIG_NAND +#define CONFIG_SERIAL1 +#define CONFIG_CONS_INDEX 1 + +#include <configs/ti_am335x_common.h> + +#define MACH_TYPE_PENGWYN 1234 +#define CONFIG_MACH_TYPE MACH_TYPE_PENGWYN + +/* Clock Defines */ +#define V_OSCK 24000000 +#define V_SCLK (V_OSCK) + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +#ifdef CONFIG_NAND +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandsrcaddr=0x280000\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ + "bootz ${loadaddr}\0" \ + "nandimgsize=0x500000\0" +#else +#define NANDARGS "" +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "fdt_high=0xffffffff\0" \ + "boot_fdt=try\0" \ + "rdaddr=0x81000000\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=undefined\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "dfu_alt_info_mmc=" DFU_ALT_INFO_MMC "\0" \ + "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "spiroot=/dev/mtdblock4 rw\0" \ + "spirootfstype=jffs2\0" \ + "spisrcaddr=0xe0000\0" \ + "spiimgsize=0x362000\0" \ + "spibusno=0\0" \ + "spiargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${spiroot} " \ + "rootfstype=${spirootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "dfu_alt_info_ram=" DFU_ALT_INFO_RAM "\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcloados=run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run mmcloados;" \ + "fi;" \ + "fi;\0" \ + "spiboot=echo Booting from spi ...; " \ + "run spiargs; " \ + "sf probe ${spibusno}:0; " \ + "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ + "bootz ${loadaddr}\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "findfdt="\ + "if test $board_name = A335BONE; then " \ + "setenv fdtfile am335x-bone.dtb; fi; " \ + "if test $board_name = A335BNLT; then " \ + "setenv fdtfile am335x-boneblack.dtb; fi; " \ + "if test $board_name = A33515BB; then " \ + "setenv fdtfile am335x-evm.dtb; fi; " \ + "if test $board_name = A335X_SK; then " \ + "setenv fdtfile am335x-evmsk.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: no device tree found; fi; \0" \ + NANDARGS +#endif + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run mmcboot;" \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "run mmcboot;" \ + "run nandboot;" + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* SPL */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* USB gadget RNDIS */ +#define CONFIG_SPL_MUSB_NEW_SUPPORT + +/* General network SPL, both CPSW and USB gadget RNDIS */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" + +/* NAND support */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3),1792k(u-boot)," \ + "128k(u-boot-spl-os)," \ + "128k(u-boot-env),5m(kernel),-(rootfs)" +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#else +#define CONFIG_ENV_IS_NOWHERE +#endif /* NAND */ + + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#ifdef CONFIG_MUSB_GADGET +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" + +/* USB TI's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" +#endif /* CONFIG_MUSB_GADGET */ + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* Disable CPSW SPL support so we fit within the 101KiB limit. */ +#undef CONFIG_SPL_ETH_SUPPORT +#endif + +/* USB Device Firmware Update support */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_CMD_DFU +#define DFU_ALT_INFO_MMC \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw mmc 100 100;" \ + "u-boot.img.raw mmc 300 400;" \ + "spl-os-args.raw mmc 80 80;" \ + "spl-os-image.raw mmc 900 2000;" \ + "spl-os-args fat 0 1;" \ + "spl-os-image fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1" +#ifdef CONFIG_NAND +#define CONFIG_DFU_NAND +#define DFU_ALT_INFO_NAND \ + "SPL part 0 1;" \ + "SPL.backup1 part 0 2;" \ + "SPL.backup2 part 0 3;" \ + "SPL.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot-spl-os part 0 6;" \ + "kernel part 0 8;" \ + "rootfs part 0 9" +#endif +#define CONFIG_DFU_RAM +#define DFU_ALT_INFO_RAM \ + "kernel ram 0x80200000 0xD80000;" \ + "fdt ram 0x80F80000 0x80000;" \ + "ramdisk ram 0x81000000 0x4000000" + +/* Network. */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_NATSEMI + +/* CPSW support */ +#define CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#endif /* ! __CONFIG_PENGWYN_H */ +

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[U-Boot] [PATCH 2/2][v2] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
by Aneesh Bansal 27 Jan '14

27 Jan '14

Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 28 +++++++++++++++++++++++----- arch/powerpc/cpu/mpc85xx/start.S | 3 ++- arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++++++ boards.cfg | 1 + 4 files changed, 32 insertions(+), 6 deletions(-) Changes from v1: Updated the commit message diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b31efb7..de1116b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -125,17 +125,15 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) #endif #ifdef CONFIG_SYS_FSL_CPC -static void enable_cpc(void) + +#ifdef CONFIG_RAMBOOT_PBL || defined(CONFIG_SECURE_HKAREA_CPC) +static void disable_cpc_sram(void) { int i; - u32 size = 0; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { - u32 cpccfg0 = in_be32(&cpc->cpccfg0); - size += CPC_CFG0_SZ_K(cpccfg0); -#ifdef CONFIG_RAMBOOT_PBL if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); @@ -150,8 +148,21 @@ static void enable_cpc(void) out_be32(&cpc->cpccsr0, 0); out_be32(&cpc->cpcsrcr0, 0); } + } +} #endif +static void enable_cpc(void) +{ + int i; + u32 size = 0; + + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + u32 cpccfg0 = in_be32(&cpc->cpccfg0); + size += CPC_CFG0_SZ_K(cpccfg0); + #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); #endif @@ -250,6 +261,10 @@ void cpu_init_f (void) law = find_law(CONFIG_SYS_PBI_FLASH_BASE); if (law.index != -1) disable_law(law.index); + +#if defined(CONFIG_SECURE_HKAREA_CPC) + disable_cpc_sram(); +#endif #endif #ifdef CONFIG_CPM2 @@ -550,6 +565,9 @@ skip_l2: puts("disabled\n"); #endif +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif enable_cpc(); #ifndef CONFIG_SYS_FSL_NO_SERDES diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index db84d10..5440bf5 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -117,7 +117,8 @@ _start_e500: #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ + !defined(CONFIG_E6500) /* ISBC uses L2 as stack. * Disable L2 cache here so that u-boot can enable it later * as part of it's normal flow diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 4c7f0b1..db124df 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -15,5 +15,11 @@ #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#if CONFIG_SYS_FSL_ISBC_VER > 1 +#define CONFIG_SECURE_HKAREA_CPC +#undef CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif + #endif #endif diff --git a/boards.cfg b/boards.cfg index 928e222..1d6a14c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -780,6 +780,7 @@ Active powerpc mpc85xx - freescale b4860qds Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - +Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal(a)freescale.com> Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - -- 1.8.1.4

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[U-Boot] [PATCH 1/2] SECURE BOOT: add version info for ISBC
by Aneesh Bansal 27 Jan '14

27 Jan '14

T4/B4 SoC's have a different version of ISBC. The secure boot functionality is different with the new version of ISBC compared to the earlier SoC's. So the version information is added in file config_mpc85xx.h Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- README | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/README b/README index aea82be..6c3a8d1 100644 --- a/README +++ b/README @@ -423,6 +423,9 @@ The following options need to be configured: CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. + CONFIG_SYS_FSL_ISBC_VER + This value indicates the major ISBC version on the platform. + CONFIG_SYS_FSL_SINGLE_SOURCE_CLK Single Source Clock is clocking mode present in some of FSL SoC's. In this mode, a single differential clock is used to supply diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 54ce2f0..ba5b6fe 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -151,6 +151,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ISBC_VER 1 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 /* P1011 is single core version of P1020 */ @@ -383,6 +384,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004849 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_P3041) #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -421,6 +423,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005812 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 @@ -470,6 +473,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005812 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -504,6 +508,7 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_P5040) #define CONFIG_SYS_PPC64 @@ -536,6 +541,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #define CONFIG_SYS_FSL_ERRATUM_A005812 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_BSC9131) #define CONFIG_MAX_CPUS 1 @@ -575,6 +581,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 +#define CONFIG_SYS_FSL_ISBC_VER 1 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define CONFIG_E6500 @@ -631,6 +638,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_PCI_VER_3_X +#define CONFIG_SYS_FSL_ISBC_VER 2 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) #define CONFIG_E6500 @@ -657,6 +665,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ISBC_VER 2 #ifdef CONFIG_PPC_B4860 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 -- 1.8.1.4

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