September 2013 - U-Boot

[U-Boot] [PATCH] am335x_evm: Switch to zImage as default rather than uImage
by Tom Rini 24 Sep '13

24 Sep '13

Signed-off-by: Tom Rini <trini(a)ti.com> --- include/configs/am335x_evm.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index cdf689f..f0d1663 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -61,8 +61,9 @@ "fdt_high=0xffffffff\0" \ "boot_fdt=try\0" \ "rdaddr=0x81000000\0" \ + "bootpart=0:2\0" \ "bootdir=/boot\0" \ - "bootfile=uImage\0" \ + "bootfile=zImage\0" \ "fdtfile=undefined\0" \ "console=ttyO0,115200n8\0" \ "optargs=\0" \ @@ -71,7 +72,6 @@ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ - "bootpart=0:2\0" \ "rootpath=/export/rootfs\0" \ "nfsopts=nolock\0" \ "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ @@ -105,7 +105,7 @@ "root=${ramroot} " \ "rootfstype=${ramrootfstype}\0" \ "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcloados=run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ @@ -132,7 +132,7 @@ "echo Running uenvcmd ...;" \ "run uenvcmd;" \ "fi;" \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcloados;" \ "fi;" \ "fi;\0" \ -- 1.7.9.5

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[U-Boot] How can commit code to mailing list?
by richie_wang 24 Sep '13

24 Sep '13

I have already used the git clone http://git.denx.de/u-boot.git u-boot-dev and modified some code. What i should do commit the modification? Thanks. -- View this message in context: http://u-boot.10912.n7.nabble.com/How-can-commit-code-to-mailing-list-tp163… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH v3 02/28] sf: probe: Add new spi_flash_probe support
by Jagannadha Sutradharudu Teki 24 Sep '13

24 Sep '13

Added new spi_flash_probe support, currently added N25Q* flash part attributes support. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Defined CONFIG_SPI_FLASH_LEGACY for old probing style which is available on spi_flash_probe_legacy.c, this will removed soon once all flashes are supported in new spi_flash_probe. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- Changes for v3: - Fix warning issue. Changes for v2: - Removed CONFIG_SPI_FLASH_NEW, add CONFIG_SPI_FLASH_LEGACY - Enable CONFIG_SPI_FLASH_STMICRO in spi_flash_params table - Updated few structure members drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/spi_flash_probe.c | 229 ++++++++++++------------- drivers/mtd/spi/spi_flash_probe_legacy.c | 276 +++++++++++++++++++++++++++++++ 3 files changed, 385 insertions(+), 121 deletions(-) create mode 100644 drivers/mtd/spi/spi_flash_probe_legacy.c diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 193cb5d..dde2691 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -14,6 +14,7 @@ COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o COBJS-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o endif +COBJS-$(CONFIG_SPI_FLASH_LEGACY) += spi_flash_probe_legacy.o spi_flash_ops.o spi_flash.o COBJS-$(CONFIG_SPI_FLASH) += spi_flash_probe.o spi_flash_ops.o spi_flash.o COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o diff --git a/drivers/mtd/spi/spi_flash_probe.c b/drivers/mtd/spi/spi_flash_probe.c index 32ec578..620e41b 100644 --- a/drivers/mtd/spi/spi_flash_probe.c +++ b/drivers/mtd/spi/spi_flash_probe.c @@ -18,6 +18,98 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * struct spi_flash_params - SPI/QSPI flash device params structure + * + * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) + * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) + * @ext_jedec: Device ext_jedec ID + * @sector_size: Sector size of this device + * @nr_sectors: No.of sectors on this device + */ +struct spi_flash_params { + const char *name; + u32 jedec; + u16 ext_jedec; + u32 sector_size; + u32 nr_sectors; +}; + +static const struct spi_flash_params spi_flash_params_table[] = { +#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ + {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64}, + {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64}, + {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128}, + {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128}, + {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256}, + {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256}, + {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512}, + {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512}, + {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024}, + {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024}, + {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048}, + {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048}, +#endif + /* + * TODO: + * ATMEL + * EON + * GIGADEVICE + * MACRONIX + * RAMTRON + * SPANSION + * SST + * STMICRO (M25*) + * WINBOND + */ +}; + +struct spi_flash *spi_flash_validate_ids(struct spi_slave *spi, u8 *idcode) +{ + const struct spi_flash_params *params; + struct spi_flash *flash; + int i; + u16 jedec = idcode[1] << 8 | idcode[2]; + + /* Get the flash id (jedec = manuf_id + dev_id) */ + for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) { + params = &spi_flash_params_table[i]; + if ((params->jedec >> 16) == idcode[0]) { + if ((params->jedec & 0xFFFF) == jedec) + break; + } + } + + if (i == ARRAY_SIZE(spi_flash_params_table)) { + printf("SF: Unsupported flash ID: manuf %02x, jedec %04x\n", + idcode[0], jedec); + return NULL; + } + + flash = malloc(sizeof(*flash)); + if (!flash) { + debug("SF: Failed to allocate spi_flash\n"); + return NULL; + } + memset(flash, '\0', sizeof(*flash)); + + flash->spi = spi; + flash->name = params->name; + flash->poll_cmd = CMD_READ_STATUS; + + /* Assign spi_flash ops */ + flash->write = spi_flash_cmd_write_multi; + flash->erase = spi_flash_cmd_erase; + flash->read = spi_flash_cmd_read_fast; + + /* Compute the flash size */ + flash->page_size = 256; + flash->sector_size = params->sector_size; + flash->size = flash->sector_size * params->nr_sectors; + + return flash; +} + #ifdef CONFIG_SPI_FLASH_BAR int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0) { @@ -84,89 +176,22 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) } #endif /* CONFIG_OF_CONTROL */ -/* - * The following table holds all device probe functions - * - * shift: number of continuation bytes before the ID - * idcode: the expected IDCODE or 0xff for non JEDEC devices - * probe: the function to call - * - * Non JEDEC devices should be ordered in the table such that - * the probe functions with best detection algorithms come first. - * - * Several matching entries are permitted, they will be tried - * in sequence until a probe function returns non NULL. - * - * IDCODE_CONT_LEN may be redefined if a device needs to declare a - * larger "shift" value. IDCODE_PART_LEN generally shouldn't be - * changed. This is the max number of bytes probe functions may - * examine when looking up part-specific identification info. - * - * Probe functions will be given the idcode buffer starting at their - * manu id byte (the "idcode" in the table below). In other words, - * all of the continuation bytes will be skipped (the "shift" below). - */ -#define IDCODE_CONT_LEN 0 -#define IDCODE_PART_LEN 5 -static const struct { - const u8 shift; - const u8 idcode; - struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); -} flashes[] = { - /* Keep it sorted by define name */ -#ifdef CONFIG_SPI_FLASH_ATMEL - { 0, 0x1f, spi_flash_probe_atmel, }, -#endif -#ifdef CONFIG_SPI_FLASH_EON - { 0, 0x1c, spi_flash_probe_eon, }, -#endif -#ifdef CONFIG_SPI_FLASH_GIGADEVICE - { 0, 0xc8, spi_flash_probe_gigadevice, }, -#endif -#ifdef CONFIG_SPI_FLASH_MACRONIX - { 0, 0xc2, spi_flash_probe_macronix, }, -#endif -#ifdef CONFIG_SPI_FLASH_SPANSION - { 0, 0x01, spi_flash_probe_spansion, }, -#endif -#ifdef CONFIG_SPI_FLASH_SST - { 0, 0xbf, spi_flash_probe_sst, }, -#endif -#ifdef CONFIG_SPI_FLASH_STMICRO - { 0, 0x20, spi_flash_probe_stmicro, }, -#endif -#ifdef CONFIG_SPI_FLASH_WINBOND - { 0, 0xef, spi_flash_probe_winbond, }, -#endif -#ifdef CONFIG_SPI_FRAM_RAMTRON - { 6, 0xc2, spi_fram_probe_ramtron, }, -# undef IDCODE_CONT_LEN -# define IDCODE_CONT_LEN 6 -#endif - /* Keep it sorted by best detection */ -#ifdef CONFIG_SPI_FLASH_STMICRO - { 0, 0xff, spi_flash_probe_stmicro, }, -#endif -#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC - { 0, 0xff, spi_fram_probe_ramtron, }, -#endif -}; -#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) - struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode) { struct spi_slave *spi; struct spi_flash *flash = NULL; - int ret, i, shift; - u8 idcode[IDCODE_LEN], *idp; + u8 idcode[5], *idp; + int ret; + /* Setup spi_slave */ spi = spi_setup_slave(bus, cs, max_hz, spi_mode); if (!spi) { printf("SF: Failed to set up slave\n"); return NULL; } + /* Claim spi bus */ ret = spi_claim_bus(spi); if (ret) { debug("SF: Failed to claim SPI bus: %d\n", ret); @@ -175,45 +200,33 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, /* Read the ID codes */ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); - if (ret) + if (ret) { + printf("SF: Failed to get idcodes\n"); goto err_read_id; + } #ifdef DEBUG printf("SF: Got idcodes\n"); print_buffer(0, idcode, 1, sizeof(idcode), 0); #endif - /* count the number of continuation bytes */ - for (shift = 0, idp = idcode; - shift < IDCODE_CONT_LEN && *idp == 0x7f; - ++shift, ++idp) - continue; - - /* search the table for matches in shift and id */ - for (i = 0; i < ARRAY_SIZE(flashes); ++i) - if (flashes[i].shift == shift && flashes[i].idcode == *idp) { - /* we have a match, call probe */ - flash = flashes[i].probe(spi, idp); - if (flash) - break; - } - - if (!flash) { - printf("SF: Unsupported manufacturer %02x\n", *idp); - goto err_manufacturer_probe; - } + /* Validate ID's from flash dev table */ + idp = idcode; + flash = spi_flash_validate_ids(spi, idp); + if (!flash) + goto err_read_id; #ifdef CONFIG_SPI_FLASH_BAR - /* Configure the BAR - disover bank cmds and read current bank */ + /* Configure the BAR - discover bank cmds and read current bank */ ret = spi_flash_bank_config(flash, *idp); if (ret < 0) - goto err_manufacturer_probe; + goto err_read_id; #endif #ifdef CONFIG_OF_CONTROL if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { debug("SF: FDT decode error\n"); - goto err_manufacturer_probe; + goto err_read_id; } #endif #ifndef CONFIG_SPL_BUILD @@ -231,11 +244,11 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, } #endif + /* Release spi bus */ spi_release_bus(spi); return flash; -err_manufacturer_probe: err_read_id: spi_release_bus(spi); err_claim_bus: @@ -243,32 +256,6 @@ err_claim_bus: return NULL; } -void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, - const char *name) -{ - struct spi_flash *flash; - void *ptr; - - ptr = malloc(size); - if (!ptr) { - debug("SF: Failed to allocate memory\n"); - return NULL; - } - memset(ptr, '\0', size); - flash = (struct spi_flash *)(ptr + offset); - - /* Set up some basic fields - caller will sort out sizes */ - flash->spi = spi; - flash->name = name; - flash->poll_cmd = CMD_READ_STATUS; - - flash->read = spi_flash_cmd_read_fast; - flash->write = spi_flash_cmd_write_multi; - flash->erase = spi_flash_cmd_erase; - - return flash; -} - void spi_flash_free(struct spi_flash *flash) { spi_free_slave(flash->spi); diff --git a/drivers/mtd/spi/spi_flash_probe_legacy.c b/drivers/mtd/spi/spi_flash_probe_legacy.c new file mode 100644 index 0000000..32ec578 --- /dev/null +++ b/drivers/mtd/spi/spi_flash_probe_legacy.c @@ -0,0 +1,276 @@ +/* + * SPI flash probing + * + * Copyright (C) 2008 Atmel Corporation + * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik + * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <fdtdec.h> +#include <malloc.h> +#include <spi.h> +#include <spi_flash.h> + +#include "spi_flash_internal.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPI_FLASH_BAR +int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0) +{ + u8 cmd; + u8 curr_bank = 0; + + /* discover bank cmds */ + switch (idcode0) { + case SPI_FLASH_SPANSION_IDCODE0: + flash->bank_read_cmd = CMD_BANKADDR_BRRD; + flash->bank_write_cmd = CMD_BANKADDR_BRWR; + break; + case SPI_FLASH_STMICRO_IDCODE0: + case SPI_FLASH_WINBOND_IDCODE0: + flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; + flash->bank_write_cmd = CMD_EXTNADDR_WREAR; + break; + default: + printf("SF: Unsupported bank commands %02x\n", idcode0); + return -1; + } + + /* read the bank reg - on which bank the flash is in currently */ + cmd = flash->bank_read_cmd; + if (flash->size > SPI_FLASH_16MB_BOUN) { + if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) { + debug("SF: fail to read bank addr register\n"); + return -1; + } + flash->bank_curr = curr_bank; + } else { + flash->bank_curr = curr_bank; + } + + return 0; +} +#endif + +#ifdef CONFIG_OF_CONTROL +int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) +{ + fdt_addr_t addr; + fdt_size_t size; + int node; + + /* If there is no node, do nothing */ + node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); + if (node < 0) + return 0; + + addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); + if (addr == FDT_ADDR_T_NONE) { + debug("%s: Cannot decode address\n", __func__); + return 0; + } + + if (flash->size != size) { + debug("%s: Memory map must cover entire device\n", __func__); + return -1; + } + flash->memory_map = (void *)addr; + + return 0; +} +#endif /* CONFIG_OF_CONTROL */ + +/* + * The following table holds all device probe functions + * + * shift: number of continuation bytes before the ID + * idcode: the expected IDCODE or 0xff for non JEDEC devices + * probe: the function to call + * + * Non JEDEC devices should be ordered in the table such that + * the probe functions with best detection algorithms come first. + * + * Several matching entries are permitted, they will be tried + * in sequence until a probe function returns non NULL. + * + * IDCODE_CONT_LEN may be redefined if a device needs to declare a + * larger "shift" value. IDCODE_PART_LEN generally shouldn't be + * changed. This is the max number of bytes probe functions may + * examine when looking up part-specific identification info. + * + * Probe functions will be given the idcode buffer starting at their + * manu id byte (the "idcode" in the table below). In other words, + * all of the continuation bytes will be skipped (the "shift" below). + */ +#define IDCODE_CONT_LEN 0 +#define IDCODE_PART_LEN 5 +static const struct { + const u8 shift; + const u8 idcode; + struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); +} flashes[] = { + /* Keep it sorted by define name */ +#ifdef CONFIG_SPI_FLASH_ATMEL + { 0, 0x1f, spi_flash_probe_atmel, }, +#endif +#ifdef CONFIG_SPI_FLASH_EON + { 0, 0x1c, spi_flash_probe_eon, }, +#endif +#ifdef CONFIG_SPI_FLASH_GIGADEVICE + { 0, 0xc8, spi_flash_probe_gigadevice, }, +#endif +#ifdef CONFIG_SPI_FLASH_MACRONIX + { 0, 0xc2, spi_flash_probe_macronix, }, +#endif +#ifdef CONFIG_SPI_FLASH_SPANSION + { 0, 0x01, spi_flash_probe_spansion, }, +#endif +#ifdef CONFIG_SPI_FLASH_SST + { 0, 0xbf, spi_flash_probe_sst, }, +#endif +#ifdef CONFIG_SPI_FLASH_STMICRO + { 0, 0x20, spi_flash_probe_stmicro, }, +#endif +#ifdef CONFIG_SPI_FLASH_WINBOND + { 0, 0xef, spi_flash_probe_winbond, }, +#endif +#ifdef CONFIG_SPI_FRAM_RAMTRON + { 6, 0xc2, spi_fram_probe_ramtron, }, +# undef IDCODE_CONT_LEN +# define IDCODE_CONT_LEN 6 +#endif + /* Keep it sorted by best detection */ +#ifdef CONFIG_SPI_FLASH_STMICRO + { 0, 0xff, spi_flash_probe_stmicro, }, +#endif +#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC + { 0, 0xff, spi_fram_probe_ramtron, }, +#endif +}; +#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + struct spi_flash *flash = NULL; + int ret, i, shift; + u8 idcode[IDCODE_LEN], *idp; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + printf("SF: Failed to set up slave\n"); + return NULL; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("SF: Failed to claim SPI bus: %d\n", ret); + goto err_claim_bus; + } + + /* Read the ID codes */ + ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); + if (ret) + goto err_read_id; + +#ifdef DEBUG + printf("SF: Got idcodes\n"); + print_buffer(0, idcode, 1, sizeof(idcode), 0); +#endif + + /* count the number of continuation bytes */ + for (shift = 0, idp = idcode; + shift < IDCODE_CONT_LEN && *idp == 0x7f; + ++shift, ++idp) + continue; + + /* search the table for matches in shift and id */ + for (i = 0; i < ARRAY_SIZE(flashes); ++i) + if (flashes[i].shift == shift && flashes[i].idcode == *idp) { + /* we have a match, call probe */ + flash = flashes[i].probe(spi, idp); + if (flash) + break; + } + + if (!flash) { + printf("SF: Unsupported manufacturer %02x\n", *idp); + goto err_manufacturer_probe; + } + +#ifdef CONFIG_SPI_FLASH_BAR + /* Configure the BAR - disover bank cmds and read current bank */ + ret = spi_flash_bank_config(flash, *idp); + if (ret < 0) + goto err_manufacturer_probe; +#endif + +#ifdef CONFIG_OF_CONTROL + if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { + debug("SF: FDT decode error\n"); + goto err_manufacturer_probe; + } +#endif +#ifndef CONFIG_SPL_BUILD + printf("SF: Detected %s with page size ", flash->name); + print_size(flash->sector_size, ", total "); + print_size(flash->size, ""); + if (flash->memory_map) + printf(", mapped at %p", flash->memory_map); + puts("\n"); +#endif +#ifndef CONFIG_SPI_FLASH_BAR + if (flash->size > SPI_FLASH_16MB_BOUN) { + puts("SF: Warning - Only lower 16MiB accessible,"); + puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); + } +#endif + + spi_release_bus(spi); + + return flash; + +err_manufacturer_probe: +err_read_id: + spi_release_bus(spi); +err_claim_bus: + spi_free_slave(spi); + return NULL; +} + +void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, + const char *name) +{ + struct spi_flash *flash; + void *ptr; + + ptr = malloc(size); + if (!ptr) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + memset(ptr, '\0', size); + flash = (struct spi_flash *)(ptr + offset); + + /* Set up some basic fields - caller will sort out sizes */ + flash->spi = spi; + flash->name = name; + flash->poll_cmd = CMD_READ_STATUS; + + flash->read = spi_flash_cmd_read_fast; + flash->write = spi_flash_cmd_write_multi; + flash->erase = spi_flash_cmd_erase; + + return flash; +} + +void spi_flash_free(struct spi_flash *flash) +{ + spi_free_slave(flash->spi); + free(flash); +} -- 1.8.3

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[U-Boot] [PATCH] arm:samsung:serial: Extract common Samsung UART code
by Lukasz Majewski 24 Sep '13

24 Sep '13

This commit removes duplicated code for UART IP block embedded at Samsung SoCs. New ./include/asm/samsung-common directory has been created to store common code for existing and future Samsung targets. Additionally building of UART code now depends on more verbose CONFIG_S5P_SERIAL define. For this reason all relevant configs have been adjusted. Signed-off-by: Lukasz Majewski <l.majewski(a)majess.pl> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- arch/arm/include/asm/arch-exynos/uart.h | 58 ------------------ arch/arm/include/asm/arch-s5pc1xx/uart.h | 58 ------------------ arch/arm/include/asm/samsung-common/uart.h | 88 ++++++++++++++++++++++++++++ drivers/serial/Makefile | 2 +- drivers/serial/serial_s5p.c | 13 +--- include/configs/exynos5250-dt.h | 1 + include/configs/origen.h | 1 + include/configs/s5p_goni.h | 1 + include/configs/s5pc210_universal.h | 1 + include/configs/smdkc100.h | 1 + include/configs/smdkv310.h | 1 + include/configs/trats.h | 1 + 12 files changed, 98 insertions(+), 128 deletions(-) delete mode 100644 arch/arm/include/asm/arch-exynos/uart.h delete mode 100644 arch/arm/include/asm/arch-s5pc1xx/uart.h create mode 100644 arch/arm/include/asm/samsung-common/uart.h diff --git a/arch/arm/include/asm/arch-exynos/uart.h b/arch/arm/include/asm/arch-exynos/uart.h deleted file mode 100644 index 6cc68df..0000000 --- a/arch/arm/include/asm/arch-exynos/uart.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang(a)samsung.com> - * Heungjun Kim <riverful.kim(a)samsung.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_UART_H_ -#define __ASM_ARCH_UART_H_ - -#ifndef __ASSEMBLY__ -/* baudrate rest value */ -union br_rest { - unsigned short slot; /* udivslot */ - unsigned char value; /* ufracval */ -}; - -struct s5p_uart { - unsigned int ulcon; - unsigned int ucon; - unsigned int ufcon; - unsigned int umcon; - unsigned int utrstat; - unsigned int uerstat; - unsigned int ufstat; - unsigned int umstat; - unsigned char utxh; - unsigned char res1[3]; - unsigned char urxh; - unsigned char res2[3]; - unsigned int ubrdiv; - union br_rest rest; - unsigned char res3[0xffd0]; -}; - -static inline int s5p_uart_divslot(void) -{ - return 0; -} - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/include/asm/arch-s5pc1xx/uart.h deleted file mode 100644 index 1c56739..0000000 --- a/arch/arm/include/asm/arch-s5pc1xx/uart.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang(a)samsung.com> - * Heungjun Kim <riverful.kim(a)samsung.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_UART_H_ -#define __ASM_ARCH_UART_H_ - -#ifndef __ASSEMBLY__ -/* baudrate rest value */ -union br_rest { - unsigned short slot; /* udivslot */ - unsigned char value; /* ufracval */ -}; - -struct s5p_uart { - unsigned int ulcon; - unsigned int ucon; - unsigned int ufcon; - unsigned int umcon; - unsigned int utrstat; - unsigned int uerstat; - unsigned int ufstat; - unsigned int umstat; - unsigned char utxh; - unsigned char res1[3]; - unsigned char urxh; - unsigned char res2[3]; - unsigned int ubrdiv; - union br_rest rest; - unsigned char res3[0x3d0]; -}; - -static inline int s5p_uart_divslot(void) -{ - return 1; -} - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/arm/include/asm/samsung-common/uart.h b/arch/arm/include/asm/samsung-common/uart.h new file mode 100644 index 0000000..3b6572d --- /dev/null +++ b/arch/arm/include/asm/samsung-common/uart.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_UART_H_ +#define __ASM_ARCH_UART_H_ + +#ifndef __ASSEMBLY__ +/* baudrate rest value */ +union br_rest { + unsigned short slot; /* udivslot */ + unsigned char value; /* ufracval */ +}; + +struct s5p_uart { + unsigned int ulcon; + unsigned int ucon; + unsigned int ufcon; + unsigned int umcon; + unsigned int utrstat; + unsigned int uerstat; + unsigned int ufstat; + unsigned int umstat; + unsigned char utxh; + unsigned char res1[3]; + unsigned char urxh; + unsigned char res2[3]; + unsigned int ubrdiv; + union br_rest rest; +#if defined(CONFIG_S5PC100) || \ + defined(CONFIG_S5PC110) || \ + defined(CONFIG_S3C64XX) + unsigned char res3[0x3d0]; +#else /* Exynos 4 and 5 */ + unsigned char res3[0xffd0]; +#endif +}; + + +static inline int s5p_uart_divslot(void) +{ +#if defined(CONFIG_S5PC100) || \ + defined(CONFIG_S5PC110) || \ + defined(CONFIG_S3C64XX) + return 1; +#else /* Exynos 4 and 5 */ + return 0; +#endif +} + +#if defined(CONFIG_S3C64XX) +#define RX_FIFO_COUNT_MASK 0x3f +#define RX_FIFO_FULL_MASK (1 << 6) +#define TX_FIFO_FULL_MASK (1 << 14) +#else /* S5PC110 and Exynos 4 and 5 */ +#define RX_FIFO_COUNT_MASK 0xff +#define RX_FIFO_FULL_MASK (1 << 8) +#define TX_FIFO_FULL_MASK (1 << 24) +#endif + +/* Information about a serial port */ +struct fdt_serial { + u32 base_addr; /* address of registers in physical memory */ + u8 port_id; /* uart port number */ + u8 enabled; /* 1 if enabled, 0 if disabled */ +}; + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 0f954a5..4c4ba75 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -35,7 +35,7 @@ COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o -COBJS-$(CONFIG_S5P) += serial_s5p.o +COBJS-$(CONFIG_S5P_SERIAL) += serial_s5p.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 6836c7a..fb0677b 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -25,22 +25,13 @@ #include <fdtdec.h> #include <linux/compiler.h> #include <asm/io.h> -#include <asm/arch/uart.h> +#include <asm/samsung-common/uart.h> #include <asm/arch/clk.h> #include <serial.h> DECLARE_GLOBAL_DATA_PTR; -#define RX_FIFO_COUNT_MASK 0xff -#define RX_FIFO_FULL_MASK (1 << 8) -#define TX_FIFO_FULL_MASK (1 << 24) - -/* Information about a serial port */ -struct fdt_serial { - u32 base_addr; /* address of registers in physical memory */ - u8 port_id; /* uart port number */ - u8 enabled; /* 1 if enabled, 0 if disabled */ -} config __attribute__ ((section(".data"))); +struct fdt_serial config __attribute__ ((section(".data"))); static inline struct s5p_uart *s5p_get_base_uart(int dev_index) { diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 582c584..303a8de 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -86,6 +86,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) /* select serial console configuration */ +#define CONFIG_S5P_SERIAL #define CONFIG_BAUDRATE 115200 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 #define CONFIG_SILENT_CONSOLE diff --git a/include/configs/origen.h b/include/configs/origen.h index 5013aee..7197243 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) /* select serial console configuration */ +#define CONFIG_S5P_SERIAL #define CONFIG_SERIAL2 1 /* use SERIAL 2 */ #define CONFIG_BAUDRATE 115200 #define EXYNOS4_DEFAULT_UART_OFFSET 0x020000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 56e8347..440c4a3 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -58,6 +58,7 @@ /* * select serial console configuration */ +#define CONFIG_S5P_SERIAL #define CONFIG_SERIAL2 1 /* use SERIAL2 */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index eb13bb3..398db2a 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) /* select serial console configuration */ +#define CONFIG_S5P_SERIAL #define CONFIG_SERIAL2 1 /* use SERIAL 2 */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index fb640db..6964a77 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -63,6 +63,7 @@ /* * select serial console configuration */ +#define CONFIG_S5P_SERIAL #define CONFIG_SERIAL0 1 /* use SERIAL 0 on SMDKC100 */ /* PWM */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 0f04597..3c68543 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) /* select serial console configuration */ +#define CONFIG_S5P_SERIAL #define CONFIG_SERIAL1 1 /* use SERIAL 1 */ #define CONFIG_BAUDRATE 115200 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 diff --git a/include/configs/trats.h b/include/configs/trats.h index 356d87b..e9c1fa4 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -69,6 +69,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (16 << 20)) /* select serial console configuration */ +#define CONFIG_S5P_SERIAL #define CONFIG_SERIAL2 /* use SERIAL 2 */ #define CONFIG_BAUDRATE 115200 -- 1.7.10.4

4 13

[U-Boot] s3c2416 usb ohci issue
by Zoltan Gyarmati 24 Sep '13

24 Sep '13

Hi, i'm trying to bring up the current mainline u-boot version on a SOM2416II board, which based on the s3c2416 SOC. Already the base booting had some challenges and required some patching (mostly based on José Miguel Gonçalves' patchset from September 2012), so now the booting, the serial console and the ethernet works well, but unfortunately i got blocked with the OHCI support. I'm using the "new" general ohci support (ohci-hcd.c), and as the CPU init function i use the appropriate functions from ohci-s3c24xx.c. After the u-boot succesfully started, and calling the 'usb start' command, it recognizes succesfully only the root hub, and when trying to init the USB storage device, it fails with a DEVICENOTRESPONDING error. Please find the full boot log here: http://pastebin.com/APrDJ0GR , the config (among with the full tree) here: https://github.com/Cimitech/uboot/blob/v2013.07-2416/include/configs/mini24… Is there anybody else who was recently trying to make this work? Any hints which way i should start with the debugging? What i found similar issues were mostly related to slow, or not proper USB memory sticks, so i tried with several devices, and also played around with the related timeouts, without any success. Thanks for any hints in advance, best regards -- br, Zoltan Gyarmati mail: mr.zoltan.gyarmati(a)gmail.com freenode nick: zgyarmati

2 1

[U-Boot] Does u-boot support S3C24xx nand ecc?
by Woody Wu 24 Sep '13

24 Sep '13

Hi, Does anyone know if u-boot (version 2009.11) already contains supports to the hardware ECC for NAND in S3C24xx (Specifically S3C2416) SoC? Thanks in advance. -- I can't go back to yesterday - because I was a different person then

3 2

[U-Boot] [PATCH 2/3] mtd/ifc: Add support of 8K page size NAND flash
by Prabhakar Kushwaha 24 Sep '13

24 Sep '13

Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 24 +++++++++++ arch/powerpc/include/asm/fsl_ifc.h | 2 + drivers/mtd/nand/fsl_ifc_nand.c | 78 ++++++++++++++++++++++++++++++++++++ drivers/mtd/nand/fsl_ifc_spl.c | 4 ++ 4 files changed, 108 insertions(+) diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index 2d0fb43..64a5225 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -34,6 +34,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR0_EXT set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); #endif +#ifdef CONFIG_SYS_CSOR0_EXT + set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); +#endif set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); @@ -43,6 +46,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR1_EXT set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); #endif +#ifdef CONFIG_SYS_CSOR1_EXT + set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); +#endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); @@ -57,6 +63,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR2_EXT set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); #endif +#ifdef CONFIG_SYS_CSOR2_EXT + set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); +#endif #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); @@ -71,6 +80,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR3_EXT set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); #endif +#ifdef CONFIG_SYS_CSOR3_EXT + set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); +#endif #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); @@ -85,6 +97,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR4_EXT set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); #endif +#ifdef CONFIG_SYS_CSOR4_EXT + set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); +#endif #if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); @@ -99,6 +114,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR5_EXT set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); #endif +#ifdef CONFIG_SYS_CSOR5_EXT + set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT); +#endif #if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); @@ -113,6 +131,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR6_EXT set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); #endif +#ifdef CONFIG_SYS_CSOR6_EXT + set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); +#endif #if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); @@ -127,6 +148,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR7_EXT set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); #endif +#ifdef CONFIG_SYS_CSOR7_EXT + set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#endif #if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index a945e4b..182b1a6 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -77,6 +77,7 @@ #define CSOR_NAND_PGS_512 0x00000000 #define CSOR_NAND_PGS_2K 0x00080000 #define CSOR_NAND_PGS_4K 0x00100000 +#define CSOR_NAND_PGS_8K 0x00180000 /* Spare region Size */ #define CSOR_NAND_SPRZ_MASK 0x0000E000 #define CSOR_NAND_SPRZ_SHIFT 13 @@ -86,6 +87,7 @@ #define CSOR_NAND_SPRZ_210 0x00006000 #define CSOR_NAND_SPRZ_218 0x00008000 #define CSOR_NAND_SPRZ_224 0x0000A000 +#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 98a09c0..cfed549 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -125,6 +125,69 @@ static struct nand_ecclayout oob_4096_ecc8 = { .oobfree = { {2, 6}, {136, 82} }, }; +/* 8192-byte page size with 4-bit ECC */ +static struct nand_ecclayout oob_8192_ecc4 = { + .eccbytes = 128, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + }, + .oobfree = { {2, 6}, {136, 208} }, +}; + +/* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */ +static struct nand_ecclayout oob_8192_ecc8 = { + .eccbytes = 256, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + 136, 137, 138, 139, 140, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, + 152, 153, 154, 155, 156, 157, 158, 159, + 160, 161, 162, 163, 164, 165, 166, 167, + 168, 169, 170, 171, 172, 173, 174, 175, + 176, 177, 178, 179, 180, 181, 182, 183, + 184, 185, 186, 187, 188, 189, 190, 191, + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212, 213, 214, 215, + 216, 217, 218, 219, 220, 221, 222, 223, + 224, 225, 226, 227, 228, 229, 230, 231, + 232, 233, 234, 235, 236, 237, 238, 239, + 240, 241, 242, 243, 244, 245, 246, 247, + 248, 249, 250, 251, 252, 253, 254, 255, + 256, 257, 258, 259, 260, 261, 262, 263, + }, + .oobfree = { {2, 6}, {264, 80} }, +}; /* * Generic flash bbt descriptors @@ -902,6 +965,21 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) priv->bufnum_mask = 1; break; + case CSOR_NAND_PGS_8K: + if ((csor & CSOR_NAND_ECC_MODE_MASK) == + CSOR_NAND_ECC_MODE_4) { + layout = &oob_8192_ecc4; + nand->ecc.strength = 4; + } else { + layout = &oob_8192_ecc8; + nand->ecc.strength = 8; + nand->ecc.bytes = 16; + } + + priv->bufnum_mask = 0; + break; + + default: printf("ifc nand: bad csor %#x: bad page size\n", csor); return -ENODEV; diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index d462265..b6d3335 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -112,6 +112,10 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; + if (csor & CSOR_NAND_PGS_8K) { + page_size = 8192; + bufnum_mask = 0x0; + } if (csor & CSOR_NAND_PGS_4K) { page_size = 4096; bufnum_mask = 0x1; -- 1.7.9.5

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[U-Boot] [PATCH] boards/c29xpcie: Update TLB and LAW size for IFC NAND
by Prabhakar Kushwaha 24 Sep '13

24 Sep '13

IFC NAND AMASK register is programmed for 64K size. so Update TLB & LAW size accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master board/freescale/c29xpcie/law.c | 2 +- board/freescale/c29xpcie/tlb.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c index cd8fc21..d48ec23 100644 --- a/board/freescale/c29xpcie/law.c +++ b/board/freescale/c29xpcie/law.c @@ -11,7 +11,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K, LAW_TRGT_IF_PLATFORM_SRAM), }; diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c index ddd1ef8..0fa1dc5 100644 --- a/board/freescale/c29xpcie/tlb.c +++ b/board/freescale/c29xpcie/tlb.c @@ -50,7 +50,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_16K, 1), + 0, 5, BOOKE_PAGESZ_64K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, -- 1.7.9.5

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Re: [U-Boot] [PATCH 2/2] Armada100: Add SD card support for Marvell gplugD
by Pantelis Antoniou 24 Sep '13

24 Sep '13

Hi Ajay, On Sep 24, 2013, at 11:02 AM, Ajay Bhargav wrote: > This patch adds support for SD card interface (MMC1 and MMC2) for > Marvell gplugD. > > Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> > --- > arch/arm/include/asm/arch-armada100/cpu.h | 1 + > arch/arm/include/asm/arch-armada100/mfp.h | 17 ++++++++++++++ > board/Marvell/gplugd/gplugd.c | 39 +++++++++++++++++++++++++++++++ > include/configs/gplugd.h | 9 +++++++ > 4 files changed, 66 insertions(+) > > diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h > index c1f190d..8c5091e 100644 > --- a/arch/arm/include/asm/arch-armada100/cpu.h > +++ b/arch/arm/include/asm/arch-armada100/cpu.h > @@ -158,5 +158,6 @@ struct armd1cpu_registers { > */ > u32 armd1_sdram_base(int); > u32 armd1_sdram_size(int); > +int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); > > #endif /* _ARMADA100CPU_H */ > diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h > index b918239..202332b 100644 > --- a/arch/arm/include/asm/arch-armada100/mfp.h > +++ b/arch/arm/include/asm/arch-armada100/mfp.h > @@ -73,6 +73,23 @@ > #define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) > #define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) > > +/* MMC 1 */ > +#define MFP040_MMC1_D1 (MFP_REG(0x00C) | MFP_AF1 | MFP_DRIVE_MEDIUM) > +#define MFP041_MMC1_D0 (MFP_REG(0x010) | MFP_AF1 | MFP_DRIVE_MEDIUM) > +#define MFP043_MMC1_CLK (MFP_REG(0x018) | MFP_AF1 | MFP_DRIVE_MEDIUM) > +#define MFP049_MMC1_CMD (MFP_REG(0x030) | MFP_AF1 | MFP_DRIVE_MEDIUM) > +#define MFP051_MMC1_D3 (MFP_REG(0x038) | MFP_AF1 | MFP_DRIVE_MEDIUM) > +#define MFP052_MMC1_D2 (MFP_REG(0x03C) | MFP_AF1 | MFP_DRIVE_MEDIUM) > +#define MFP053_MMC1_CD (MFP_REG(0x040) | MFP_AF1 | MFP_DRIVE_MEDIUM) > + > +/* MMC2 */ > +#define MFP028_MMC2_CMD (MFP_REG(0x0BC) | MFP_AF6 | MFP_DRIVE_MEDIUM) > +#define MFP029_MMC2_CLK (MFP_REG(0x0C0) | MFP_AF6 | MFP_DRIVE_MEDIUM) > +#define MFP030_MMC2_D0 (MFP_REG(0x0C4) | MFP_AF6 | MFP_DRIVE_MEDIUM) > +#define MFP031_MMC2_D1 (MFP_REG(0x0C8) | MFP_AF6 | MFP_DRIVE_MEDIUM) > +#define MFP032_MMC2_D2 (MFP_REG(0x0CC) | MFP_AF6 | MFP_DRIVE_MEDIUM) > +#define MFP033_MMC2_D3 (MFP_REG(0x0D0) | MFP_AF6 | MFP_DRIVE_MEDIUM) > + > /* More macros can be defined here... */ > > #define MFP_PIN_MAX 117 > diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c > index 0e8ebcc..954d97e 100644 > --- a/board/Marvell/gplugd/gplugd.c > +++ b/board/Marvell/gplugd/gplugd.c > @@ -19,6 +19,7 @@ > #include <asm/arch/armada100.h> > #include <asm/gpio.h> > #include <miiphy.h> > +#include <sdhci.h> > > #ifdef CONFIG_ARMADA100_FEC > #include <net.h> > @@ -63,6 +64,23 @@ int board_early_init_f(void) > MFP110_SSP2_CS, > MFP111_SSP2_CLK, > > + /* MMC1 */ > + MFP040_MMC1_D1, > + MFP041_MMC1_D0, > + MFP043_MMC1_CLK, > + MFP049_MMC1_CMD, > + MFP051_MMC1_D3, > + MFP052_MMC1_D2, > + MFP053_MMC1_CD, > + > + /* MMC2 */ > + MFP028_MMC2_CMD, > + MFP029_MMC2_CLK, > + MFP030_MMC2_D0, > + MFP031_MMC2_D1, > + MFP032_MMC2_D2, > + MFP033_MMC2_D3, > + > MFP_EOC /*End of configuration*/ > }; > /* configure MFP's */ > @@ -90,6 +108,27 @@ int board_init(void) > return 0; > } > > +int board_mmc_init(bd_t *bd) > +{ > + struct armd1apmu_registers *apmu_regs = > + (struct armd1apmu_registers *)ARMD1_APMU_BASE; > + > + setbits_le32(&apmu_regs->sd1crc, SD1_SD2_AXI_RESET | SD1_RESET); > + udelay(10); > + setbits_le32(&apmu_regs->sd1crc, SD1_CLK_EN | SD1_SD2_AXICLK_EN); > + > + setbits_le32(&apmu_regs->sd2crc, SD2_RESET); > + udelay(10); > + setbits_le32(&apmu_regs->sd2crc, SD2_CLK_EN); > + > + mv_sdh_init(ARMD1_SD1_BASE, 0, 0, > + SDHCI_QUIRK_REG32_RW | SDHCI_QUIRK_BROKEN_R1B); > + > + mv_sdh_init(ARMD1_SD2_BASE, 0, 0, > + SDHCI_QUIRK_REG32_RW | SDHCI_QUIRK_BROKEN_R1B); > + return 0; > +} > + > #ifdef CONFIG_ARMADA100_FEC > int board_eth_init(bd_t *bis) > { > diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h > index 404c56a..a4e6c49 100644 > --- a/include/configs/gplugd.h > +++ b/include/configs/gplugd.h > @@ -95,6 +95,15 @@ > #define CONFIG_CMD_SF > #define CONFIG_SPI_FLASH_ATMEL > > +#define CONFIG_MV_SDHCI > +#define CONFIG_SDHCI > +#define CONFIG_CMD_MMC > +#define CONFIG_MMC > +#define CONFIG_GENERIC_MMC > +#define CONFIG_DOS_PARTITION > +#define CONFIG_MMC_SDMA > +#define CONFIG_MMC_SDHCI_IO_ACCESSORS > + > /* > * mv-common.h should be defined after CMD configs since it used them > * to enable certain macros > -- > 1.8.3.rc3 > Acked-by: Pantelis Antoniou <panto(a)antoniou-consulting.com> > ************************************************************************************************************************************************************* > eInfochips Business Disclaimer : This e-mail message and all attachments transmitted with it are intended solely for the use of the addressee and may contain legally privileged and confidential information. If the reader of this message is not the intended recipient, or an employee or agent responsible for delivering this message to the intended recipient, you are hereby notified that any dissemination, distribution, copying, or other use of this message or its attachments is strictly prohibited. If you have received this message in error, please notify the sender immediately by replying to this message and please delete it from your computer. Any views expressed in this message are those of the individual sender unless otherwise stated. Company has taken enough precautions to prevent the spread of viruses. However the company accepts no liability for any damage caused by any virus transmitted by this email. > ************************************************************************************************************************************************************* > > > --------------------------------------------------------------------------------------------- > Notice: > This message has been scanned by Trend Micro Mail Security scanner and is believed to be clean > ---------------------------------------------------------------------------------------------

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Re: [U-Boot] [PATCH 1/2] Armada100: Adds SD/MMC Register definitions
by Pantelis Antoniou 24 Sep '13

24 Sep '13

Hi Ajay, On Sep 24, 2013, at 11:02 AM, Ajay Bhargav wrote: > This patch add SD/MMC interface register difinitions for Armada100 > series. > > Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> > --- > arch/arm/include/asm/arch-armada100/armada100.h | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h > index d9feb16..81e4b8a 100644 > --- a/arch/arm/include/asm/arch-armada100/armada100.h > +++ b/arch/arm/include/asm/arch-armada100/armada100.h > @@ -27,6 +27,14 @@ > #define SSP2_APBCLK 0x01 > #define SSP2_FNCLK 0x02 > > +/* SD Clock/Reset Control Register Bit definition */ > +#define SD1_SD2_AXI_RESET 0x01 > +#define SD1_RESET 0x02 > +#define SD1_SD2_AXICLK_EN 0x08 > +#define SD1_CLK_EN 0x10 > +#define SD2_RESET 0x02 > +#define SD2_CLK_EN 0x10 > + > /* USB Clock/reset control bits */ > #define USB_SPH_AXICLK_EN 0x10 > #define USB_SPH_AXI_RST 0x02 > @@ -53,6 +61,8 @@ > #define ARMD1_UART3_BASE 0xD4026000 > #define ARMD1_MPMU_BASE 0xD4050000 > #define ARMD1_USB_HOST_BASE 0xD4209000 > +#define ARMD1_SD1_BASE 0xD4280000 > +#define ARMD1_SD2_BASE 0xD4281000 > #define ARMD1_APMU_BASE 0xD4282800 > #define ARMD1_CPU_BASE 0xD4282C00 > > -- > 1.8.3.rc3 > Looks fine. Acked-by: Pantelis Antoniou <panto(a)antoniou-consulting.com> > ************************************************************************************************************************************************************* > eInfochips Business Disclaimer : This e-mail message and all attachments transmitted with it are intended solely for the use of the addressee and may contain legally privileged and confidential information. If the reader of this message is not the intended recipient, or an employee or agent responsible for delivering this message to the intended recipient, you are hereby notified that any dissemination, distribution, copying, or other use of this message or its attachments is strictly prohibited. If you have received this message in error, please notify the sender immediately by replying to this message and please delete it from your computer. Any views expressed in this message are those of the individual sender unless otherwise stated. Company has taken enough precautions to prevent the spread of viruses. However the company accepts no liability for any damage caused by any virus transmitted by this email. > ************************************************************************************************************************************************************* > > > --------------------------------------------------------------------------------------------- > Notice: > This message has been scanned by Trend Micro Mail Security scanner and is believed to be clean > ---------------------------------------------------------------------------------------------

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