June 2013 - U-Boot

[U-Boot] [PATCH] da850evm: Use clrbits function with correct endianess
by Christian Riesch 30 Jul '13

30 Jul '13

The current code uses clrbits_be32 which is incorrect since we are on a little endian machine here. This patch fixes this issue and also removes some unnecessary code: Reading the current GPIO bank state is not required if we are using the SET and CLEAR GPIO registers for setting/clearing bits. Signed-off-by: Christian Riesch <christian.riesch(a)omicron.at> Cc: Nagabhushana Netagunte <nagabhushana.netagunte(a)ti.com> Cc: Rajashekhara, Sudhakar <sudhakar.raj(a)ti.com> --- Hi, due to lack of hardware I only compile tested this code. I am looking forward to your comments. Regards, Christian board/davinci/da8xxevm/da850evm.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 0c7aabb..147013c 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -335,10 +335,6 @@ int board_early_init_f(void) int board_init(void) { -#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC) - u32 val; -#endif - #ifndef CONFIG_USE_IRQ irq_init(); #endif @@ -378,12 +374,10 @@ int board_init(void) #ifdef CONFIG_USE_NOR /* Set the GPIO direction as output */ - clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); + clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); /* Set the output as low */ - val = readl(GPIO_BANK0_REG_SET_ADDR); - val |= (0x01 << 11); - writel(val, GPIO_BANK0_REG_CLR_ADDR); + writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR); #endif #ifdef CONFIG_DAVINCI_MMC @@ -391,9 +385,7 @@ int board_init(void) clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); /* Set the output as high */ - val = readl(GPIO_BANK0_REG_SET_ADDR); - val |= (0x01 << 11); - writel(val, GPIO_BANK0_REG_SET_ADDR); + writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR); #endif #ifdef CONFIG_DRIVER_TI_EMAC -- 1.7.9.5

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[U-Boot] [PATCH] cfi_flash: Add prototypes of overridable functions
by Masahiro Yamada 30 Jul '13

30 Jul '13

This commit adds some prototypes into include/mtd/cfi_flash.h. These functions are defined with a weak attribute in drivers/mtd/cfi_flash.c. This means they can be overrided by board-specific ones if necessary. When defining such functions under board/ directory or somewhere, cfi_flash.h should be included. This makes sure that board-specfic cfi functions are defined in a correct prototype. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- include/mtd/cfi_flash.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index b644b91..f97cf66 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -184,5 +184,19 @@ extern int cfi_flash_num_flash_banks; void flash_write_cmd(flash_info_t * info, flash_sect_t sect, uint offset, u32 cmd); +phys_addr_t cfi_flash_bank_addr(int i); +unsigned long cfi_flash_bank_size(int i); +void flash_cmd_reset(flash_info_t *info); + +#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +void flash_write8(u8 value, void *addr); +void flash_write16(u16 value, void *addr); +void flash_write32(u32 value, void *addr); +void flash_write64(u64 value, void *addr); +u8 flash_read8(void *addr); +u16 flash_read16(void *addr); +u32 flash_read32(void *addr); +u64 flash_read64(void *addr); +#endif #endif /* __CFI_FLASH_H__ */ -- 1.8.1.2

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[U-Boot] [PATCH 0/9] TS-7800 port for U-Boot
by Michael Spang 29 Jul '13

29 Jul '13

The TS-7800 is an Orion5x implementation by Technologic Systems. Albert, Wolfgang - Thanks for reviewing my patch series and sorry for the delay in updating it. Changelog: - Fixed all checkpatch errors. - Updated copyright year. - Renamed CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT and introduced new CONFIG_SKIP_LOWLEVEL_INIT that skips only lowlevel_init. - Documented machine type ID workaround in the README. - Removed "ddr" from name of orion5x_ddr_addr_decode_registers. - Allow the environment to override the MAC even if CONFIG_PRESERVE_LOCAL_MAC is set. Michael Spang (9): arm926ej-s: Invalidate instruction cache in flush_cache mvgbe: Support preserving the existing MAC address orion5x: Increase maximum bank size to 128M orion5x: Fix wrong address in orion5x_sdram_bar ARM: Rename CONFIG_SKIP_LOWLEVEL_INIT to CONFIG_SKIP_CPU_INIT_CRIT ARM: Implement CONFIG_SKIP_LOWLEVEL_INIT for arm926ej-s Add board support for TS-7800 Add NAND support for TS-7800 Add README for TS-7800 MAKEALL | 1 + Makefile | 2 +- README | 8 +- arch/arm/cpu/arm1136/start.S | 6 +- arch/arm/cpu/arm720t/start.S | 2 +- arch/arm/cpu/arm920t/at91/lowlevel_init.S | 4 +- arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S | 4 +- arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 4 +- arch/arm/cpu/arm920t/start.S | 6 +- arch/arm/cpu/arm925t/start.S | 2 +- arch/arm/cpu/arm926ejs/at91/Makefile | 2 + arch/arm/cpu/arm926ejs/davinci/Makefile | 2 + arch/arm/cpu/arm926ejs/orion5x/Makefile | 2 + arch/arm/cpu/arm926ejs/orion5x/dram.c | 6 +- arch/arm/cpu/arm926ejs/start.S | 9 +- arch/arm/cpu/arm946es/start.S | 4 +- arch/arm/cpu/arm_intcm/start.S | 4 +- arch/arm/cpu/armv7/start.S | 2 +- arch/arm/cpu/lh7a40x/start.S | 2 +- arch/arm/cpu/s3c44b0/start.S | 2 +- arch/arm/cpu/sa1100/start.S | 2 +- arch/arm/include/asm/arch-orion5x/cpu.h | 2 +- arch/arm/include/asm/arch-orion5x/orion5x.h | 3 +- arch/arm/lib/cache.c | 2 + board/ns9750dev/lowlevel_init.S | 6 +- board/technologic/ts7800/Makefile | 46 ++++++ board/technologic/ts7800/ts7800.c | 36 +++++ boards.cfg | 1 + doc/README.ts7800 | 84 ++++++++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/ts7800_nand.c | 68 ++++++++ drivers/net/mvgbe.c | 20 +++ include/common.h | 2 +- include/configs/SMN42.h | 2 +- include/configs/a320evb.h | 2 +- include/configs/afeb9260.h | 2 +- include/configs/armadillo.h | 2 +- include/configs/aspenite.h | 2 +- include/configs/at91cap9adk.h | 2 +- include/configs/at91rm9200dk.h | 12 +- include/configs/at91rm9200ek.h | 6 +- include/configs/at91sam9260ek.h | 2 +- include/configs/at91sam9261ek.h | 2 +- include/configs/at91sam9263ek.h | 4 +- include/configs/at91sam9m10g45ek.h | 2 +- include/configs/at91sam9rlek.h | 2 +- include/configs/cmc_pu2.h | 4 +- include/configs/colibri_pxa270.h | 2 +- include/configs/cpuat91.h | 6 +- include/configs/csb637.h | 4 +- include/configs/da830evm.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/davinci_dm355evm.h | 2 +- include/configs/davinci_dm355leopard.h | 2 +- include/configs/davinci_dm365evm.h | 2 +- include/configs/davinci_dm6467evm.h | 2 +- include/configs/davinci_dvevm.h | 6 +- include/configs/davinci_schmoogie.h | 2 +- include/configs/davinci_sffsdr.h | 2 +- include/configs/davinci_sonata.h | 6 +- include/configs/dkb.h | 2 +- include/configs/dnp1110.h | 2 +- include/configs/dockstar.h | 2 +- include/configs/ea20.h | 2 +- include/configs/evb4510.h | 2 +- include/configs/gcplus.h | 4 +- include/configs/guruplug.h | 2 +- include/configs/hawkboard.h | 2 +- include/configs/integratorap.h | 2 +- include/configs/integratorcp.h | 6 +- include/configs/kb9202.h | 2 +- include/configs/km_arm.h | 2 +- include/configs/lpc2292sodimm.h | 2 +- include/configs/meesc.h | 2 +- include/configs/mp2usb.h | 4 +- include/configs/mv88f6281gtw_ge.h | 2 +- include/configs/mx31pdk.h | 2 +- include/configs/nhk8815.h | 2 +- include/configs/openrd_base.h | 2 +- include/configs/otc570.h | 2 +- include/configs/pm9261.h | 2 +- include/configs/pm9263.h | 2 +- include/configs/pm9g45.h | 2 +- include/configs/pxa255_idp.h | 2 +- include/configs/rd6281a.h | 2 +- include/configs/sbc2410x.h | 2 +- include/configs/sbc35_a9g20.h | 2 +- include/configs/shannon.h | 2 +- include/configs/sheevaplug.h | 2 +- include/configs/tegra2-common.h | 2 +- include/configs/tny_a9260.h | 2 +- include/configs/top9000.h | 2 +- include/configs/ts7800.h | 193 +++++++++++++++++++++++ include/configs/tx25.h | 2 +- include/configs/zipitz2.h | 2 +- 95 files changed, 585 insertions(+), 117 deletions(-) create mode 100644 board/technologic/ts7800/Makefile create mode 100644 board/technologic/ts7800/ts7800.c create mode 100644 doc/README.ts7800 create mode 100644 drivers/mtd/nand/ts7800_nand.c create mode 100644 include/configs/ts7800.h -- 1.7.2.3

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[U-Boot] [PATCH v5 0/7] Add cros-ec protocol driver and enable it in smdk5250
by Hung-ying Tyan 28 Jul '13

28 Jul '13

This patch series adds the drivers for the cros-ec protocol that is used to communicate with the Chrome OS Embedded Controller (EC). The series also enables its use in Google Snow which is based on smdk5250. The last patch in this series depends on the patch in the MMC series that brings in exynos5-dt.c: http://patchwork.ozlabs.org/patch/240084. ----- Changes in v5: - Change ec-interrupt gpio pin from 174 to 782. This has to be changed again after the GPIO pin numbering patches (http://patchwork.ozlabs.org/patch/233417) are in. - Add exynos: tag wherever applicable. - Add/change dependency description. Changes in v4: - Removed unrelated exynos-spi.txt. - Moved cros-ec-keyb.txt to the cros-ec-keyb patch. - Removed old code and comment. Changes in v3: - Rearranged #include directives in alphabetical order. - Removed outdated TODO and irrelevant bug reference in comments. Changes in v2: - Moved code from smdk5250.c (non-FDT) to exynos5-dt.c (FDT). - Moved code from smdk5250.h to exynos5250-dt.h. - Added gpio node to exynos5250.dtsi. - Fixed warnings of exceeding 80 chars in a line. - Added commit message. - Dropped the period from commit subject. Hung-ying Tyan (7): cros: add cros_ec driver cros: add I2C support for cros_ec cros: exynos: add SPI support for cros_ec cros: add LPC support for cros_ec cros: adds cros_ec keyboard driver cros: exynos: add cros-ec device nodes to exynos5250-snow.dts cros: exynos: enable cros-ec for smdk5250 README | 5 + arch/arm/dts/exynos5250.dtsi | 3 + board/samsung/dts/exynos5250-snow.dts | 81 ++ board/samsung/smdk5250/exynos5-dt.c | 45 + doc/device-tree-bindings/input/cros-ec-keyb.txt | 79 ++ doc/device-tree-bindings/misc/cros-ec.txt | 38 + drivers/input/Makefile | 1 + drivers/input/cros_ec_keyb.c | 261 ++++ drivers/misc/Makefile | 4 + drivers/misc/cros_ec.c | 1304 ++++++++++++++++++++ drivers/misc/cros_ec_i2c.c | 199 ++++ drivers/misc/cros_ec_lpc.c | 283 +++++ drivers/misc/cros_ec_spi.c | 161 +++ drivers/spi/exynos_spi.c | 22 + include/configs/exynos5250-dt.h | 10 +- include/cros_ec.h | 449 +++++++ include/cros_ec_message.h | 44 + include/ec_commands.h | 1440 +++++++++++++++++++++++ include/fdtdec.h | 2 + include/spi.h | 16 + lib/fdtdec.c | 2 + 21 files changed, 4448 insertions(+), 1 deletion(-) create mode 100644 doc/device-tree-bindings/input/cros-ec-keyb.txt create mode 100644 doc/device-tree-bindings/misc/cros-ec.txt create mode 100644 drivers/input/cros_ec_keyb.c create mode 100644 drivers/misc/cros_ec.c create mode 100644 drivers/misc/cros_ec_i2c.c create mode 100644 drivers/misc/cros_ec_lpc.c create mode 100644 drivers/misc/cros_ec_spi.c create mode 100644 include/cros_ec.h create mode 100644 include/cros_ec_message.h create mode 100644 include/ec_commands.h -- 1.8.2.1

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[U-Boot] [PATCH] dfu, nand: before write a buffer to nand, erase the nand sectors
by Heiko Schocher 27 Jul '13

27 Jul '13

before writing the received buffer to nand, erase the nand sectors. If not doing this, nand write fails. See for more info here: http://lists.denx.de/pipermail/u-boot/2013-June/156361.html Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Scott Wood <scottwood(a)freescale.com> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Kyungmin Park <kyungmin.park(a)samsung.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)ti.com> --- common/cmd_nand.c | 2 +- drivers/dfu/dfu_nand.c | 17 +++++++++++++++-- include/nand.h | 1 + 3 Dateien geändert, 17 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 8b1e01a..d3fe138 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -428,7 +428,7 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count, /* Adjust a chip/partition size down for bad blocks so we don't * read/write/erase past the end of a chip/partition by accident. */ -static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev) +void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev) { /* We grab the nand info object here fresh because this is usually * called after arg_off_size() which can change the value of dev. diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index 7dc89b2..6f9a934 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -63,12 +63,25 @@ static int nand_block_op(enum dfu_nand_op op, struct dfu_entity *dfu, nand = &nand_info[nand_curr_device]; - if (op == DFU_OP_READ) + if (op == DFU_OP_READ) { ret = nand_read_skip_bad(nand, start, &count, &actual, lim, buf); - else + } else { + nand_erase_options_t opts; + + memset(&opts, 0, sizeof(opts)); + opts.offset = start; + opts.length = count; + adjust_size_for_badblocks(&opts.length, offset, + nand_curr_device); + /* first erase */ + ret = nand_erase_opts(nand, &opts); + if (ret) + return ret; + /* then write */ ret = nand_write_skip_bad(nand, start, &count, &actual, lim, buf, 0); + } if (ret != 0) { printf("%s: nand_%s_skip_bad call failed at %llx!\n", diff --git a/include/nand.h b/include/nand.h index 26190e4..8495b73 100644 --- a/include/nand.h +++ b/include/nand.h @@ -141,6 +141,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, size_t *actual, loff_t lim, u_char *buffer, int flags); int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); int nand_torture(nand_info_t *nand, loff_t offset); +void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev); #define NAND_LOCK_STATUS_TIGHT 0x01 #define NAND_LOCK_STATUS_UNLOCK 0x04 -- 1.7.11.7

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[U-Boot] [PATCH v5 0/6] Update gdsys ppc4xx-based boards
by dirk.eibach＠gdsys.cc 26 Jul '13

26 Jul '13

From: Dirk Eibach <dirk.eibach(a)gdsys.cc> This series depends on i2c multibus support. It was rebased on the latest multibus branch at http://git.denx.de/?p=u-boot/u-boot-i2c.git;a=shortlog;h=refs/heads/2013062… Patch "powerpc/ppc4xx: Add bitbang i2c interface for gdsys boards" was dropped in favor of using the new framework. Changes in v5: - add board/gdsys/common/fpga.c which was forgotten in v4 Changes in v4: - Move changes ins osd.c to proper commit - Move unrelated changes ins osd.c to proper commit - do not use common FPGA register accessors here - explain why fpga_gpio_ functions are actually useful - factor out common code for fpga register access - use macro instead of #ifdef for reflection test Changes in v3: - adapt to "powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA" - squashed with "Add generic accessor functions for gdsys FPGA" - squashed with "powerpc/ppc4xx: Increase timeout for gdsys mclink bus startup" - squashed with powerpc/ppc4xx: Fixup phy erratum on gdsys iocon hardware - strictly replace base address plus offset with proper C structs Changes in v2: - fpga_state has been moved to arch_global_data - include cmd_fpgad in iocon - move cmd_fpgad to common and fix whitespace issues - update email account - use multibus soft-i2c in iocon Dirk Eibach (6): powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA powerpc/ppc4xx: Add gdsys mclink interface powerpc/ppc4xx: Add fpgad command for dumping gdsys fpga registers powerpc/ppc4xx: Support gdsys multichannel iocon hardware powerpc/ppc4xx: Consider gdsys FPGA OSD size powerpc/ppc4xx: Remove CONFIG_SYS_FLASH_PROTECTION from gdsys boards board/gdsys/405ep/405ep.c | 22 +- board/gdsys/405ep/dlvision-10g.c | 18 +- board/gdsys/405ep/io.c | 16 +- board/gdsys/405ep/iocon.c | 486 +++++++++++++++++++++++++++++++++++---- board/gdsys/405ep/neo.c | 13 +- board/gdsys/405ex/405ex.c | 22 +- board/gdsys/405ex/io64.c | 34 +-- board/gdsys/common/Makefile | 4 +- board/gdsys/common/fpga.c | 41 ++++ board/gdsys/common/mclink.c | 153 ++++++++++++ board/gdsys/common/mclink.h | 31 +++ board/gdsys/common/osd.c | 118 ++++++---- common/Makefile | 1 + common/cmd_fpgad.c | 100 ++++++++ include/configs/dlvision-10g.h | 9 +- include/configs/dlvision.h | 3 +- include/configs/io.h | 8 +- include/configs/io64.h | 6 + include/configs/iocon.h | 60 ++++- include/configs/neo.h | 8 +- include/gdsys_fpga.h | 58 ++++- 21 files changed, 1040 insertions(+), 171 deletions(-) create mode 100644 board/gdsys/common/fpga.c create mode 100644 board/gdsys/common/mclink.c create mode 100644 board/gdsys/common/mclink.h create mode 100644 common/cmd_fpgad.c -- 1.8.3

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[U-Boot] [PATCH v2 01/10] ARM: move interrupt_init to before relocation
by Rob Herring 25 Jul '13

25 Jul '13

From: Rob Herring <rob.herring(a)calxeda.com> interrupt_init also sets up the abort stack, but is not setup before relocation. So any aborts during relocation will hang and not print out any useful information. Fix this by moving the interrupt_init to after the stack setup in board_init_f. Signed-off-by: Rob Herring <rob.herring(a)calxeda.com> --- v2: - Remove interrupt_init from board_init_r arch/arm/lib/board.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 09ab4ad..c90843e 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -447,6 +447,7 @@ void board_init_f(ulong bootflag) addr_sp += 128; /* leave 32 words for abort-stack */ gd->irq_sp = addr_sp; #endif + interrupt_init(); debug("New Stack Pointer is: %08lx\n", addr_sp); @@ -648,8 +649,6 @@ void board_init_r(gd_t *id, ulong dest_addr) misc_init_r(); #endif - /* set up exceptions */ - interrupt_init(); /* enable exceptions */ enable_interrupts(); -- 1.8.1.2

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[U-Boot] PPC4XX Custom Board - Failing to read I2C
by txcotrader 25 Jul '13

25 Jul '13

Hello, I'm looking for some direction. I'm trying to update my version of u-boot for a custom board based off of the PPC460SX. I'm struggling to understand why I cannot get past reading the I2C on the DIMM. I'm receiving this error: CPU: AMCC PowerPC 460SX Rev. A at 231.291 MHz (PLB=33 OPB=16 EBC=4) Security support Bootstrap Option A - Boot ROM Location EBC (8 bits) Internal PCI arbiter enabled 32 kB I-Cache 32 kB D-Cache Board: x Processor Board - AMCC 460SX *** DEBUG: NDFC register configurations *** SDR0_EBC = 0x30011ffe SDR0_NFC0 = 0x411b0683 SDR0_PFC1 = 0x41120000 EBC0_B0CR = 0xff08a000 EBC0_B0AP = 0x10055e00 EBC0_B1CR = 0xd1018000 EBC0_B1AP = 0x018003c0 EBC0_B2CR = 0xd0018000 EBC0_B2AP = 0x03804240 EBC0_B3CR = 0x00000000 EBC0_B3AP = 0x00000000 SDR0_SDSTP0 = 0xb40b3149 SDR0_SDSTP1 = 0xe8000210 SDR0_SDSTP2 = 0x00002030 SDR0_SDSTP3 = 0xc3001380 CPR0_PLL0C = 0x40000340 CPR0_PLL1C = 0x40000340 CPR0_PLL0D = 0xb3010600 CPR0_PLL1D = 0x00010600 CPR0_PLBD = 0x04000000 CPR0_OPBD = 0x02000000 CPR0_PERD = 0x01000000 CPR0_ICFG = 0x00000000 CPR0_DDRD = 0x02000000 L2: 512KB EBC_BXAP_FPGA: 03804240 EBC_BXCR_FPGA_CS2: d0018000 I2C: ready DRAM: spd_read(0x50) returned 0 spd_read(0x50) returned 0 DIMM slot 0: Not populated ERROR - No memory installed. Install a DDR-SDRAM DIMM. I2C configs: #define CONFIG_I2C_MULTI_BUS 1 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ /*#define CONFIG_SYS_I2C_MULTI_EEPROMS*/ #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* I2C bootstrap EEPROM */ #define IIC0_BOOTPROM_ADDR 0x54 #define IIC0_PLX_FPGA_ADDR 0x69 #define IIC0_PLX_PPC_ADDR 0x6A /* I2C bootstrap EEPROM */ #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 /* RTC configuration */ #define CONFIG_RTC_DS1337 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 I found myself digging pretty deep into i2c_transfer.c but I think there is a configuration error. Any advice would be greatly appreciated. Thank you -- View this message in context: http://u-boot.10912.n7.nabble.com/PPC4XX-Custom-Board-Failing-to-read-I2C-t… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH V2 0/9] rely on latest dtc, simplify
by Stephen Warren 24 Jul '13

24 Jul '13

From: Stephen Warren <swarren(a)nvidia.com> This is a series of patches which simplifies the rules to build *.dts in U-Boot by relying on features in the latest dtc. The include rules are made more consistent between cpp (when processing *.dts) and dtc. The cpp flags are made more consistent with the way the kernel processes *.dts to allow better portability of *.dts between the two. I'm sending V2 now that dtc-1.4.0 has been tagged/released, and hence there's a version number that patch 1/9 "Validate dtc is new enough" can check for. I'll leave it up to you whether this series is applicable for the current or next release. Stephen Warren (9): Validate dtc is new enough xilinx: move microblaze-generic .dts to standard location dts/Makefile: simplify dtc invocation dts/Makefile: unify cpp/dtc include paths dt: don't use ARCH_CPU_DTS dts/Makefile: don't define ARCH_CPU_DTS, BOARD_DTS config: don't define CONFIG_ARCH_DEVICE_TREE dts/Makefile: don't use cpp -P dts/Makefile: pass -undef -D__DTS__ to cpp .gitignore | 1 + Makefile | 8 ++++++- arch/arm/cpu/armv7/tegra114/config.mk | 19 ---------------- arch/arm/cpu/armv7/tegra20/config.mk | 26 ---------------------- arch/arm/cpu/armv7/tegra30/config.mk | 19 ---------------- arch/microblaze/config.mk | 2 -- arch/x86/cpu/coreboot/config.mk | 23 ------------------- board/chromebook-x86/dts/link.dts | 2 +- board/samsung/dts/exynos5250-smdk5250.dts | 2 +- board/samsung/dts/exynos5250-snow.dts | 2 +- .../microblaze.dts => dts/microblaze-generic.dts} | 0 board/xilinx/dts/microblaze.dts | 1 - config.mk | 1 + doc/README.fdt-control | 3 +-- dts/Makefile | 25 +++++++++------------ include/configs/exynos5250-dt.h | 1 - include/configs/microblaze-generic.h | 2 +- tools/dtc-version.sh | 20 +++++++++++++++++ 18 files changed, 44 insertions(+), 113 deletions(-) delete mode 100644 arch/arm/cpu/armv7/tegra114/config.mk delete mode 100644 arch/arm/cpu/armv7/tegra20/config.mk delete mode 100644 arch/arm/cpu/armv7/tegra30/config.mk delete mode 100644 arch/x86/cpu/coreboot/config.mk rename board/xilinx/{microblaze-generic/dts/microblaze.dts => dts/microblaze-generic.dts} (100%) delete mode 100644 board/xilinx/dts/microblaze.dts create mode 100755 tools/dtc-version.sh -- 1.8.1.5

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[U-Boot] [PATCH 1/4] nds32: Enable two banks of SDRAM on Andes board
by Kuan-Yu Kuo 24 Jul '13

24 Jul '13

The original adp-ag101/adp-ag101p initialize only one bank(64MB) by default at boot time, but it is not enough for some application, so increasing to two banks(128M). Signed-off-by: Kuan-Yu Kuo <ken.kuoky(a)gmail.com> Cc: Macpaul Lin <macpaul(a)gmail.com> --- arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 6 +++++- board/AndesTech/adp-ag101/adp-ag101.c | 10 +++++++++- board/AndesTech/adp-ag101p/adp-ag101p.c | 10 +++++++++- include/configs/adp-ag101.h | 10 +++++++++- include/configs/adp-ag101p.h | 9 ++++++++- 5 files changed, 40 insertions(+), 5 deletions(-) diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index 29c93fe..55985cf 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -38,6 +38,7 @@ #define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1) #define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2) #define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR) +#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR) #define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1 #define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2 @@ -45,6 +46,7 @@ #define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2 #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR +#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR /* * parameters for the static memory controller @@ -167,12 +169,12 @@ relo_base: */ led 0x1a write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100 + write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001140 /* clear empty BSR registers */ led 0x1b li $r4, CONFIG_FTSDMC021_BASE li $r5, 0x0 - swi $r5, [$r4 + FTSDMC021_BANK1_BSR] swi $r5, [$r4 + FTSDMC021_BANK2_BSR] swi $r5, [$r4 + FTSDMC021_BANK3_BSR] @@ -223,6 +225,8 @@ relo_base: * - after remap: flash/rom 0x80000000, sdram: 0x00000000 */ led 0x1c + write32 SDMC_B0_BSR_A, 0x00001000 + write32 SDMC_B1_BSR_A, 0x00001040 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1 #endif /* #ifdef CONFIG_MEM_REMAP */ diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c index 82ce4c9..ebc20a5 100644 --- a/board/AndesTech/adp-ag101/adp-ag101.c +++ b/board/AndesTech/adp-ag101/adp-ag101.c @@ -50,7 +50,7 @@ int board_init(void) int dram_init(void) { unsigned long sdram_base = PHYS_SDRAM_0; - unsigned long expected_size = PHYS_SDRAM_0_SIZE; + unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; unsigned long actual_size; actual_size = get_ram_size((void *)sdram_base, expected_size); @@ -65,6 +65,14 @@ int dram_init(void) return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; +} + int board_eth_init(bd_t *bd) { return ftmac100_initialize(bd); diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c index 8dd2043..26d67e2 100644 --- a/board/AndesTech/adp-ag101p/adp-ag101p.c +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -50,7 +50,7 @@ int board_init(void) int dram_init(void) { unsigned long sdram_base = PHYS_SDRAM_0; - unsigned long expected_size = PHYS_SDRAM_0_SIZE; + unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; unsigned long actual_size; actual_size = get_ram_size((void *)sdram_base, expected_size); @@ -65,6 +65,14 @@ int dram_init(void) return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; +} + int board_eth_init(bd_t *bd) { return ftmac100_initialize(bd); diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h index b6e3844..1b84b04 100644 --- a/include/configs/adp-ag101.h +++ b/include/configs/adp-ag101.h @@ -235,6 +235,11 @@ #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ CONFIG_SYS_FTSDMC021_BANK0_BASE) +#define CONFIG_SYS_FTSDMC021_BANK1_BASE \ + (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) +#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ + CONFIG_SYS_FTSDMC021_BANK1_BASE) + #endif /* @@ -248,9 +253,12 @@ #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ #endif +#define PHYS_SDRAM_1 \ + (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index ef55e35..cec89f6 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -236,6 +236,10 @@ #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ CONFIG_SYS_FTSDMC021_BANK0_BASE) +#define CONFIG_SYS_FTSDMC021_BANK1_BASE \ + (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) +#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ + CONFIG_SYS_FTSDMC021_BANK1_BASE) #endif /* @@ -249,9 +253,12 @@ #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ #endif +#define PHYS_SDRAM_1 \ + (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 -- 1.7.9.5

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