June 2013 - U-Boot

[U-Boot] [PATCH V3] ARM: OMAP5: Power: Add more functionality to Palmas driver
by Lubomir Popov 06 Jun '13

06 Jun '13

Add some useful functions, and the corresponding definitions. Add support for powering on the dra7xx_evm SD/MMC LDO (courtesy Lokesh Vutla <lokeshvutla(a)ti.com>). Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- V3 does some cleanup and adds support for the dra7xx_evm board (power on LDO1 used for the SD/MMC interface). V2 aligns to changed PMIC name (and file names accordingly) from twl6035 to Palmas and is based on current u-boot-ti master. drivers/power/palmas.c | 130 +++++++++++++++++++++++++++++++++++++++++++----- include/palmas.h | 90 ++++++++++++++++++++++++++++++--- 2 files changed, 201 insertions(+), 19 deletions(-) diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 09c832d..6c60b5f 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -25,28 +25,134 @@ void palmas_init_settings(void) { - return; +#ifdef CONFIG_PALMAS_SMPS7_FPWM + int err; + /* + * Set SMPS7 (1.8 V I/O supply on platforms with TWL6035/37) to + * forced PWM mode. This reduces noise (but affects efficiency). + */ + u8 val = SMPS_MODE_SLP_FPWM | SMPS_MODE_ACT_FPWM; + if ((err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS7_CTRL, val))) + printf("palmas: could not force PWM for SMPS7: err = %d\n", + err); +#endif } int palmas_mmc1_poweron_ldo(void) { u8 val = 0; - /* set LDO9 TWL6035 to 3V */ - val = 0x2b; /* (3 -.9)*28 +1 */ - - if (palmas_i2c_write_u8(0x48, LDO9_VOLTAGE, val)) { - printf("twl6035: could not set LDO9 voltage.\n"); +#if defined(CONFIG_DRA7XX) + /* + * Currently valid for the dra7xx_evm board: + * Set TPS659038 LDO1 to 3.0 V + */ + val = LDO_VOLT_3V0; + if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, val)) { + printf("tps65903x: could not set LDO1 voltage.\n"); + return 1; + } + /* TURN ON LDO1 */ + val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val)) { + printf("tps65903x: could not turn on LDO1.\n"); return 1; } + return 0; +#else + /* + * We assume that this is a OMAP543X + TWL603X board: + * Set TWL6035/37 LDO9 to 3.0 V + */ + val = LDO_VOLT_3V0; + return twl603x_mmc1_set_ldo9(val); +#endif +} - /* TURN ON LDO9 */ - val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; +/* + * On some OMAP5 + TWL603X hardware the SD card socket and LDO9_IN are + * powered by an external 3.3 V regulator, while the output of LDO9 + * supplies VDDS_SDCARD for the OMAP5 interface only. This implies that + * LDO9 could be set to 'bypass' mode when required (e.g. for 3.3 V cards). + */ +int twl603x_mmc1_set_ldo9(u8 vsel) +{ + u8 cval=0, vval=0; /* Off by default */ + int err; - if (palmas_i2c_write_u8(0x48, LDO9_CTRL, val)) { - printf("twl6035: could not turn on LDO9.\n"); - return 1; + if (vsel) { + /* Turn on */ + if (vsel > LDO_VOLT_3V3) { + /* Put LDO9 in bypass */ + cval = LDO9_BYP_EN | RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + vval = LDO_VOLT_3V3; + } + else { + cval = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + vval = vsel & 0x3f; + } + } + if ((err = palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_VOLTAGE, vval))) { + printf("twl603x: could not set LDO9 %s: err = %d\n", + vsel > LDO_VOLT_3V3 ? "bypass" : "voltage", err); + return err; } + if ((err = palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_CTRL, cval))) + printf("twl603x: could not turn %s LDO9: err = %d\n", + cval ? "on" : "off", err); + return err; +} - return 0; +#ifdef CONFIG_PALMAS_AUDPWR +/* + * Turn audio codec power and 32 kHz clock on/off. Use for + * testing OMAP543X + TWL603X + TWL604X boards only. + */ +int twl603x_audio_power(u8 on) +{ + u8 cval=0, vval=0, c32k=0; + int err; + + if (on) { + vval = SMPS_VOLT_2V1; + cval = SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO; + c32k = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + } + /* Set SMPS9 to 2.1 V (for TWL604x), or to 0 (off) */ + if ((err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS9_VOLTAGE, + vval))) { + printf("twl603x: could not set SMPS9 voltage: err = %d\n", + err); + return err; + } + /* Turn on or off SMPS9 */ + if ((err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS9_CTRL, cval))) { + printf("twl603x: could not turn SMPS9 %s: err = %d\n", + cval ? "on" : "off", err); + return err; + } + /* Output 32 kHz clock on or off */ + if ((err = palmas_i2c_write_u8(TWL603X_CHIP_P1, CLK32KGAUDIO_CTRL, + c32k))) + printf("twl603x: could not turn CLK32KGAUDIO %s: err = %d\n", + c32k ? "on" : "off", err); + return err; } +#endif + +/* + * Enable/disable back-up battery (or super cap) charging on TWL6035/37. + * Please use defined BB_xxx values. + */ +int twl603x_enable_bb_charge(u8 bb_fields) +{ + u8 val = bb_fields & 0x0f; + int err; + + val |= (VRTC_EN_SLP | VRTC_EN_OFF | VRTC_PWEN); + if ((err = palmas_i2c_write_u8(TWL603X_CHIP_P1, BB_VRTC_CTRL, val))) + printf("twl603x: could not set BB_VRTC_CTRL to 0x%02x: err = %d\n", + val, err); + return err; +} + diff --git a/include/palmas.h b/include/palmas.h index 3b18589..aff48b5 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -26,17 +26,90 @@ #include <common.h> #include <i2c.h> -/* I2C chip addresses */ -#define PALMAS_CHIP_ADDR 0x48 +/* I2C chip addresses, TW6035/37 */ +#define TWL603X_CHIP_P1 0x48 /* Page 1 */ +#define TWL603X_CHIP_P2 0x49 /* Page 2 */ +#define TWL603X_CHIP_P3 0x4a /* Page 3 */ -/* 0x1XY translates to page 1, register address 0xXY */ +/* TPS659038/39 */ +#define TPS65903X_CHIP_P1 0x58 /* Page 1 */ + +/* Page 1 registers (0x1XY translates to page 1, reg addr 0xXY): */ + +/* LDO1 control/voltage */ +#define LDO1_CTRL 0x50 +#define LDO1_VOLTAGE 0x51 + +/* LDO9 control/voltage */ #define LDO9_CTRL 0x60 #define LDO9_VOLTAGE 0x61 -/* Bit field definitions for LDOx_CTRL */ -#define LDO_ON (1 << 4) -#define LDO_MODE_SLEEP (1 << 2) -#define LDO_MODE_ACTIVE (1 << 0) +/* LDOUSB control/voltage */ +#define LDOUSB_CTRL 0x64 +#define LDOUSB_VOLTAGE 0x65 + +/* Control of 32 kHz audio clock */ +#define CLK32KGAUDIO_CTRL 0xd5 + +/* SYSEN2_CTRL for VCC_3v3_AUX supply on the sEVM */ +#define SYSEN2_CTRL 0xd9 + +/* + * Bit field definitions for LDOx_CTRL, SYSENx_CTRL + * and some other xxx_CTRL resources: + */ +#define LDO9_BYP_EN (1 << 6) /* LDO9 only! */ +#define RSC_STAT_ON (1 << 4) /* RO status bit! */ +#define RSC_MODE_SLEEP (1 << 2) +#define RSC_MODE_ACTIVE (1 << 0) + +/* Some LDO voltage values */ +#define LDO_VOLT_OFF 0 +#define LDO_VOLT_1V8 0x13 +#define LDO_VOLT_3V0 0x2b +#define LDO_VOLT_3V3 0x31 +/* Request bypass, LDO9 only */ +#define LDO9_BYPASS 0x3f + +/* SMPS7_CTRL */ +#define SMPS7_CTRL 0x30 + +/* SMPS9_CTRL */ +#define SMPS9_CTRL 0x38 +#define SMPS9_VOLTAGE 0x3b + +/* Bit field definitions for SMPSx_CTRL */ +#define SMPS_MODE_ACT_AUTO 1 +#define SMPS_MODE_ACT_ECO 2 +#define SMPS_MODE_ACT_FPWM 3 +#define SMPS_MODE_SLP_AUTO (1 << 2) +#define SMPS_MODE_SLP_ECO (2 << 2) +#define SMPS_MODE_SLP_FPWM (3 << 2) + +/* + * Some popular SMPS voltages, all with RANGE=1; note + * that RANGE cannot be changed on the fly + */ +#define SMPS_VOLT_OFF 0 +#define SMPS_VOLT_1V2 0x90 +#define SMPS_VOLT_1V8 0xae +#define SMPS_VOLT_2V1 0xbd +#define SMPS_VOLT_3V0 0xea +#define SMPS_VOLT_3V3 0xf9 + +/* Backup Battery & VRTC Control */ +#define BB_VRTC_CTRL 0xa8 +/* Bit definitions for BB_VRTC_CTRL */ +#define VRTC_EN_SLP (1 << 6) +#define VRTC_EN_OFF (1 << 5) +#define VRTC_PWEN (1 << 4) +#define BB_LOW_ICHRG (1 << 3) +#define BB_HIGH_ICHRG (0 << 3) +#define BB_VSEL_3V0 (0 << 1) +#define BB_VSEL_2V5 (1 << 1) +#define BB_VSEL_3V15 (2 << 1) +#define BB_VSEL_VBAT (3 << 1) +#define BB_CHRG_EN (1 << 0) /* * Functions to read and write from TPS659038/TWL6035/TWL6037 @@ -54,5 +127,8 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) void palmas_init_settings(void); int palmas_mmc1_poweron_ldo(void); +int twl603x_mmc1_set_ldo9(u8 vsel); +int twl603x_audio_power(u8 on); +int twl603x_enable_bb_charge(u8 bb_fields); #endif /* PALMAS_H */ -- 1.7.9.5

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[U-Boot] imx: Vybrid VF610 mac address issue
by Andy Voltz 06 Jun '13

06 Jun '13

I recently tried booting the VF610 support on the Tower board, but the mac address is reversed in Linux userspace. DHCP/BOOTP seems to work properly in u-boot. I'm booting this kernel: https://github.com/Timesys/linux-timesys/ ref: 2c4ead2dd6da019f5052a69b12c8f5b6b71f8dca I haven't yet seen how the address is passed to the kernel, but our previous u-boot support does not have this issue with the same kernel. That u-boot branch is also on our github. Any ideas? Thanks -- Andy Voltz Timesys Corporation

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[U-Boot] ASM code for UART initialization
by André Schaller 06 Jun '13

06 Jun '13

Hi, could someone support me with developing ASM code for initializing UART interface on OMAP4460 to send some bytes over the wire at a very early stage of booting x-loader? The code needs to be executed in start.S. Is it possible to use existing C code and use the generated assembly from gcc as the actual code or does it need major modifications to be executed in start.S? Thanks in advance. Regards, André

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[U-Boot] [PATCH v2] OMAP5: Fix bug in omap5_es1_prcm struct
by Lubomir Popov 06 Jun '13

06 Jun '13

The newly introduced function setup_warmreset_time(), called from within prcm_init(), tries to write to the prm_rsttime OMAP5 register. The struct member holding this register's address is however initialized for OMAP5 ES2.0 only. On ES1.0 devices this uninitialized value causes a second (warm) reset at startup. Add .prm_rsttime address init to the ES1.0 struct. Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- V2 gives the correct prm_rsttime reg address for ES1.0. Copy-paste from ES2.0 in V1, sorry. arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index e9f6a32..f29ac77 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -298,6 +298,7 @@ struct prcm_regs const omap5_es1_prcm = { .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, .prm_rstctrl = 0x4ae07b00, .prm_rstst = 0x4ae07b04, + .prm_rsttime = 0x4ae07b08, .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, -- 1.7.12.4 (Apple Git-37)

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[U-Boot] [PATCH 0/4] imx: nitrogen6x: Config changes
by Robert Winkler 06 Jun '13

06 Jun '13

These are just some config changes for nitrogen6x. RAW_INITRD, BOOTZ, FS_GENERIC are being used by this project http://www.eewiki.net/display/linuxonarm/i.MX6x+SABRE+Lite DCACHE can finally be enabled because some related bugs have been fixed. Robert Winkler (4): imx: nitrogen6x: Enabled data cache imx: nitrogen6x: Enable bootz imx: nitrogen6x: Enable raw initrd imx: nitrogen6x: Enable filesystem generic commands include/configs/nitrogen6x.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 1.8.3

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[U-Boot] [PATCH] Add SPI Flash STMicro's N25Q512A & add flag status check during SPI Flash write
by Insop Song 06 Jun '13

06 Jun '13

Hi, I've made two changes while I was working on STMidro's SPI Flash N25Q512A - add the device entry for STMidro's SPI Flash N25Q512A - add Flag status check during Without this flag checking "sf write" will fail and SPI flash is locked up Please see the patch and let me know your feedback. ------------------------------------- >From 97572b32c49d06ca6f8548ed88e6e381fb719a08 Mon Sep 17 00:00:00 2001 From: Insop Song <insop.song(a)cohere.net> Date: Sun, 2 Jun 2013 13:33:37 -0700 Subject: [PATCH] Add SPI Flash STMicro's N25Q512A & add flag status check during SPI Flash write Signed-off-by: Insop Song <insop.song(a)cohere.net> --- drivers/mtd/spi/spi_flash.c | 25 +++++++++++++++++++++++++ drivers/mtd/spi/spi_flash_internal.h | 1 + drivers/mtd/spi/stmicro.c | 6 ++++++ 3 files changed, 32 insertions(+) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 00aece9..f53756d 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -72,6 +72,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, size_t chunk_len, actual; int ret; u8 cmd[4]; + u8 flag_status; page_size = flash->page_size; page_addr = offset / page_size; @@ -83,6 +84,18 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, return ret; } +wait_flag: + ret = spi_flash_cmd(flash->spi, CMD_READ_FLAG_STATUS, &flag_status, sizeof(flag_status)); + if (ret < 0) { + printf("SF: reading flag failed\n"); + return ret; + } + debug("flag_status %d\n", flag_status); + if ((flag_status & 0x80) == 0) { + udelay(10); + goto wait_flag; + } + cmd[0] = CMD_PAGE_PROGRAM; for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); @@ -106,6 +119,18 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, debug("SF: write failed\n"); break; } + /* check status */ +flag_check: + ret = spi_flash_cmd(flash->spi, CMD_READ_FLAG_STATUS, &flag_status, sizeof(flag_status)); + if (ret < 0) { + printf("SF: reading flag failed\n"); + break; + } + debug("flag_status %d\n", flag_status); + if (!(flag_status & 0x80)) { + udelay(100); + goto flag_check; + } ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); if (ret) diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 141cfa8..90b6993 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -22,6 +22,7 @@ #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 +#define CMD_READ_FLAG_STATUS 0x70 #define CMD_WRITE_ENABLE 0x06 #define CMD_ERASE_4K 0x20 #define CMD_ERASE_32K 0x52 diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index 30b626a..ad94ad2 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -110,6 +110,12 @@ static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { .nr_sectors = 512, .name = "N25Q256", }, + { + .id = 0xba20, + .pages_per_sector = 256, + .nr_sectors = 1024, + .name = "N25Q512A", + }, }; struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) -- 1.7.9.5

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[U-Boot] [PATCH v2 00/16] sf: Update sf framework to support all sizes of flashes
by Jagannadha Sutradharudu Teki 06 Jun '13

06 Jun '13

This series is v2 for the patch series sent few weeks back with a head "sf: Accessing > 16MBytes flashes in existing 3-byte addr mode." The current implementation in sf supports 3-byte address mode due to this up to 16MB amount of flash is able to access for those flashes which has an actual size of > 16MB. This series of patches is more detailed/meatured changes w.r.t the current sf framework in addition to changes related to support all sizes using bank/exnt register addr accessing support. With these new updates on sf framework, the flashes which has < 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~600 bytes. sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s sf update(for first 16MBytes), Changes after: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s The main aim of these changes is to not effect the current framework and at the same time to support the > 16Mbyte flashes, becuase of this I involved few flash vendor people in CC [thought that they may/mayn't be a mailing list members] to know their views. REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE. Please let me know for any issues/concerns/questions. Thanks, Jagan. Jagannadha Sutradharudu Teki (16): sf: Add bank address register writing support sf: Add bank address register reading support sf: Add extended addr write support for winbond|stmicro sf: Add extended addr read support for winbond|stmicro sf: read flash bank addr register at probe time sf: Update sf to support all sizes of flashes sf: Update sf read to support all sizes of flashes sf: Use spi_flash_addr() in write call sf: stmicro: Add support for N25Q512 sf: stmicro: Add support for N25Q512A sf: stmicro: Add support for N25Q1024 sf: stmicro: Add support for N25Q1024A sf: spansion: Add support for S25FL512S_256K sf: Use spi_flash_read_common() in write status poll sf: Remove spi_flash_cmd_poll_bit() sf: Add Flag status register polling support drivers/mtd/spi/spansion.c | 7 ++ drivers/mtd/spi/spi_flash.c | 192 +++++++++++++++++++++++++++-------- drivers/mtd/spi/spi_flash_internal.h | 21 +++- drivers/mtd/spi/stmicro.c | 24 +++++ include/spi_flash.h | 4 + 5 files changed, 203 insertions(+), 45 deletions(-) -- 1.8.3

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[U-Boot] [PATCH V2] exynos: spl: Add a custom spi copy function
by Rajeshwari Shinde 06 Jun '13

06 Jun '13

This patch implements a custom spi_copy funtion to copy u-boot from SF to RAM. This is faster then iROM spi_copy funtion as this runs spi at 50Mhz and also in WORD mode of operation. Changed a printf in pinmux.c to debug just to avoid the compilation error in SPL. Removed enum for boot mode from spl_boot.c as it was already define in spl.h Based on "[PATCH V2] spi: exynos: Support word transfers" Signed-off-by: Alim Akhtar <alim.akhtar(a)samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong(a)chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> --- Changes in V2: - Corrected the commit message. - Added a SPI timeout check. - Corrected the comments. arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- arch/arm/include/asm/arch-exynos/spi.h | 2 + board/samsung/smdk5250/spl_boot.c | 136 ++++++++++++++++++++++++++++--- include/configs/exynos5250-dt.h | 3 + spl/Makefile | 4 + 5 files changed, 132 insertions(+), 15 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index bd499b4..c484a86 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -427,7 +427,7 @@ static int exynos4_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC3: case PERIPH_ID_SDMMC4: - printf("SDMMC device %d not implemented\n", peripheral); + debug("SDMMC device %d not implemented\n", peripheral); return -1; default: debug("%s: invalid peripheral %d", __func__, peripheral); diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h index e67ad27..3430ac1 100644 --- a/arch/arm/include/asm/arch-exynos/spi.h +++ b/arch/arm/include/asm/arch-exynos/spi.h @@ -43,6 +43,8 @@ struct exynos_spi { #define SPI_TIMEOUT_MS 10 +#define SF_READ_DATA_CMD 0x3 + /* SPI_CHCFG */ #define SPI_CH_HS_EN (1 << 6) #define SPI_CH_RST (1 << 5) diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index c0bcf46..85a5d68 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -22,17 +22,13 @@ #include<common.h> #include<config.h> +#include <asm/arch/clk.h> +#include <asm/arch/spi.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/periph.h> +#include <asm/arch/spl.h> -enum boot_mode { - BOOT_MODE_MMC = 4, - BOOT_MODE_SERIAL = 20, - /* Boot based on Operating Mode pin settings */ - BOOT_MODE_OM = 32, - BOOT_MODE_USB, /* Boot using USB download */ -}; - - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); - typedef u32 (*usb_copy_func_t)(void); +typedef u32 (*usb_copy_func_t)(void); /* * Set/clear program flow prediction and return the previous state. @@ -48,6 +44,119 @@ static int config_branch_prediction(int set_cr_z) return cr & CR_Z; } +static void spi_rx_tx(struct exynos_spi *regs, int todo, + void *dinp, void const *doutp, int i) +{ + uint *rxp = (uint *)(dinp + (i * (32 * 1024))); + int rx_lvl, tx_lvl; + uint out_bytes, in_bytes; + + out_bytes = todo; + in_bytes = todo; + setbits_le32(&regs->ch_cfg, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt); + + while (in_bytes) { + uint32_t spi_sts; + int temp; + + spi_sts = readl(&regs->spi_sts); + rx_lvl = ((spi_sts >> 15) & 0x7f); + tx_lvl = ((spi_sts >> 6) & 0x7f); + while (tx_lvl < 32 && out_bytes) { + temp = 0xffffffff; + writel(temp, &regs->tx_data); + out_bytes -= 4; + tx_lvl += 4; + } + while (rx_lvl >= 4 && in_bytes) { + temp = readl(&regs->rx_data); + if (rxp) + *rxp++ = temp; + in_bytes -= 4; + rx_lvl -= 4; + } + } +} + +/* +* Copy uboot from spi flash to RAM +* +* @parma uboot_size size of u-boot to copy +* @param uboot_addr address in u-boot to copy +*/ +static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) +{ + int upto, todo; + int i, timeout = 100; + struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE; + + set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* set the spi1 GPIO */ + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + + /* set pktcnt and enable it */ + writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt); + /* set FB_CLK_SEL */ + writel(SPI_FB_DELAY_180, &regs->fb_clk); + /* set CH_WIDTH and BUS_WIDTH as word */ + setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + + /* clear rx and tx channel if set priveously */ + clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + + setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN | + SPI_RX_BYTE_SWAP | + SPI_RX_HWORD_SWAP); + + /* do a soft reset */ + setbits_le32(&regs->ch_cfg, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + + /* now set rx and tx channel ON */ + setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + + /* Send read instruction (0x3h) followed by a 24 bit addr */ + writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data); + + /* waiting for TX done */ + while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) { + if (!timeout) { + debug("SPI TIMEOUT\n"); + break; + } + timeout--; + } + + for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { + todo = min(uboot_size - upto, (1 << 15)); + spi_rx_tx(regs, todo, (void *)(uboot_addr), + (void *)(SPI_FLASH_UBOOT_POS), i); + } + + setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + + /* + * Let put controller mode to BYTE as + * SPI driver does not support WORD mode yet + */ + clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + writel(0, &regs->swap_cfg); + + /* + * Flush spi tx, rx fifos and reset the SPI controller + * and clear rx/tx channel + */ + clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); +} + /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -55,13 +164,13 @@ static int config_branch_prediction(int set_cr_z) */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; usb_copy_func_t usb_copy; int is_cr_z_set; unsigned int sec_boot_check; enum boot_mode bootmode = BOOT_MODE_OM; u32 (*copy_bl2)(u32, u32, u32); + struct spl_machine_param *param = spl_get_machine_params(); /* Read iRAM location to check for secondary USB boot mode */ sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); @@ -73,9 +182,8 @@ void copy_uboot_to_ram(void) switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; - spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, - CONFIG_SYS_TEXT_BASE); + /* Customised function to copy u-boot from SF */ + exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index d78b892..c759ad2 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -152,6 +152,8 @@ /* MMC SPL */ #define CONFIG_SPL +#define CONFIG_SPL_GPIO_SUPPORT + #define COPY_BL2_FNPTR_ADDR 0x02020030 /* specific .lds file */ @@ -306,6 +308,7 @@ #define CONFIG_ENV_SPI_MODE SPI_MODE_0 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE #define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_ENV_SPI_BASE 0x12D30000 #define CONFIG_ENV_SPI_MAX_HZ 50000000 #endif diff --git a/spl/Makefile b/spl/Makefile index 8b655c4..974cc06 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -102,6 +102,10 @@ ifneq ($(CONFIG_MX23)$(CONFIG_MX35),) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif +ifneq ($(CONFIG_EXYNOS4)$(CONFIG_EXYNOS5),) +LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o +endif + # Add GCC lib ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o -- 1.7.4.4

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[U-Boot] [PATCH] powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
by Prabhakar Kushwaha 06 Jun '13

06 Jun '13

init_tlbs() initialize all the TLB entries required for the system. So disable DEBUG TLB entry before TLB entries initialization. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index f4403c2..3ab7748 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -180,5 +180,9 @@ void cpu_init_early_f(void) invalidate_tlb(1); +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_SPL_BUILD) + disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); +#endif + init_tlbs(); } -- 1.7.9.5

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[U-Boot] Maintain U-Boot splash until application is loaded
by Otavio Salvador 06 Jun '13

06 Jun '13

Hello, I am working in a product and we'd like to keep the U-Boot splash until the application has been loaded so we have a graceful initialization. This project uses MX23 (so mxs SoC family). I tried to check the U-Boot mailing list archive for it but I couldn't find anything useful. I also did look at kernel source and it seems CONFIG_FB_PRE_INIT_FB is available for only *one* board. Could someone advice me how to do that? Regards, -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://projetos.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750

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