June 2013 - U-Boot

[U-Boot] [PATCH 00/11] arm: add Faraday A36x SoC platform support
by Kuo-Jung Su 07 Apr '14

07 Apr '14

From: Kuo-Jung Su <dantesu(a)faraday-tech.com> These patches introduce Faraday A36x SoC platform support. Here are some public documents for your reference. http://www.faraday-tech.com/html/documentation/index.html There is also a A369 QEMU emulator available at my github account: https://github.com/dantesu1218/qemu.git Here is quick start for QEMU: 1. Download the QEMU source tree $ git clone -b qemu-1.3.0 https://github.com/dantesu1218/qemu.git 2. Build & Install the QEMU: $ ./configure --target-list=arm-softmmu $ make $ make install 3. Launch u-boot with QEMU: $ qemu-system-arm -M a369 -m 512M -nographic -kernel ~/u-boot-2012.10/u-boot Kuo-Jung Su (11): arm: add MMU/d-cache support for Faraday cores net/ftgmac100: add MMU/D-cache support net: add FTMAC110 10/100Mbps ethernet support usb-ehci: add Faraday USB 2.0 EHCI controller support usb-gadget: add FOTG210 USB gadget support i2c: add FTI2C010 I2C controller support spi: add FTSPI010 SPI controller support mtd/nand: add FTNANDC021 NAND flash controller support mtd/spi: add FTSPI020 SPI Flash controller support mmc: add an alternative FTSDC010 driver support arm: add Faraday A36x SoC platform support arch/arm/cpu/faraday/Makefile | 57 ++ arch/arm/cpu/faraday/a360/Makefile | 49 ++ arch/arm/cpu/faraday/a360/reset.c | 22 + arch/arm/cpu/faraday/a369/Makefile | 50 ++ arch/arm/cpu/faraday/a369/cmd_fa606.c | 74 +++ arch/arm/cpu/faraday/a369/reset.c | 22 + arch/arm/cpu/faraday/cmd_bootfa.c | 121 ++++ arch/arm/cpu/faraday/config.mk | 33 + arch/arm/cpu/faraday/cpu.c | 230 +++++++ arch/arm/cpu/faraday/ftpwmtmr010.c | 165 +++++ arch/arm/cpu/faraday/fttmr010.c | 155 +++++ arch/arm/cpu/faraday/fwimage.h | 38 ++ arch/arm/cpu/faraday/fwimage2.h | 70 +++ arch/arm/cpu/faraday/interrupts.c | 169 ++++++ arch/arm/cpu/faraday/start.S | 535 +++++++++++++++++ arch/arm/cpu/u-boot.lds | 11 + arch/arm/include/asm/arch-a360/hardware.h | 80 +++ arch/arm/include/asm/arch-a369/hardware.h | 106 ++++ arch/arm/include/asm/dma-mapping.h | 55 +- arch/arm/include/asm/global_data.h | 4 + arch/arm/include/asm/io.h | 75 +++ arch/arm/include/asm/mach-types.h | 1 + arch/arm/lib/cache-cp15.c | 44 ++ board/faraday/a360evb/Makefile | 49 ++ board/faraday/a360evb/board.c | 65 ++ board/faraday/a360evb/clk.c | 48 ++ board/faraday/a360evb/config.mk | 33 + board/faraday/a360evb/lowlevel_init.S | 33 + board/faraday/a369evb/Makefile | 49 ++ board/faraday/a369evb/board.c | 182 ++++++ board/faraday/a369evb/clk.c | 80 +++ board/faraday/a369evb/config.mk | 33 + board/faraday/a369evb/lowlevel_init.S | 133 +++++ boards.cfg | 3 + common/cmd_boot.c | 4 + common/usb_hub.c | 5 + drivers/i2c/Makefile | 1 + drivers/i2c/fti2c010.c | 360 +++++++++++ drivers/i2c/fti2c010.h | 68 +++ drivers/mmc/Makefile | 1 + drivers/mmc/ftsdc010_mci.c | 362 +++++++++++ drivers/mmc/ftsdc010_mci.h | 91 +++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/ftnandc021.c | 550 +++++++++++++++++ drivers/mtd/nand/ftnandc021.h | 165 +++++ drivers/mtd/spi/Makefile | 4 + drivers/mtd/spi/ftspi020.c | 589 ++++++++++++++++++ drivers/mtd/spi/ftspi020.h | 118 ++++ drivers/mtd/spi/winbond.c | 17 +- drivers/net/Makefile | 1 + drivers/net/ftgmac100.c | 83 ++- drivers/net/ftmac110.c | 484 +++++++++++++++ drivers/net/ftmac110.h | 131 ++++ drivers/spi/Makefile | 1 + drivers/spi/ftssp010_spi.c | 333 +++++++++++ drivers/spi/ftssp010_spi.h | 85 +++ drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/fotg210.c | 926 +++++++++++++++++++++++++++++ drivers/usb/gadget/fotg210.h | 99 +++ drivers/usb/gadget/gadget_chips.h | 8 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-faraday.c | 157 +++++ drivers/usb/host/ehci-hcd.c | 11 + drivers/usb/host/ehci.h | 5 + include/common.h | 13 + include/configs/a360.h | 180 ++++++ include/configs/a369.h | 40 ++ include/configs/a369_defaults.h | 285 +++++++++ include/configs/a369_fa606te.h | 32 + include/faraday/fttmr010.h | 51 +- include/faraday/ftwdt010_wdt.h | 8 + 71 files changed, 8110 insertions(+), 35 deletions(-) create mode 100644 arch/arm/cpu/faraday/Makefile create mode 100644 arch/arm/cpu/faraday/a360/Makefile create mode 100644 arch/arm/cpu/faraday/a360/reset.c create mode 100644 arch/arm/cpu/faraday/a369/Makefile create mode 100644 arch/arm/cpu/faraday/a369/cmd_fa606.c create mode 100644 arch/arm/cpu/faraday/a369/reset.c create mode 100644 arch/arm/cpu/faraday/cmd_bootfa.c create mode 100644 arch/arm/cpu/faraday/config.mk create mode 100644 arch/arm/cpu/faraday/cpu.c create mode 100644 arch/arm/cpu/faraday/ftpwmtmr010.c create mode 100644 arch/arm/cpu/faraday/fttmr010.c create mode 100644 arch/arm/cpu/faraday/fwimage.h create mode 100644 arch/arm/cpu/faraday/fwimage2.h create mode 100644 arch/arm/cpu/faraday/interrupts.c create mode 100644 arch/arm/cpu/faraday/start.S create mode 100644 arch/arm/include/asm/arch-a360/hardware.h create mode 100644 arch/arm/include/asm/arch-a369/hardware.h create mode 100644 board/faraday/a360evb/Makefile create mode 100644 board/faraday/a360evb/board.c create mode 100644 board/faraday/a360evb/clk.c create mode 100644 board/faraday/a360evb/config.mk create mode 100644 board/faraday/a360evb/lowlevel_init.S create mode 100644 board/faraday/a369evb/Makefile create mode 100644 board/faraday/a369evb/board.c create mode 100644 board/faraday/a369evb/clk.c create mode 100644 board/faraday/a369evb/config.mk create mode 100644 board/faraday/a369evb/lowlevel_init.S create mode 100644 drivers/i2c/fti2c010.c create mode 100644 drivers/i2c/fti2c010.h create mode 100644 drivers/mmc/ftsdc010_mci.c create mode 100644 drivers/mmc/ftsdc010_mci.h create mode 100644 drivers/mtd/nand/ftnandc021.c create mode 100644 drivers/mtd/nand/ftnandc021.h create mode 100644 drivers/mtd/spi/ftspi020.c create mode 100644 drivers/mtd/spi/ftspi020.h create mode 100644 drivers/net/ftmac110.c create mode 100644 drivers/net/ftmac110.h create mode 100644 drivers/spi/ftssp010_spi.c create mode 100644 drivers/spi/ftssp010_spi.h create mode 100644 drivers/usb/gadget/fotg210.c create mode 100644 drivers/usb/gadget/fotg210.h create mode 100644 drivers/usb/host/ehci-faraday.c create mode 100644 include/configs/a360.h create mode 100644 include/configs/a369.h create mode 100644 include/configs/a369_defaults.h create mode 100644 include/configs/a369_fa606te.h -- 1.7.9.5

12 310

[U-Boot] [PATCH 00/10] Add Marvell Dove and SolidRun CuBox
by Sebastian Hesselbarth 04 Mar '14

04 Mar '14

This patch set add support for the Marvell Dove 88AP510 SoC and the SolidRun CuBox board based on that SoC. The patch set is divided into the four following sections: (1) Patches 1-5: Add support for the Dove SoC and related drivers. Where possible drivers from Marvell Kirkwood are reused (mvsata, mvgbe), or forked to allow more generic usage (SPI, GPIO). The SDHCI driver is different and a new driver is added for it. The forked drivers can also be reused on Kirkwood but that would have required patching existing boards. (2) Patches 6-8: Allow mvgbe to use the phylib API, add support for 88E1310 PHY and allow Dove to use the driver. (3) Patch 9 Add the SolidRun CuBox as the first board based on Marvell Dove SoC. (4) Patch 10 Add support for different UART boot mode found on Dove. Sebastian Hesselbarth (10): ARM: dove: add support for Marvell Dove SoC GPIO: add gpio driver for Orion SoCs MMC: sdhci: Add support for dove sdhci SPI: Add Orion SPI driver block: mvsata: add dove include NET: phy: add 88E1310 PHY initialization NET: mvgbe: add phylib support NET: mvgbe: add support for Dove Boards: Add support for SolidRun CuBox tools: Add support for Dove to kwboot arch/arm/cpu/armv7/dove/Makefile | 49 +++++ arch/arm/cpu/armv7/dove/cpu.c | 266 ++++++++++++++++++++++++++ arch/arm/cpu/armv7/dove/dram.c | 116 +++++++++++ arch/arm/cpu/armv7/dove/lowlevel_init.S | 83 ++++++++ arch/arm/cpu/armv7/dove/mpp.c | 319 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/dove/timer.c | 176 +++++++++++++++++ arch/arm/cpu/armv7/dove/usb.c | 101 ++++++++++ arch/arm/include/asm/arch-dove/config.h | 153 +++++++++++++++ arch/arm/include/asm/arch-dove/cpu.h | 204 ++++++++++++++++++++ arch/arm/include/asm/arch-dove/dove.h | 93 +++++++++ arch/arm/include/asm/arch-dove/gpio.h | 35 ++++ arch/arm/include/asm/arch-dove/mpp.h | 283 +++++++++++++++++++++++++++ board/solidrun/cubox/Makefile | 45 +++++ board/solidrun/cubox/cubox.c | 141 ++++++++++++++ board/solidrun/cubox/kwbimage.cfg | 76 ++++++++ boards.cfg | 1 + drivers/block/mvsata_ide.c | 2 + drivers/gpio/Makefile | 1 + drivers/gpio/orion_gpio.c | 167 ++++++++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/dove_sdhci.c | 101 ++++++++++ drivers/net/mvgbe.c | 70 ++++++- drivers/net/mvgbe.h | 7 + drivers/net/phy/marvell.c | 48 +++++ drivers/spi/Makefile | 1 + drivers/spi/orion_spi.c | 217 +++++++++++++++++++++ include/configs/cubox.h | 175 +++++++++++++++++ include/orion_gpio.h | 64 +++++++ tools/Makefile | 2 + tools/kwboot.c | 44 ++++- 30 files changed, 3033 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/armv7/dove/Makefile create mode 100644 arch/arm/cpu/armv7/dove/cpu.c create mode 100644 arch/arm/cpu/armv7/dove/dram.c create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/dove/mpp.c create mode 100644 arch/arm/cpu/armv7/dove/timer.c create mode 100644 arch/arm/cpu/armv7/dove/usb.c create mode 100644 arch/arm/include/asm/arch-dove/config.h create mode 100644 arch/arm/include/asm/arch-dove/cpu.h create mode 100644 arch/arm/include/asm/arch-dove/dove.h create mode 100644 arch/arm/include/asm/arch-dove/gpio.h create mode 100644 arch/arm/include/asm/arch-dove/mpp.h create mode 100644 board/solidrun/cubox/Makefile create mode 100644 board/solidrun/cubox/cubox.c create mode 100644 board/solidrun/cubox/kwbimage.cfg create mode 100644 drivers/gpio/orion_gpio.c create mode 100644 drivers/mmc/dove_sdhci.c create mode 100644 drivers/spi/orion_spi.c create mode 100644 include/configs/cubox.h create mode 100644 include/orion_gpio.h --- Cc: u-boot(a)lists.denx.de Cc: Sebastian Hesselbarth <sebastian.hesselbarth(a)gmail.com> Cc: Rabeeh Khoury <rabeeh(a)solid-run.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Prafulla Wadaskar <prafulla(a)marvell.com> Cc: Andy Fleming <afleming(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Cc: Daniel Stodden <daniel.stodden(a)gmail.com> Cc: Dieter Kiermaier <dk-arm-linux(a)gmx.de> -- 1.7.10.4

14 123

[U-Boot] [PATCH 1/1] TPM: STMicroelectronics u-boot driver I2C
by Mathias leblanc 17 Feb '14

17 Feb '14

From: Mathias Leblanc <mathias.leblanc(a)st.com> * STMicroelectronics version 1.2.0, Copyright (C) 2013 * This is free software, and you are welcome to redistribute it. This is the u-boot driver for TPM chip from ST Microelectronics. If you have a TPM security chip from STMicroelectronics working with an I2C, read the README file and add the correct defines regarding the tpm in the configuration file of your board. This file is located in include/configs/your_board.h The tpm command will be accessible from within uboot terminal. Signed-off-by: Mathias Leblanc <mathias.leblanc(a)st.com> --- README | 14 +- common/cmd_tpm.c | 122 ++++++++ drivers/tpm/Makefile | 1 + drivers/tpm/slb9635_i2c/tpm.c | 20 ++ drivers/tpm/slb9635_i2c/tpm.h | 1 + drivers/tpm/tis_i2c.c | 37 +++ drivers/tpm/tpm_i2c_st.c | 599 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 8 + include/tpm.h | 18 ++ 9 files changed, 819 insertions(+), 1 deletion(-) create mode 100644 drivers/tpm/tpm_i2c_st.c diff --git a/README b/README index 0d37d56..a72b570 100644 --- a/README +++ b/README @@ -1208,7 +1208,7 @@ The following options need to be configured: If this option is set, the driver enables cache flush. - TPM Support: - CONFIG_GENERIC_LPC_TPM + CONFIG_TPM Support for generic parallel port TPM devices. Only one device per system is supported at this time. @@ -1217,6 +1217,18 @@ The following options need to be configured: to. Contemporary x86 systems usually map it at 0xfed40000. + CONFIG_ST_TPM_I2C + Define to compile the ST TPM I2C DRIVER. + + CONFIG_TPM_I2C_BUS + Define the bus number of the board. + + CONFIG_TPM_I2C_ADDR + Define the address of the TPM. + + CONFIG_CMD_TPM + Define to use some TPM u-boot commands. + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define diff --git a/common/cmd_tpm.c b/common/cmd_tpm.c index 46fae18..fba1fe7 100644 --- a/common/cmd_tpm.c +++ b/common/cmd_tpm.c @@ -27,6 +27,14 @@ #include <asm/unaligned.h> #include <linux/string.h> +#define MAX_TRANSACTION_SIZE 30 +#define CHECK(exp) do { \ + int _rv = exp; \ + if (_rv) { \ + printf("CHECK: %s %d %x\n", #exp, __LINE__, _rv);\ + } \ + } while (0) + /** * Print a byte string in hexdecimal format, 16-bytes per line. * @@ -546,6 +554,118 @@ static int do_tpm_nv_write(cmd_tbl_t *cmdtp, int flag, return convert_return_code(err); } +static int do_tpm_hash(cmd_tbl_t *cmdtp, int flag, int argc, +char * const argv[]) +{ + u8 tpm_buffer[MAX_TRANSACTION_SIZE]; + u32 write_size, read_size; + char *p; + int rv = -1; + argc -= 1; + argv += 1; + uint8_t response[1024]; + size_t rlength = MAX_TRANSACTION_SIZE; + + u8 startup[] = { + 0x00, 0xc1, + 0x00, 0x00, 0x00, 0x0c, + 0x00, 0x00, 0x00, 0x99, + 0x00, 0x01 + }; + + u8 selftestfull[] = { + 0x00, 0xc1, + 0x00, 0x00, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x50 + }; + + u8 readpcr17[] = { + 0x00, 0xc1, + 0x00, 0x00, 0x00, 0x0e, + 0x00, 0x00, 0x00, 0x15, + 0x00, 0x00, 0x00, 0x11 + }; + + for (write_size = 0; write_size < argc; write_size++) { + u32 datum = kstrtoul(argv[write_size], &p, 0); + if (*p || (datum > 0xff)) { + printf("\n%s: bad data value\n\n", argv[write_size]); + cmd_usage(cmdtp); + return rv; + } + tpm_buffer[write_size] = (u8)datum; + } + + if (tis_init()) { + puts("tis_init() failed!\n"); + return -1; + } + + if (tis_open()) { + puts("tis_open() failed!\n"); + return -1; + } + + rv = tis_sendrecv(startup, sizeof(startup), response, &rlength); + if (rv) { + printf("tpm test startup failed\n"); + CHECK(tis_close()); + } + + rv = tis_sendrecv(selftestfull, sizeof(selftestfull), response, + &rlength); + if (rv) { + printf("tpm test selftestfull failed\n"); + CHECK(tis_close()); + } + + if (! + tis_sendrecv(readpcr17, sizeof(readpcr17), response, &read_size)) { + int i; + puts("TPM Read PCR 17:\n"); + for (i = 10; i < read_size; i++) + printf(" %2.2x", response[i]); + puts("\n"); + rv = 0; + } else { + printf("tpm test readpcr17 failed\n"); + CHECK(tis_close()); + } + + read_size = sizeof(tpm_buffer); + if (! + tis_sendrecv_hash(tpm_buffer, write_size, tpm_buffer, &read_size)) { + int i; + puts("Got TPM Hash response:\n"); + for (i = 0; i < read_size; i++) + printf(" %2.2x", tpm_buffer[i]); + puts("\n"); + rv = 0; + } else { + puts("tpm hash command failed\n"); + } + + if (! + tis_sendrecv(readpcr17, sizeof(readpcr17), response, &read_size)) { + int i; + puts("TPM Read PCR 17 after hash:\n"); + for (i = 10; i < read_size; i++) + printf(" %2.2x", response[i]); + puts("\n"); + rv = 0; + } else { + printf("tpm test readpcr17 failed\n"); + CHECK(tis_close()); + } + + if (tis_close()) { + puts("tis_close() failed!\n"); + rv = -1; + } + + return rv; +} + #define MAKE_TPM_CMD_ENTRY(cmd) \ U_BOOT_CMD_MKENT(cmd, 0, 1, do_tpm_ ## cmd, "", "") @@ -590,6 +710,8 @@ static cmd_tbl_t tpm_commands[] = { do_tpm_nv_read, "", ""), U_BOOT_CMD_MKENT(nv_write, 0, 1, do_tpm_nv_write, "", ""), + U_BOOT_CMD_MKENT(hash, 0, 1, + do_tpm_hash, "", ""), }; static int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index e8c159c..cbececf 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -28,6 +28,7 @@ $(shell mkdir -p $(obj)slb9635_i2c) COBJS-$(CONFIG_GENERIC_LPC_TPM) = generic_lpc_tpm.o COBJS-$(CONFIG_INFINEON_TPM_I2C) += tis_i2c.o slb9635_i2c/tpm.o COBJS-$(CONFIG_INFINEON_TPM_I2C) += slb9635_i2c/tpm_tis_i2c.o +COBJS-$(CONFIG_ST_TPM_I2C) = tis_i2c.o tpm_i2c_st.o slb9635_i2c/tpm.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/tpm/slb9635_i2c/tpm.c b/drivers/tpm/slb9635_i2c/tpm.c index 496c48e..c92bd06 100644 --- a/drivers/tpm/slb9635_i2c/tpm.c +++ b/drivers/tpm/slb9635_i2c/tpm.c @@ -444,6 +444,26 @@ int tpm_open(uint32_t dev_addr) return rc; } +ssize_t tpm_transmit_hash(const unsigned char *buf, size_t bufsiz) +{ + ssize_t rc; + + struct tpm_chip *chip = &g_chip; + + rc = chip->vendor.send_hash(chip, (u8 *)buf, bufsiz); + if (rc < 0) { + dev_err(chip->dev, "tpm_transmit: tpm_send: error %zd\n", rc); + goto out; + } + + dbg_printf("out_recv: reading response...\n"); + rc = chip->vendor.recv(chip, (u8 *)buf, TPM_BUFSIZE); + if (rc < 0) + dev_err(chip->dev, "tpm_transmit: tpm_recv: error %zd\n", rc); +out: + return rc; +} + void tpm_close(void) { if (g_chip.is_open) { diff --git a/drivers/tpm/slb9635_i2c/tpm.h b/drivers/tpm/slb9635_i2c/tpm.h index 9ddee86..88e0c07 100644 --- a/drivers/tpm/slb9635_i2c/tpm.h +++ b/drivers/tpm/slb9635_i2c/tpm.h @@ -64,6 +64,7 @@ struct tpm_vendor_specific { int irq; int (*recv) (struct tpm_chip *, u8 *, size_t); int (*send) (struct tpm_chip *, u8 *, size_t); + int (*send_hash) (struct tpm_chip *, u8 *, size_t); void (*cancel) (struct tpm_chip *); u8(*status) (struct tpm_chip *); int locality; diff --git a/drivers/tpm/tis_i2c.c b/drivers/tpm/tis_i2c.c index e818fba..36ae544 100644 --- a/drivers/tpm/tis_i2c.c +++ b/drivers/tpm/tis_i2c.c @@ -82,8 +82,13 @@ static int tpm_decode_config(struct tpm *dev) dev->i2c_bus = i2c_bus; dev->slave_addr = fdtdec_get_addr(blob, node, "reg"); #else + #ifdef CONFIG_INFINEON_TPM_I2C_BUS dev->i2c_bus = CONFIG_INFINEON_TPM_I2C_BUS; dev->slave_addr = CONFIG_INFINEON_TPM_I2C_ADDR; + #else + dev->i2c_bus = CONFIG_TPM_I2C_BUS; + dev->slave_addr = CONFIG_TPM_I2C_ADDR; + #endif #endif return 0; } @@ -179,3 +184,35 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, return 0; } + +int tis_sendrecv_hash(const uint8_t *sendbuf, size_t sbuf_size, + uint8_t *recvbuf, size_t *rbuf_len) +{ + int len; + uint8_t buf[TPM_BUFSIZE]; + + if (!tpm.inited) + return -1; + + if (sizeof(buf) < sbuf_size) + return -1; + + memcpy(buf, sendbuf, sbuf_size); + + if (tpm_select()) + return -1; + + len = tpm_transmit_hash(buf, sbuf_size); + + tpm_deselect(); + + if (len < 10) { + *rbuf_len = 0; + return -1; + } + + memcpy(recvbuf, buf, len); + *rbuf_len = len; + + return 0; +} diff --git a/drivers/tpm/tpm_i2c_st.c b/drivers/tpm/tpm_i2c_st.c new file mode 100644 index 0000000..16753f8 --- /dev/null +++ b/drivers/tpm/tpm_i2c_st.c @@ -0,0 +1,599 @@ +/* + * STMicroelectronics TPM I2C UBOOT Linux driver for TPM ST33ZP24 + * Copyright (C) 2013 STMicroelectronics + * + * (c) Copyright 2013 Mathias Leblanc <mathias.leblanc(a)st.com> + * This file is released under the terms of GPL v2 and any later version + * See the file COPYING in the root directory of the source tree for details + * + * Description: + * Device driver for TCG/TCPA TPM (trusted platform module). + * Specifications at www.trustedcomputinggroup.org + * + * This device driver implements the TPM interface as defined in + * the TCG TPM Interface Spec version 1.2, revision 1.0 and the + * STMicroelectronics I2C Protocol Stack Specification version 1.2.0. + * + * It is based on the Linux I2C TPM driver from Peter Huewe, modified + * from the original tpm + * device drivers from Leendert van Dorn, Dave Safford, Reiner Sailer + * and Kyleen Hall. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * @Author: Mathias Leblanc tpmsupport(a)st.com + * + * @File: tpm_i2c_st.c + * + */ + +#include <common.h> +#include <i2c.h> +#include <linux/types.h> + +#include "slb9635_i2c/compatibility.h" +#include "slb9635_i2c/tpm.h" + +/* max. buffer size supported by our tpm */ +#ifdef TPM_BUFSIZE +#undef TPM_BUFSIZE +#endif + +#define MINOR_NUM_I2C 224 + +#define TPM_ACCESS (0x0) +#define TPM_STS (0x18) +#define TPM_HASH_END (0x20) +#define TPM_DATA_FIFO (0x24) +#define TPM_HASH_DATA (0x24) +#define TPM_HASH_START (0x28) +#define TPM_INTF_CAPABILITY (0x14) +#define TPM_INT_STATUS (0x10) +#define TPM_INT_ENABLE (0x08) + +#define TPM_DUMMY_BYTE 0xAA +#define TPM_WRITE_DIRECTION 0x80 +#define TPM_HEADER_SIZE 10 +#define TPM_BUFSIZE 2048 + +#define LOCALITY0 0 +#define LOCALITY4 4 + +struct st_tpm_hash { + int size; + u8 *data; +}; + +enum stm33zp24_access { + TPM_ACCESS_VALID = 0x80, + TPM_ACCESS_ACTIVE_LOCALITY = 0x20, + TPM_ACCESS_REQUEST_PENDING = 0x04, + TPM_ACCESS_REQUEST_USE = 0x02, +}; + +enum stm33zp24_status { + TPM_STS_VALID = 0x80, + TPM_STS_COMMAND_READY = 0x40, + TPM_STS_GO = 0x20, + TPM_STS_DATA_AVAIL = 0x10, + TPM_STS_DATA_EXPECT = 0x08, +}; + +enum stm33zp24_int_flags { + TPM_GLOBAL_INT_ENABLE = 0x80, + TPM_INTF_CMD_READY_INT = 0x080, + TPM_INTF_FIFO_AVALAIBLE_INT = 0x040, + TPM_INTF_WAKE_UP_READY_INT = 0x020, + TPM_INTF_LOC4SOFTRELEASE_INT = 0x008, + TPM_INTF_LOCALITY_CHANGE_INT = 0x004, + TPM_INTF_STS_VALID_INT = 0x002, + TPM_INTF_DATA_AVAIL_INT = 0x001, +}; + +enum tis_defaults { + TIS_SHORT_TIMEOUT = 750, /* ms */ + TIS_LONG_TIMEOUT = 2000, /* 2 sec */ +}; + +struct tpm_i2c_ST_dev { + uint addr; + u8 buf[TPM_BUFSIZE]; +}; + +static struct tpm_i2c_ST_dev tpm_dev = { + /* Note: replace with defined addr from board configuration */ + .addr = CONFIG_TPM_I2C_ADDR +}; + +/* + * write8_reg + * Send byte to the TIS register according to the ST33ZP24 I2C protocol. + * @param: tpm_register, the tpm tis register where the data should be written + * @param: tpm_data, the tpm_data to write inside the tpm_register + * @param: tpm_size, The length of the data + * @return: Returns zero in case of success else the negative error code. + */ +static int write8_reg(u8 addr, u8 tpm_register, + u8 *tpm_data, u16 tpm_size) +{ + u8 data; + data = tpm_register; + memcpy(&(tpm_dev.buf[0]), &data, sizeof(data)); + memcpy(&(tpm_dev.buf[0])+1, tpm_data, tpm_size); + + return i2c_write(addr, 0, 0, &tpm_dev.buf[0], + tpm_size + 1); + +} /* write8_reg() */ + +/* +* read8_reg +* Recv byte from the TIS register according to the ST33ZP24 I2C protocol. +* @param: tpm_register, the tpm tis register where the data should be read +* @param: tpm_data, the TPM response +* @param: tpm_size, tpm TPM response size to read. +* @return: Returns zero in case of success else the negative error code. +*/ +static int read8_reg(u8 addr, u8 tpm_register, +u8 *tpm_data, int tpm_size) +{ + u8 status = 0; + u8 data; + data = TPM_DUMMY_BYTE; + status = write8_reg(addr, tpm_register, &data, 1); + if (status == 0) + status = i2c_read(addr, 0, 0, tpm_data, tpm_size); +return status; +} /* read8_reg() */ + +/* + * I2C_WRITE_DATA + * Send byte to the TIS register according to the ST33ZP24 I2C protocol. + * @param: client, the chip description + * @param: tpm_register, the tpm tis register where the data should be written + * @param: tpm_data, the tpm_data to write inside the tpm_register + * @param: tpm_size, The length of the data + * @return: Returns zero in case of success else the negative error code. + */ +#define I2C_WRITE_DATA(client, tpm_register, tpm_data, tpm_size)\ + (write8_reg(client, tpm_register | \ + TPM_WRITE_DIRECTION, tpm_data, tpm_size)) + +/* + * I2C_READ_DATA + * Recv byte from the TIS register according to the ST33ZP24 I2C protocol. + * @param: tpm, the chip description + * @param: tpm_register, the tpm tis register where the data should be read + * @param: tpm_data, the TPM response + * @param: tpm_size, tpm TPM response size to read. + * @return: Returns zero in case of success else the negative error code. + */ +#define I2C_READ_DATA(client, tpm_register, tpm_data, tpm_size)\ + (read8_reg(client, tpm_register, tpm_data, tpm_size)) + +/* + * release_locality release the active locality + * @param: chip, the tpm chip description. + */ +static void release_locality(struct tpm_chip *chip) +{ + u8 data = TPM_ACCESS_ACTIVE_LOCALITY; + + I2C_WRITE_DATA(tpm_dev.addr, TPM_ACCESS, &data, 1); +} + +/* + * clear_interruption + * clear the TPM interrupt register. + * @param: tpm, the chip description + */ +static void clear_interruption(u8 addr) +{ + u8 interrupt; + I2C_READ_DATA(tpm_dev.addr, TPM_INT_STATUS, &interrupt, 1); + I2C_WRITE_DATA(tpm_dev.addr, TPM_INT_STATUS, &interrupt, 1); + I2C_READ_DATA(tpm_dev.addr, TPM_INT_STATUS, &interrupt, 1); +} /* clear_interruption() */ + +int wait_for_serirq_timeout(struct tpm_chip *chip, int condition, + unsigned long timeout) +{ + int status = 2; + + clear_interruption(tpm_dev.addr); + if (condition) + status = 1; + + return status; +} + +/* + * check_locality if the locality is active + * @param: chip, the tpm chip description + * @return: the active locality or -EACCESS. + */ +static int check_locality(struct tpm_chip *chip) +{ + u8 data; + u8 status; + status = I2C_READ_DATA(tpm_dev.addr, TPM_ACCESS, &data, 1); + + if ((status == 0) && (data & + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) + return chip->vendor.locality; + + return -EACCES; + +} /* check_locality() */ + +/* + * request_locality request the TPM locality + * @param: chip, the chip description + * @return: the active locality or EACCESS. + */ +static int request_locality(struct tpm_chip *chip) +{ + unsigned long start, stop; + long rc; + u8 data; + if (check_locality(chip) == chip->vendor.locality) + return chip->vendor.locality; + + data = TPM_ACCESS_REQUEST_USE; + rc = I2C_WRITE_DATA(tpm_dev.addr, TPM_ACCESS, &data, 1); + if (rc < 0) + goto end; + + if (chip->vendor.irq) { + rc = wait_for_serirq_timeout(chip, (check_locality + (chip) >= 0), + chip->vendor.timeout_a); + if (rc > 0) + return chip->vendor.locality; + } else{ + /* wait for locality activated */ + start = get_timer(0); + stop = chip->vendor.timeout_a; + do { + if (check_locality(chip) >= 0) + return chip->vendor.locality; + + msleep(TPM_TIMEOUT); + } while (get_timer(start) < stop); + } + rc = -EACCES; +end: + return rc; +} /* request_locality() */ + +/* + * tpm_stm_i2c_cancel, cancel is not implemented. + * @param: chip, tpm_chip description. + */ +static void tpm_stm_i2c_cancel(struct tpm_chip *chip) +{ + u8 data; + + data = TPM_STS_COMMAND_READY; + I2C_WRITE_DATA(tpm_dev.addr, TPM_STS, &data, 1); + if (chip->vendor.irq) + wait_for_serirq_timeout(chip, 1, chip->vendor.timeout_a); +} /* tpm_stm_i2c_cancel() */ + +/* + * tpm_stm_spi_status return the TPM_STS register + * @param: chip, the tpm chip description + * @return: the TPM_STS register value. + */ +static u8 tpm_stm_i2c_status(struct tpm_chip *chip) +{ + u8 data; + I2C_READ_DATA(tpm_dev.addr, TPM_STS, &data, 1); + return data; +} /* tpm_stm_i2c_status() */ + +/* + * get_burstcount return the burstcount address 0x19 0x1A + * @param: chip, the chip description + * return: the burstcount. + */ +static int get_burstcount(struct tpm_chip *chip) +{ + unsigned long start, stop; + int burstcnt, status; + u8 tpm_reg, temp; + + /* wait for burstcount */ + /* which timeout value, spec has 2 answers (c & d) */ + start = get_timer(0); + stop = chip->vendor.timeout_d; + do { + tpm_reg = TPM_STS + 1; + status = I2C_READ_DATA(tpm_dev.addr, tpm_reg, &temp, 1); + if (status < 0) + goto end; + + tpm_reg = tpm_reg + 1; + burstcnt = temp; + status = I2C_READ_DATA(tpm_dev.addr, tpm_reg, &temp, 1); + if (status < 0) + goto end; + + burstcnt |= temp << 8; + if (burstcnt) + return burstcnt; + + msleep(TPM_TIMEOUT); + } while (get_timer(start) < stop); + +end: + return -EBUSY; +} /* get_burstcount() */ + + +/* + * recv_data receive data + * @param: chip, the tpm chip description + * @param: buf, the buffer where the data are received + * @param: count, the number of data to receive + * @return: the number of bytes read from TPM FIFO. + */ +static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count) +{ + int size = 0, burstcnt, len; + + while (size < count) { + burstcnt = get_burstcount(chip); + len = count - size; + if ((len) > burstcnt) + len = burstcnt; + if ( + I2C_READ_DATA(tpm_dev.addr, TPM_DATA_FIFO, buf + size, len) == 0) + size += len; + else + break; + } + return size; +} /* recv_data() */ + +/* + * tpm_stm_i2c_recv received TPM response through the I2C bus. + * @param: chip, tpm_chip description. + * @param: buf, the buffer to store datas. + * @param: count, the number of bytes to send. + * @return: Returns zero in case of success else the negative error code. + */ +static int tpm_stm_i2c_recv(struct tpm_chip *chip, unsigned char *buf, + size_t count) +{ + int size = 0; + int expected; + + if (chip == NULL) + return -EBUSY; + + if (count < TPM_HEADER_SIZE) { + size = -EIO; + goto out; + } + + size = recv_data(chip, buf, TPM_HEADER_SIZE); + if (size < TPM_HEADER_SIZE) { + dev_err(chip->dev, "Unable to read header\n"); + goto out; + } + + + expected = get_unaligned_be32(buf + TPM_RSP_SIZE_BYTE); + if (expected > count) { + size = -EIO; + goto out; + } + + size += recv_data(chip, &buf[TPM_HEADER_SIZE], + expected - TPM_HEADER_SIZE); + if (size < expected) { + dev_err(chip->dev, "Unable to read remainder of result\n"); + size = -ETIME; + goto out; + } + +out: + chip->vendor.cancel(chip); + release_locality(chip); + return size; +} /* tpm_stm_i2c_recv() */ + +/* + * tpm_stm_i2c_send send TPM commands through the I2C bus. + * + * @param: chip, tpm_chip description. + * @param: buf, the buffer to send. + * @param: len, the number of bytes to send. + * @return: Returns zero in case of success else the negative error code. + */ +static int tpm_stm_i2c_send(struct tpm_chip *chip, u8 *buf, + size_t len) +{ + u32 ret = 0, + status, + burstcnt = 0, i, size; + u8 data; + + if (chip == NULL) + return -EBUSY; + if (len < TPM_HEADER_SIZE) + return -EBUSY; + + ret = request_locality(chip); + if (ret < 0) + return ret; + + status = tpm_stm_i2c_status(chip); + if ((status & TPM_STS_COMMAND_READY) == 0) + tpm_stm_i2c_cancel(chip); + + for (i = 0; i < len - 1;) { + burstcnt = get_burstcount(chip); + size = len - i - 1; + if ((size) > burstcnt) + size = burstcnt; + ret = I2C_WRITE_DATA(tpm_dev.addr, TPM_DATA_FIFO, buf, size); + if (ret < 0) + goto out_err; + + i += size; + } + + status = tpm_stm_i2c_status(chip); + if ((status & TPM_STS_DATA_EXPECT) == 0) { + ret = -EIO; + goto out_err; + } + + ret = I2C_WRITE_DATA(tpm_dev.addr, TPM_DATA_FIFO, buf + len - 1, 1); + if (ret < 0) + goto out_err; + + status = tpm_stm_i2c_status(chip); + if ((status & TPM_STS_DATA_EXPECT) != 0) { + ret = -EIO; + goto out_err; + } + + data = TPM_STS_GO; + I2C_WRITE_DATA(tpm_dev.addr, TPM_STS, &data, 1); + + return len; +out_err: + tpm_stm_i2c_cancel(chip); + release_locality(chip); + return ret; +} /* tpm_stm_i2c_send() */ + +/* + * tpm_stm_i2c_send_hash send TPM locality 4 hash datas through the I2C bus + * to update the PCR[17]. + * @param: chip, the tpm_chip description. + * @param: buf, the data buffer to send. + * @param: len, the number of bytes to send. + * @return: Returns zero in case of success else the negative error code. + */ +static int tpm_stm_i2c_send_hash(struct tpm_chip *chip, unsigned char *buf, + size_t len) +{ + u32 ret = 0; + u8 data; + + if (chip == NULL) + return -EBUSY; + + release_locality(chip); + + tpm_dev.addr = 0x1B; + chip->vendor.locality = LOCALITY4; + + data = TPM_DUMMY_BYTE; + ret = I2C_WRITE_DATA(tpm_dev.addr, TPM_HASH_START, &data, 1); + if (ret < 0) + goto end; + ret = I2C_WRITE_DATA(tpm_dev.addr, TPM_DATA_FIFO, buf, len); + if (ret < 0) + goto end; + +end: + I2C_WRITE_DATA(tpm_dev.addr, TPM_HASH_END, &data, 1); + release_locality(chip); + chip->vendor.locality = LOCALITY0; + tpm_dev.addr = 0x13; + ret = request_locality(chip); + return ret; +} /* tpm_stm_i2c_send_hash */ + +static struct tpm_vendor_specific st_i2c_tpm = { + .send = tpm_stm_i2c_send, + .send_hash = tpm_stm_i2c_send_hash, + .recv = tpm_stm_i2c_recv, + .cancel = tpm_stm_i2c_cancel, + .status = tpm_stm_i2c_status, + .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID, + .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID, + .req_canceled = TPM_STS_COMMAND_READY, +}; + +/* + * tpm_vendor_init initialize the TPM device + * @param: dev_addr, the i2c address of the tpm. + * @return: 0 in case of success. + * -1 in other case. + */ +int tpm_vendor_init(uint32_t dev_addr) +{ + u32 vendor; + uint old_addr; + int rc = 0; + struct tpm_chip *chip; + + old_addr = tpm_dev.addr; + if (dev_addr != 0) + tpm_dev.addr = dev_addr; + + chip = tpm_register_hardware(&st_i2c_tpm); + + if (chip < 0) { + rc = -ENODEV; + goto out_err; + } + + /* Default timeouts */ + chip->vendor.timeout_a = TIS_SHORT_TIMEOUT; + chip->vendor.timeout_b = TIS_LONG_TIMEOUT; + chip->vendor.timeout_c = TIS_SHORT_TIMEOUT; + chip->vendor.timeout_d = TIS_SHORT_TIMEOUT; + + chip->vendor.locality = LOCALITY0; + + if (request_locality(chip) != 0) { + rc = -ENODEV; + goto out_err; + } + + vendor = be32_to_cpu(vendor); + + + dev_info(dev, "1.2 TPM STMicroelectronics"); + /* + * A timeout query to TPM can be placed here. + * Standard timeout values are used so far + */ + + return 0; + +out_err: + tpm_dev.addr = old_addr; + return rc; +} /* tpm_vendor_init() */ + + + +void tpm_vendor_cleanup(struct tpm_chip *chip) +{ + release_locality(chip); +} /* tpm_vendor_cleanup() */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 48ce4c0..ef381f8 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -111,6 +111,14 @@ #define STATUS_LED_BOOT STATUS_LED_BIT #define STATUS_LED_GREEN STATUS_LED_BIT1 +/* TPM */ +#define CONFIG_CMD_TPM +#define CONFIG_TPM +#define CONFIG_ST_TPM_DEBUG +#define CONFIG_ST_TPM_I2C +#define CONFIG_TPM_I2C_BUS 1 +#define CONFIG_TPM_I2C_ADDR 0x13 + /* Enable Multi Bus support for I2C */ #define CONFIG_I2C_MULTI_BUS 1 diff --git a/include/tpm.h b/include/tpm.h index 7219b73..36ba0bb 100644 --- a/include/tpm.h +++ b/include/tpm.h @@ -201,4 +201,22 @@ uint32_t tpm_physical_set_deactivated(uint8_t state); uint32_t tpm_get_capability(uint32_t cap_area, uint32_t sub_cap, void *cap, size_t count); +/* + * tis_sendrecv_hash() + * + * Send the requested data to the TPM for hash in LOC 4 + * and then try to get its response + * + * @sendbuf - buffer of the data to hash + * @send_size size of the data to send + * @recvbuf - memory to save the response to + * @recv_len - pointer to the size of the response buffer + * + * Returns 0 on success (and places the number of response bytes at recv_len) + * or -1 on failure. + */ +int tis_sendrecv_hash(const uint8_t *sendbuf, size_t send_size, + uint8_t *recvbuf, + size_t *recv_len); + #endif /* __TPM_H */ -- 1.7.9.5

2 4

[U-Boot] [PATCH 2/2] ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALL
by Jassi Brar 24 Jan '14

24 Jan '14

The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh(a)linaro.org> --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 6 - arch/arm/include/asm/arch-omap4/sys_proto.h | 1 - arch/arm/include/asm/arch-omap5/sys_proto.h | 1 - board/ti/omap5_evm/evm.c | 11 - board/ti/omap5_evm/mux_data.h | 234 ------------------------ board/ti/panda/panda.c | 28 --- board/ti/panda/panda_mux_data.h | 186 ------------------- board/ti/sdp4430/sdp.c | 18 -- board/ti/sdp4430/sdp4430_mux_data.h | 197 -------------------- 9 files changed, 0 insertions(+), 682 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 459ebb5..077fc27 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -51,16 +51,10 @@ static void set_mux_conf_regs(void) set_muxconf_regs_essential(); break; case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: set_muxconf_regs_essential(); -#ifdef CONFIG_SYS_ENABLE_PADS_ALL - set_muxconf_regs_non_essential(); -#endif break; } } diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index d633573..90befa1 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -37,7 +37,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 74feb90..9a49393 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -38,7 +38,6 @@ void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); -void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c index c8dfdf8..4b61819 100644 --- a/board/ti/omap5_evm/evm.c +++ b/board/ti/omap5_evm/evm.c @@ -80,17 +80,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h index a82795d..c5af6cd 100644 --- a/board/ti/omap5_evm/mux_data.h +++ b/board/ti/omap5_evm/mux_data.h @@ -67,238 +67,4 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - - {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ - {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ - {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ - {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ - {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ - {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ - {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ - {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ - {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ - {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ - {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ - {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ - {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ - {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ - {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ - {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ - {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ - {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ - {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ - {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ - {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ - {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ - {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ - {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ - {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ - {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ - {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ - {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ - {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ - {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ - {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ - {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ - {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ - {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ - {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ - {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ - {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ - {HSI1_CADATA, (M6)}, /* GPIO3_71 */ - {UART1_TX, (M0)}, /* UART1_TX */ - {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ - {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ - {UART1_RTS, (M0)}, /* UART1_RTS */ - {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ - {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ - {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ - {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ - {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ - {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ - {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ - {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ - {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ - {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ - {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ - {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ - {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ - {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ - {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ - {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ - {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ - {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ - {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ - {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ - {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ - {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ - {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ - {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ - {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ - {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ - {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ - {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ - {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ - {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ - {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ - {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ - {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ - {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ - {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ - {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ - {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ - {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ - {RFBI_RE, (M4)}, /* KBD_COL4 */ - {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ - {RFBI_DATA8, (M4)}, /* KBD_COL3 */ - {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ - {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ - {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ - {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ - {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ - {RFBI_DATA14, (M4)}, /* KBD_COL7 */ - {RFBI_DATA15, (M4)}, /* KBD_COL6 */ - {GPIO6_182, (M6)}, /* GPIO6_182 */ - {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ - {GPIO6_184, (M4)}, /* KBD_COL2 */ - {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ - {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ - {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ - {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ - {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ - {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ - {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ - {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ - {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ - {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ - {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ - {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ - {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ - {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ - {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ - {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ - {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ - {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ - {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ - {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ - {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ - {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ - {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ - {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ - {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ - {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ - {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ - {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ - {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ - {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ - {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ - {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ - {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ - {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ - {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ - {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ - {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ - {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ - {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ - {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ - {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ - {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ - {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ - {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ - {CAM_STROBE, (M0)}, /* CAM_STROBE */ - {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ - {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ - {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ - {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ - {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ - {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ - {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ - {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ - {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ - {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ - {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ - {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ - {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ - {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ - {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ - {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ - {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ - {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ - {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ - {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ - {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ - {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ - {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ - {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ - {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ - {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ - {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ - {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ - {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ - {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ - {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ - {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ - {UART5_TX, (M0)}, /* UART5_TX */ - {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ - {UART5_RTS, (M0)}, /* UART5_RTS */ - {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ - {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ - {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ - {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ - {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ - {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ - {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ - {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ - {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ - {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ - {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ - {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ - {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ - {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ - {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ - {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ - {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ - {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ - {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - -/* - * This pad keeps C2C Module always enabled. - * Putting this in safe mode do not cause the issue. - * C2C driver could enable this mux setting if needed. - */ - {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ - {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ - {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ - {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ - {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ - {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ - {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ - {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ - {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ - {JTAG_TDO, (M0)}, /* JTAG_TDO */ - {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ - {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ - {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ - {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ - {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ - {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ - {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ - {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ - {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ - {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ - {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ - {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ - {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ - {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ - {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ - -}; - #endif /* _EVM4430_MUX_DATA_H */ diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index ee82771..25cbc7c 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -148,34 +148,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux(CONTROL_PADCONF_CORE, - core_padconf_array_non_essential_4430, - sizeof(core_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - else - do_set_mux(CONTROL_PADCONF_CORE, - core_padconf_array_non_essential_4460, - sizeof(core_padconf_array_non_essential_4460) / - sizeof(struct pad_conf_entry)); - - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) - do_set_mux(CONTROL_PADCONF_WKUP, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index 5939257..4300401 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -100,190 +100,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (M3)}, /* gpio_46 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ - {UART2_RTS, (M7)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ - {UART2_TX, (M7)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4430[] = { - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ -}; - -const struct pad_conf_entry core_padconf_array_non_essential_4460[] = { - {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ - {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ -}; - #endif /* _PANDA_MUX_DATA_H_ */ diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 982c771..4d31dac 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -87,24 +87,6 @@ void set_muxconf_regs_essential(void) sizeof(struct pad_conf_entry)); } -void set_muxconf_regs_non_essential(void) -{ - do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, - sizeof(core_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, - sizeof(wkup_padconf_array_non_essential) / - sizeof(struct pad_conf_entry)); - - if (omap_revision() < OMAP4460_ES1_0) { - do_set_mux(CONTROL_PADCONF_WKUP, - wkup_padconf_array_non_essential_4430, - sizeof(wkup_padconf_array_non_essential_4430) / - sizeof(struct pad_conf_entry)); - } -} - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 0760dad..76a9331 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -81,201 +81,4 @@ const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { }; -const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (M1)}, /* dsi1_te0 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ - {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ - {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ - {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ - {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ - {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ - {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ - -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ -}; - -const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { - {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ -}; - #endif /* _SDP4430_MUX_DATA_H */ -- 1.7.4.1

2 1

[U-Boot] [PATCH 1/2] ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL
by Jassi Brar 24 Jan '14

24 Jan '14

The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh(a)linaro.org> --- Hi, The commit f3f98bb0 seems to suggest we want to move these settings into the kernel, but perhaps we should also evaluate the option of making these inits fully board specific but in u-boot? Thanks. arch/arm/cpu/armv7/omap-common/clocks-common.c | 47 ------------- arch/arm/cpu/armv7/omap4/clocks.c | 84 ----------------------- arch/arm/cpu/armv7/omap5/clocks.c | 87 ------------------------ arch/arm/include/asm/arch-omap4/clocks.h | 1 - arch/arm/include/asm/arch-omap5/clocks.h | 1 - 5 files changed, 0 insertions(+), 220 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index b1fd277..fc14465 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -326,49 +326,6 @@ static void setup_dplls(void) #endif } -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL -static void setup_non_essential_dplls(void) -{ - u32 abe_ref_clk; - const struct dpll_params *params; - - /* IVA */ - clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, - CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); - - params = get_iva_dpll_params(); - do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); - - /* Configure ABE dpll */ - params = get_abe_dpll_params(); -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; -#else - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; - /* - * We need to enable some additional options to achieve - * 196.608MHz from 32768 Hz - */ - setbits_le32(&prcm->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| - CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| - CM_CLKMODE_DPLL_LPMODE_EN_MASK| - CM_CLKMODE_DPLL_REGM4XEN_MASK); - /* Spend 4 REFCLK cycles at each stage */ - clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_RAMP_RATE_MASK, - 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); -#endif - - /* Select the right reference clk */ - clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, - CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, - abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); - /* Lock the dpll */ - do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); -} -#endif - void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv) { u32 step; @@ -584,10 +541,6 @@ void prcm_init(void) enable_basic_clocks(); scale_vcores(); setup_dplls(); -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL - setup_non_essential_dplls(); - enable_non_essential_clocks(); -#endif break; default: break; diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 5bd0a88..b3fc652 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -431,87 +431,3 @@ void enable_basic_uboot_clocks(void) clk_modules_explicit_en_essential, 1); } - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, - &prcm->cm_l4per_mcbsp4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index eecfbad..6c5441f 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -405,90 +405,3 @@ void enable_basic_uboot_clocks(void) clk_modules_explicit_en_essential, 1); } - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_mpu_m3_mpu_m3_clkctrl, - &prcm->cm_ivahd_ivahd_clkctrl, - &prcm->cm_ivahd_sl2_clkctrl, - &prcm->cm_dsp_dsp_clkctrl, - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index be20fc0..eff7d02 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -753,7 +753,6 @@ void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); void do_enable_clocks(u32 *const *clk_domains, u32 *const *clk_modules_hw_auto, u32 *const *clk_modules_explicit_en, diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 5f1a7aa..4f387a7 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -726,7 +726,6 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv); void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); -void enable_non_essential_clocks(void); void enable_basic_uboot_clocks(void); void do_enable_clocks(u32 *const *clk_domains, u32 *const *clk_modules_hw_auto, -- 1.7.4.1

3 2

[U-Boot] U-boot for 64bit ARMv8
by Richard Schmitt 24 Jan '14

24 Jan '14

Is anyone considering porting/supporting uboot for ARMv8. Our initial investigation of boot loader support for ARMv8 indicates that the only boot loader currently being targeted is UEFI. The decisions we need to make are: - Do we move to UEFI on ARM? - Can we leverage someone else's enablement of ARMv8? - Do we provide our own enablement of ARMv8? Any opinions? Rich

5 6

[U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
by Armando Visconti 08 Jan '14

08 Jan '14

This patch adds the support for the ARM PL022 SPI controller for the standard variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO. Signed-off-by: Armando Visconti <armando.visconti(a)st.com> Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> Acked-by: Stefan Roese <sr(a)denx.de> --- v5->v6 1. Make use of spi_alloc_slave() macro. 2. Changed the identation on 'if statement' as requested by Jagan. drivers/spi/Makefile | 1 + drivers/spi/pl022_spi.c | 308 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 309 insertions(+) create mode 100644 drivers/spi/pl022_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d08609e..b6443b1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o +COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c new file mode 100644 index 0000000..5b47413 --- /dev/null +++ b/drivers/spi/pl022_spi.c @@ -0,0 +1,308 @@ +/* + * (C) Copyright 2012 + * Armando Visconti, ST Microelectronics, armando.visconti(a)st.com. + * + * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c + * by Atmel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* SSP registers mapping */ +struct pl022 { + u32 ssp_cr0; /* 0x000 */ + u32 ssp_cr1; /* 0x004 */ + u32 ssp_dr; /* 0x008 */ + u32 ssp_sr; /* 0x00c */ + u32 ssp_cpsr; /* 0x010 */ + u32 ssp_imsc; /* 0x014 */ + u32 ssp_ris; /* 0x018 */ + u32 ssp_mis; /* 0x01c */ + u32 ssp_icr; /* 0x020 */ + u32 ssp_dmacr; /* 0x024 */ + u8 reserved_1[0x080 - 0x028]; + u32 ssp_itcr; /* 0x080 */ + u32 ssp_itip; /* 0x084 */ + u32 ssp_itop; /* 0x088 */ + u32 ssp_tdr; /* 0x08c */ + u8 reserved_2[0xFE0 - 0x090]; + u32 ssp_pid0; /* 0xfe0 */ + u32 ssp_pid1; /* 0xfe4 */ + u32 ssp_pid2; /* 0xfe8 */ + u32 ssp_pid3; /* 0xfec */ + u32 ssp_cid0; /* 0xff0 */ + u32 ssp_cid1; /* 0xff4 */ + u32 ssp_cid2; /* 0xff8 */ + u32 ssp_cid3; /* 0xffc */ +}; + +/* SSP Control Register 0 - SSP_CR0 */ +#define SSP_CR0_SPO (0x1 << 6) +#define SSP_CR0_SPH (0x1 << 7) +#define SSP_CR0_8BIT_MODE (0x07) +#define SSP_SCR_MAX (0xFF) +#define SSP_SCR_SHFT 8 + +/* SSP Control Register 0 - SSP_CR1 */ +#define SSP_CR1_MASK_SSE (0x1 << 1) + +#define SSP_CPSR_MAX (0xFE) + +/* SSP Status Register - SSP_SR */ +#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */ +#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */ +#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */ +#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */ +#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ + +struct pl022_spi_slave { + struct spi_slave slave; + void *regs; + unsigned int freq; +}; + +static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave) +{ + return container_of(slave, struct pl022_spi_slave, slave); +} + +/* + * Following three functions should be provided by the + * board support package. + */ +int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void __weak spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void __weak spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_init(void) +{ + /* do nothing */ +} + +/* + * ARM PL022 exists in different 'flavors'. + * This drivers currently support the standard variant (0x00041022), that has a + * 16bit wide and 8 locations deep TX/RX FIFO. + */ +static int pl022_is_supported(struct pl022_spi_slave *ps) +{ + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* PL022 version is 0x00041022 */ + if ((readl(&pl022->ssp_pid0) == 0x22) && + (readl(&pl022->ssp_pid1) == 0x10) && + ((readl(&pl022->ssp_pid2) & 0xf) == 0x04) && + (readl(&pl022->ssp_pid3) == 0x00)) + return 1; + + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct pl022_spi_slave *ps; + struct pl022 *pl022; + u16 scr = 1, prescaler, cr0 = 0, cpsr = 0; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ps = spi_alloc_slave(struct pl022_spi_slave, bus, cs); + if (!ps) + return NULL; + + ps->freq = max_hz; + + switch (bus) { + case 0: + ps->regs = (void *)CONFIG_SYS_SPI_BASE; + break; +#ifdef CONFIG_SYS_SPI_BASE1 + case 1: + ps->regs = (void *)CONFIG_SYS_SPI_BASE1; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE2 + case 2: + ps->regs = (void *)CONFIG_SYS_SPI_BASE2; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE3 + case 3: + ps->regs = (void *)CONFIG_SYS_SPI_BASE3; + break; +#endif + default: + free(ps); + return NULL; + } + + pl022 = (struct pl022 *)ps->regs; + + /* Check the PL022 version */ + if (!pl022_is_supported(ps)) { + free(ps); + return NULL; + } + + /* Set requested polarity and 8bit mode */ + cr0 = SSP_CR0_8BIT_MODE; + cr0 |= (mode & SPI_CPHA) ? SSP_CR0_SPH : 0; + cr0 |= (mode & SPI_CPOL) ? SSP_CR0_SPO : 0; + + writel(cr0, &pl022->ssp_cr0); + + /* Program the SSPClk frequency */ + prescaler = CONFIG_SYS_SPI_CLK / ps->freq; + + if (prescaler <= 0xFF) { + cpsr = prescaler; + } else { + for (scr = 1; scr <= SSP_SCR_MAX; scr++) { + if (!(prescaler % scr)) { + cpsr = prescaler / scr; + if (cpsr <= SSP_CPSR_MAX) + break; + } + } + + if (scr > SSP_SCR_MAX) { + scr = SSP_SCR_MAX; + cpsr = prescaler / scr; + cpsr &= SSP_CPSR_MAX; + } + } + + if (cpsr & 0x1) + cpsr++; + + writel(cpsr, &pl022->ssp_cpsr); + cr0 = readl(&pl022->ssp_cr0); + writel(cr0 | (scr - 1) << SSP_SCR_SHFT, &pl022->ssp_cr0); + + return &ps->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + + free(ps); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Enable the SPI hardware */ + setbits_le32(&pl022->ssp_cr1, SSP_CR1_MASK_SSE); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Disable the SPI hardware */ + writel(0x0, &pl022->ssp_cr1); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + u32 len_tx = 0, len_rx = 0, len; + u32 ret = 0; + const u8 *txp = dout; + u8 *rxp = din, value; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * TODO: The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + ret = -1; + + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (len_tx < len) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_TNF) { + value = (txp != NULL) ? *txp++ : 0; + writel(value, &pl022->ssp_dr); + len_tx++; + } + + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + + while (len_rx < len_tx) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} -- 1.7.11.7

3 13

[U-Boot] [PATCH v2] exynos5250: remove redundant SPI and PMIC related configs
by Inderpal Singh 07 Jan '14

07 Jan '14

They have been defined once already. Hence remove the redundant definitions. Signed-off-by: Inderpal Singh <inderpal.singh(a)linaro.org> --- v1 was posted as the first patch of [1] Changes in v2: - split from the patchset at [1] - removed redundant configs for PMIC - rebased to latest u-boot-samsung master branch [1] http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/157101 include/configs/exynos5250-dt.h | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 62b83d4..03b07b2 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -246,11 +246,6 @@ #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_I2C_EDID -/* PMIC */ -#define CONFIG_PMIC -#define CONFIG_PMIC_I2C -#define CONFIG_PMIC_MAX77686 - /* SPI */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SPI_FLASH @@ -278,27 +273,6 @@ #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX77686 -/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH - -#ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 50000000 -#define EXYNOS5_SPI_NUM_CONTROLLERS 5 -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X -- 1.7.9.5

3 5

[U-Boot] [PATCH 0/4] Add support for TI TPS65090
by Simon Glass 02 Jan '14

02 Jan '14

This series adds support for the TPS65090 PMIC as used on the Samsung ARM Chromebook. It is plumbed into smdk5250 for now, while we await the exynos5-dt board being applied upstream. Aaron Durbin (3): exynos5: Enable tps65090 on smdk5250 power: Explicitly select pmic device's bus exynos5: support tps65090 pmic Tom Wai-Hong Tam (1): power: Add support for TPS65090 PMU chip. board/samsung/smdk5250/smdk5250.c | 33 +++- doc/device-tree-bindings/power/tps65090.txt | 21 ++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65090.c | 296 ++++++++++++++++++++++++++++ drivers/power/power_i2c.c | 4 + include/configs/exynos5250-dt.h | 1 + include/fdtdec.h | 1 + include/power/tps65090_pmic.h | 83 ++++++++ lib/fdtdec.c | 1 + 9 files changed, 433 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/power/tps65090.txt create mode 100644 drivers/power/pmic/pmic_tps65090.c create mode 100644 include/power/tps65090_pmic.h -- 1.8.1.3

3 7

[U-Boot] [PATCH] i2c: s3c24xx: add hsi2c controller support
by Naveen Krishna Chatradhi 09 Dec '13

09 Dec '13

Add support for hsi2c controller available on exynos5420. Note: driver currently supports only fast speed mode 100kbps Signed-off-by: Naveen Krishna Chatradhi <ch.naveen(a)samsung.com> Signed-off-by: R. Chandrasekar <rc.sekar(a)samsung.com> --- drivers/i2c/s3c24x0_i2c.c | 389 ++++++++++++++++++++++++++++++++++++++++++--- drivers/i2c/s3c24x0_i2c.h | 33 ++++ 2 files changed, 397 insertions(+), 25 deletions(-) diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 769a2ba..3117ab7 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -32,6 +32,7 @@ #include <asm/arch/clk.h> #include <asm/arch/cpu.h> #include <asm/arch/pinmux.h> +#include <asm/arch/clock.h> #else #include <asm/arch/s3c24x0_cpu.h> #endif @@ -50,6 +51,60 @@ #define I2C_NOK_LA 3 /* Lost arbitration */ #define I2C_NOK_TOUT 4 /* time out */ +/* HSI2C specific register description */ + +/* I2C_CTL Register bits */ +#define HSI2C_FUNC_MODE_I2C (1u << 0) +#define HSI2C_MASTER (1u << 3) +#define HSI2C_RXCHON (1u << 6) /* Write/Send */ +#define HSI2C_TXCHON (1u << 7) /* Read/Receive */ +#define HSI2C_SW_RST (1u << 31) + +/* I2C_FIFO_CTL Register bits */ +#define HSI2C_RXFIFO_EN (1u << 0) +#define HSI2C_TXFIFO_EN (1u << 1) +#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) +#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) + +/* I2C_TRAILING_CTL Register bits */ +#define HSI2C_TRAILING_COUNT (0xff) + +/* I2C_INT_EN Register bits */ +#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) +#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) +#define HSI2C_INT_TRAILING_EN (1u << 6) +#define HSI2C_INT_I2C_EN (1u << 9) + +/* I2C_CONF Register bits */ +#define HSI2C_AUTO_MODE (1u << 31) +#define HSI2C_10BIT_ADDR_MODE (1u << 30) +#define HSI2C_HS_MODE (1u << 29) + +/* I2C_AUTO_CONF Register bits */ +#define HSI2C_READ_WRITE (1u << 16) +#define HSI2C_STOP_AFTER_TRANS (1u << 17) +#define HSI2C_MASTER_RUN (1u << 31) + +/* I2C_TIMEOUT Register bits */ +#define HSI2C_TIMEOUT_EN (1u << 31) + +/* I2C_TRANS_STATUS register bits */ +#define HSI2C_MASTER_BUSY (1u << 17) +#define HSI2C_SLAVE_BUSY (1u << 16) +#define HSI2C_NO_DEV (1u << 3) +#define HSI2C_NO_DEV_ACK (1u << 2) +#define HSI2C_TRANS_ABORT (1u << 1) +#define HSI2C_TRANS_DONE (1u << 0) +#define HSI2C_TIMEOUT_AUTO (0u << 0) + +#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) + +/* Controller operating frequency, timing values for operation + * are calculated against this frequency + */ +#define HSI2C_FS_TX_CLOCK 1000000 + +/* S3C I2C Controller bits */ #define I2CSTAT_BSY 0x20 /* Busy bit */ #define I2CSTAT_NACK 0x01 /* Nack bit */ #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ @@ -61,6 +116,7 @@ #define I2C_TIMEOUT 1 /* 1 second */ +#define HSI2C_TIMEOUT 100 /* * For SPL boot some boards need i2c before SDRAM is initialised so force @@ -120,9 +176,23 @@ static int WaitForXfer(struct s3c24x0_i2c *i2c) return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; } -static int IsACK(struct s3c24x0_i2c *i2c) +static int hsi2c_wait_for_irq(struct exynos5_hsi2c *i2c) { - return !(readl(&i2c->iicstat) & I2CSTAT_NACK); + int i = HSI2C_TIMEOUT * 10; + int ret = I2C_NOK_TOUT; + + while (i > 0) { + /* wait for a while and retry */ + udelay(50); + if (readl(&i2c->usi_int_stat) & + (HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN)) { + ret = I2C_OK; + break; + } + i--; + } + + return ret; } static void ReadWriteByte(struct s3c24x0_i2c *i2c) @@ -130,6 +200,22 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c) writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } +static void hsi2c_clear_irqpd(struct exynos5_hsi2c *i2c) +{ + writel(readl(&i2c->usi_int_stat), &i2c->usi_int_stat); +} + +static int hsi2c_isack(struct exynos5_hsi2c *i2c) +{ + return readl(&i2c->usi_trans_status) & + (HSI2C_NO_DEV | HSI2C_NO_DEV_ACK); +} + +static int IsACK(struct s3c24x0_i2c *i2c) +{ + return !(readl(&i2c->iicstat) & I2CSTAT_NACK); +} + static struct s3c24x0_i2c *get_base_i2c(void) { #ifdef CONFIG_EXYNOS4 @@ -147,6 +233,18 @@ static struct s3c24x0_i2c *get_base_i2c(void) #endif } +static struct exynos5_hsi2c *get_base_hsi2c(void) +{ + struct exynos5_hsi2c *i2c = NULL; + int bus = g_current_bus; + + if (proid_is_exynos5420()) + i2c = (struct exynos5_hsi2c *)(EXYNOS5420_I2C_BASE + + ((bus) * EXYNOS5_I2C_SPACING)); + + return i2c; +} + static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) { ulong freq, pres = 16, div; @@ -174,6 +272,74 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); } +static void hsi2c_ch_init(struct exynos5_hsi2c *i2c, int speed) +{ + u32 i2c_timeout; + ulong clkin = get_i2c_clk(); + u32 i2c_timing_s1; + u32 i2c_timing_s2; + u32 i2c_timing_s3; + u32 i2c_timing_sla; + unsigned int op_clk = HSI2C_FS_TX_CLOCK; + unsigned int n_clkdiv; + unsigned int t_start_su, t_start_hd; + unsigned int t_stop_su; + unsigned int t_data_su, t_data_hd; + unsigned int t_scl_l, t_scl_h; + unsigned int t_sr_release; + unsigned int t_ftl_cycle; + unsigned int i = 0, utemp0 = 0, utemp1 = 0, utemp2 = 0; + + /* FPCLK / FI2C = + * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE + * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + * uTemp1 = (TSCLK_L + TSCLK_H + 2) + * uTemp2 = TSCLK_L + TSCLK_H + */ + t_ftl_cycle = (readl(&i2c->usi_conf) >> 16) & 0x7; + utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; + + /* CLK_DIV max is 256 */ + for (i = 0; i < 256; i++) { + utemp1 = utemp0 / (i + 1); + /* SCLK_L/H max is 256 / 2 */ + if (utemp1 < 128) { + utemp2 = utemp1 - 2; + break; + } + } + + n_clkdiv = i; + t_scl_l = utemp2 / 2; + t_scl_h = utemp2 / 2; + t_start_su = t_scl_l; + t_start_hd = t_scl_l; + t_stop_su = t_scl_l; + t_data_su = t_scl_l / 2; + t_data_hd = t_scl_l / 2; + t_sr_release = utemp2; + + i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; + i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; + i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; + i2c_timing_sla = t_data_hd << 0; + + writel(HSI2C_TRAILING_COUNT, &i2c->usi_trailing_ctl); + + /* Clear to enable Timeout */ + i2c_timeout = readl(&i2c->usi_timeout); + i2c_timeout &= ~HSI2C_TIMEOUT_EN; + writel(i2c_timeout, &i2c->usi_timeout); + + writel(readl(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); + + /* Currently operating in Fast speed mode. */ + writel(i2c_timing_s1, &i2c->usi_timing_fs1); + writel(i2c_timing_s2, &i2c->usi_timing_fs2); + writel(i2c_timing_s3, &i2c->usi_timing_fs3); + writel(i2c_timing_sla, &i2c->usi_timing_sla); +} + /* * MULTI BUS I2C support */ @@ -181,16 +347,18 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) #ifdef CONFIG_I2C_MULTI_BUS int i2c_set_bus_num(unsigned int bus) { - struct s3c24x0_i2c *i2c; - if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) { debug("Bad bus: %d\n", bus); return -1; } g_current_bus = bus; - i2c = get_base_i2c(); - i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (proid_is_exynos5420() && (bus > 3)) { + hsi2c_ch_init(get_base_hsi2c(), + CONFIG_SYS_I2C_SPEED); + } else + i2c_ch_init(get_base_i2c(), CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE); return 0; } @@ -269,24 +437,182 @@ void i2c_init(int speed, int slaveadd) } /* + * Send a STOP event and wait for it to have completed + * + * @param mode If it is a master transmitter or receiver + * @return I2C_OK if the line became idle before timeout I2C_NOK_TOUT otherwise + */ +static int hsi2c_send_stop(struct exynos5_hsi2c *i2c, int result) +{ + int timeout; + int ret = I2C_NOK_TOUT; + + /* Wait for the STOP to send and the bus to go idle */ + for (timeout = HSI2C_TIMEOUT; timeout > 0; timeout -= 5) { + if (!(readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY)) { + ret = I2C_OK; + goto out; + } + udelay(5); + } + out: + /* Setting the STOP event to fire */ + writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); + writel(0x0, &i2c->usi_int_en); + + return (result == I2C_OK) ? ret : result; +} + +static int hsi2c_write(unsigned char chip, + unsigned char addr[], + unsigned char alen, + unsigned char data[], + unsigned short len) +{ + struct exynos5_hsi2c *i2c = get_base_hsi2c(); + int i = 0, result = I2C_OK; + u32 i2c_auto_conf; + u32 stat; + + /* Check I2C bus idle */ + i = HSI2C_TIMEOUT * 20; + while ((readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) + && (i > 0)) { + udelay(50); + i--; + } + + stat = readl(&i2c->usi_trans_status); + + if (stat & HSI2C_MASTER_BUSY) { + debug("%s: bus busy\n", __func__); + return I2C_NOK_TOUT; + } + /* Disable TXFIFO and RXFIFO */ + writel(0, &i2c->usi_fifo_ctl); + + /* chip address */ + writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); + + /* Enable interrupts */ + writel((HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN), + &i2c->usi_int_en); + + /* usi_ctl enable i2c func, master write configure */ + writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + &i2c->usi_ctl); + + /* i2c_conf configure */ + writel(readl(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); + + /* auto_conf for write length and stop configure */ + i2c_auto_conf = ((len + alen) | HSI2C_STOP_AFTER_TRANS); + i2c_auto_conf &= ~HSI2C_READ_WRITE; + writel(i2c_auto_conf, &i2c->usi_auto_conf); + + /* Master run, start xfer */ + writel(readl(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN, + &i2c->usi_auto_conf); + + result = hsi2c_wait_for_irq(i2c); + if ((result == I2C_OK) && hsi2c_isack(i2c)) { + result = I2C_NACK; + goto err; + } + + for (i = 0; i < alen && (result == I2C_OK); i++) { + writel(addr[i], &i2c->usi_txdata); + result = hsi2c_wait_for_irq(i2c); + } + + for (i = 0; i < len && (result == I2C_OK); i++) { + writel(data[i], &i2c->usi_txdata); + result = hsi2c_wait_for_irq(i2c); + } + + err: + hsi2c_clear_irqpd(i2c); + return hsi2c_send_stop(i2c, result); +} + +static int hsi2c_read(unsigned char chip, + unsigned char addr[], + unsigned char alen, + unsigned char data[], + unsigned short len, + int check) +{ + struct exynos5_hsi2c *i2c = get_base_hsi2c(); + int i, result; + u32 i2c_auto_conf; + + if (!check) { + result = hsi2c_write(chip, addr, alen, data, 0); + if (result != I2C_OK) { + debug("write failed Result = %d\n", result); + return result; + } + } + + /* start read */ + /* Disable TXFIFO and RXFIFO */ + writel(0, &i2c->usi_fifo_ctl); + + /* chip address */ + writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); + + /* Enable interrupts */ + writel(HSI2C_INT_I2C_EN, &i2c->usi_int_en); + + /* i2c_conf configure */ + writel(readl(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); + + /* auto_conf, length and stop configure */ + i2c_auto_conf = (len | HSI2C_STOP_AFTER_TRANS | HSI2C_READ_WRITE); + writel(i2c_auto_conf, &i2c->usi_auto_conf); + + /* usi_ctl enable i2c func, master WRITE configure */ + writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + &i2c->usi_ctl); + + /* Master run, start xfer */ + writel(readl(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN, + &i2c->usi_auto_conf); + + result = hsi2c_wait_for_irq(i2c); + if ((result == I2C_OK) && hsi2c_isack(i2c)) { + result = I2C_NACK; + goto err; + } + + for (i = 0; i < len && (result == I2C_OK); i++) { + result = hsi2c_wait_for_irq(i2c); + data[i] = readl(&i2c->usi_rxdata); + } + err: + /* Stop and quit */ + hsi2c_clear_irqpd(i2c); + return hsi2c_send_stop(i2c, result); +} + +/* * cmd_type is 0 for write, 1 for read. * * addr_len can take any value from 0-255, it is only limited * by the char, we could make it larger if needed. If it is * 0 we skip the address write cycle. */ -static int i2c_transfer(struct s3c24x0_i2c *i2c, - unsigned char cmd_type, +static int i2c_transfer(unsigned char cmd_type, unsigned char chip, unsigned char addr[], unsigned char addr_len, unsigned char data[], unsigned short data_len) { + struct s3c24x0_i2c *i2c = get_base_i2c(); int i, result; if (data == 0 || data_len == 0) { - /*Don't support data transfer of no length or to address 0 */ debug("i2c_transfer: bad call\n"); return I2C_NOK; } @@ -428,10 +754,8 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, int i2c_probe(uchar chip) { - struct s3c24x0_i2c *i2c; uchar buf[1]; - i2c = get_base_i2c(); buf[0] = 0; /* @@ -439,12 +763,15 @@ int i2c_probe(uchar chip) * address was <ACK>ed (i.e. there was a chip at that address which * drove the data line low). */ - return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; + if (proid_is_exynos5420() && (g_current_bus > 3)) + return (hsi2c_read(chip, 0, 1, buf, 1, 1) != I2C_OK); + else + return i2c_transfer( + I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; } int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct s3c24x0_i2c *i2c; uchar xaddr[4]; int ret; @@ -476,9 +803,13 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif - i2c = get_base_i2c(); - ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen, - buffer, len); + if (proid_is_exynos5420() && (g_current_bus > 3)) + ret = hsi2c_read(chip, &xaddr[4 - alen], + alen, buffer, len, 0); + else + ret = i2c_transfer(I2C_READ, chip << 1, + &xaddr[4 - alen], alen, buffer, len); + if (ret != 0) { debug("I2c read: failed %d\n", ret); return 1; @@ -488,7 +819,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct s3c24x0_i2c *i2c; uchar xaddr[4]; if (alen > 4) { @@ -518,31 +848,36 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif - i2c = get_base_i2c(); - return (i2c_transfer - (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, - len) != 0); + if (proid_is_exynos5420() && (g_current_bus > 3)) + return (hsi2c_write(chip, &xaddr[4 - alen], + alen, buffer, len) != 0); + else + return (i2c_transfer(I2C_WRITE, chip << 1, + &xaddr[4 - alen], alen, buffer, len) != 0); } #ifdef CONFIG_OF_CONTROL void board_i2c_init(const void *blob) { + struct s3c24x0_i2c_bus *bus; int node_list[CONFIG_MAX_I2C_NUM]; int count, i; count = fdtdec_find_aliases_for_id(blob, "i2c", COMPAT_SAMSUNG_S3C2440_I2C, node_list, CONFIG_MAX_I2C_NUM); - for (i = 0; i < count; i++) { - struct s3c24x0_i2c_bus *bus; int node = node_list[i]; if (node <= 0) continue; bus = &i2c_bus[i]; + bus->regs = (struct s3c24x0_i2c *) - fdtdec_get_addr(blob, node, "reg"); + fdtdec_get_addr(blob, node, "reg"); + bus->hsregs = (struct exynos5_hsi2c *) + fdtdec_get_addr(blob, node, "reg"); + bus->id = pinmux_decode_periph_id(blob, node); bus->node = node; bus->bus_num = i2c_busses++; @@ -589,7 +924,11 @@ int i2c_reset_port_fdt(const void *blob, int node) return -1; } - i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (proid_is_exynos5420() && (bus > 3)) + hsi2c_ch_init(i2c->hsregs, CONFIG_SYS_I2C_SPEED); + else + i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE); return 0; } diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index a56d749..81ed19c 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -31,10 +31,43 @@ struct s3c24x0_i2c { u32 iiclc; }; +struct exynos5_hsi2c { + u32 usi_ctl; + u32 usi_fifo_ctl; + u32 usi_trailing_ctl; + u32 usi_clk_ctl; + u32 usi_clk_slot; + u32 spi_ctl; + u32 uart_ctl; + u32 res1; + u32 usi_int_en; + u32 usi_int_stat; + u32 usi_modem_stat; + u32 usi_error_stat; + u32 usi_fifo_stat; + u32 usi_txdata; + u32 usi_rxdata; + u32 res2; + u32 usi_conf; + u32 usi_auto_conf; + u32 usi_timeout; + u32 usi_manual_cmd; + u32 usi_trans_status; + u32 usi_timing_hs1; + u32 usi_timing_hs2; + u32 usi_timing_hs3; + u32 usi_timing_fs1; + u32 usi_timing_fs2; + u32 usi_timing_fs3; + u32 usi_timing_sla; + u32 i2c_addr; +}; + struct s3c24x0_i2c_bus { int node; /* device tree node */ int bus_num; /* i2c bus number */ struct s3c24x0_i2c *regs; + struct exynos5_hsi2c *hsregs; int id; }; #endif /* _S3C24X0_I2C_H */ -- 1.7.9.5

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