June 2013 - U-Boot

[U-Boot] [PATCH] vf610twr: Drop unneeded 'or' operator
by Fabio Estevam 05 Jun '13

05 Jun '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> No need to use the or operator, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/vf610twr/vf610twr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 04fa882..1156194 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -308,7 +308,7 @@ int board_mmc_init(bd_t *bis) imx_iomux_v3_setup_multiple_pads( esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); - status |= fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + status = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); return status; } -- 1.8.1.2

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[U-Boot] [PATCH V2 REPOST 1/2] lcd: add functions to set up simplefb device tree
by Stephen Warren 05 Jun '13

05 Jun '13

simple-framebuffer is a new device tree binding that describes a pre- configured frame-buffer memory region and its format. The Linux kernel contains a driver that supports this binding. Implement functions to create a DT node (or fill in an existing node) with parameters that describe the framebuffer format that U-Boot is using. This will be immediately used by the Raspberry Pi board in U-Boot, and likely will be used by the Samsung ARM ChromeBook support soon too. It could well be used by many other boards (e.g. Tegra boards with built-in LCD panels, which aren't yet supported by the Linux kernel). Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> Acked-by: Simon Glass <sjg(a)chromium.org> --- v2: Add binding doc, remove ifdefs from lcd.h --- common/lcd.c | 87 ++++++++++++++++++++ .../video/simple-framebuffer.txt | 25 ++++++ include/lcd.h | 3 + 3 files changed, 115 insertions(+) create mode 100644 doc/device-tree-bindings/video/simple-framebuffer.txt diff --git a/common/lcd.c b/common/lcd.c index edae835..3a60484 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -57,6 +57,10 @@ #include <atmel_lcdc.h> #endif +#if defined(CONFIG_LCD_DT_SIMPLEFB) +#include <libfdt.h> +#endif + /************************************************************************/ /* ** FONT DATA */ /************************************************************************/ @@ -1182,3 +1186,86 @@ int lcd_get_screen_columns(void) { return CONSOLE_COLS; } + +#if defined(CONFIG_LCD_DT_SIMPLEFB) +static int lcd_dt_simplefb_configure_node(void *blob, int off) +{ + u32 stride; + fdt32_t cells[2]; + int ret; + const char format[] = +#if LCD_BPP == LCD_COLOR16 + "r5g6b5"; +#else + ""; +#endif + + if (!format[0]) + return -1; + + stride = panel_info.vl_col * 2; + + cells[0] = cpu_to_fdt32(gd->fb_base); + cells[1] = cpu_to_fdt32(stride * panel_info.vl_row); + ret = fdt_setprop(blob, off, "reg", cells, sizeof(cells[0]) * 2); + if (ret < 0) + return -1; + + cells[0] = cpu_to_fdt32(panel_info.vl_col); + ret = fdt_setprop(blob, off, "width", cells, sizeof(cells[0])); + if (ret < 0) + return -1; + + cells[0] = cpu_to_fdt32(panel_info.vl_row); + ret = fdt_setprop(blob, off, "height", cells, sizeof(cells[0])); + if (ret < 0) + return -1; + + cells[0] = cpu_to_fdt32(stride); + ret = fdt_setprop(blob, off, "stride", cells, sizeof(cells[0])); + if (ret < 0) + return -1; + + ret = fdt_setprop(blob, off, "format", format, strlen(format) + 1); + if (ret < 0) + return -1; + + ret = fdt_delprop(blob, off, "status"); + if (ret < 0) + return -1; + + return 0; +} + +int lcd_dt_simplefb_add_node(void *blob) +{ + const char compat[] = "simple-framebuffer"; + const char disabled[] = "disabled"; + int off, ret; + + off = fdt_add_subnode(blob, 0, "framebuffer"); + if (off < 0) + return -1; + + ret = fdt_setprop(blob, off, "status", disabled, sizeof(disabled)); + if (ret < 0) + return -1; + + ret = fdt_setprop(blob, off, "compatible", compat, sizeof(compat)); + if (ret < 0) + return -1; + + return lcd_dt_simplefb_configure_node(blob, off); +} + +int lcd_dt_simplefb_enable_existing_node(void *blob) +{ + int off; + + off = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer"); + if (off < 0) + return -1; + + return lcd_dt_simplefb_configure_node(blob, off); +} +#endif diff --git a/doc/device-tree-bindings/video/simple-framebuffer.txt b/doc/device-tree-bindings/video/simple-framebuffer.txt new file mode 100644 index 0000000..3ea4605 --- /dev/null +++ b/doc/device-tree-bindings/video/simple-framebuffer.txt @@ -0,0 +1,25 @@ +Simple Framebuffer + +A simple frame-buffer describes a raw memory region that may be rendered to, +with the assumption that the display hardware has already been set up to scan +out from that buffer. + +Required properties: +- compatible: "simple-framebuffer" +- reg: Should contain the location and size of the framebuffer memory. +- width: The width of the framebuffer in pixels. +- height: The height of the framebuffer in pixels. +- stride: The number of bytes in each line of the framebuffer. +- format: The format of the framebuffer surface. Valid values are: + - r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b). + +Example: + + framebuffer { + compatible = "simple-framebuffer"; + reg = <0x1d385000 (1600 * 1200 * 2)>; + width = <1600>; + height = <1200>; + stride = <(1600 * 2)>; + format = "r5g6b5"; + }; diff --git a/include/lcd.h b/include/lcd.h index c6e7fc5..30225ed 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -324,6 +324,9 @@ void lcd_show_board_info(void); /* Return the size of the LCD frame buffer, and the line length */ int lcd_get_size(int *line_length); +int lcd_dt_simplefb_add_node(void *blob); +int lcd_dt_simplefb_enable_existing_node(void *blob); + /************************************************************************/ /* ** BITMAP DISPLAY SUPPORT */ /************************************************************************/ -- 1.7.10.4

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[U-Boot] arm, arm335x: add watchdog support
by Heiko Schocher 05 Jun '13

05 Jun '13

Add TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog support. Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Tom Rini <trini(a)ti.com> --- arch/arm/include/asm/arch-am33xx/cpu.h | 20 ++++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/omap_wdt.c | 115 +++++++++++++++++++++++++++++++++ 3 Dateien geändert, 136 Zeilen hinzugefügt(+) create mode 100644 drivers/watchdog/omap_wdt.c diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 3d3a7c8..fb44654 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -61,6 +61,26 @@ #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232 +/* + * Watchdog: + * Using the prescaler, the OMAP watchdog could go for many + * months before firing. These limits work without scaling, + * with the 60 second default assumed by most tools and docs. + */ +#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */ +#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ +#define TIMER_MARGIN_MIN 1 + +#define PTV 0 /* prescale */ +#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1) +#define WDT_WWPS_PEND_WCLR BIT(0) +#define WDT_WWPS_PEND_WLDR BIT(2) +#define WDT_WWPS_PEND_WTGR BIT(3) +#define WDT_WWPS_PEND_WSPR BIT(4) + +#define WDT_WCLR_PRE BIT(5) +#define WDT_WCLR_PTV_OFF 2 + #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct gpmc_cs { diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index d57578d..46adc42 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o COBJS-$(CONFIG_S5P) += s5p_wdt.o COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o COBJS-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o +COBJS-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c new file mode 100644 index 0000000..dc4df98 --- /dev/null +++ b/drivers/watchdog/omap_wdt.c @@ -0,0 +1,115 @@ +/* + * omap_wdt.c + * + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs(a)denx.de. + * + * Based on: + * + * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog + * + * Author: MontaVista Software, Inc. + * <gdavis(a)mvista.com> or <source(a)mvista.com> + * + * 2003 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * History: + * + * 20030527: George G. Davis <gdavis(a)mvista.com> + * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c + * (c) Copyright 2000 Oleg Drokin <green(a)crimea.edu> + * Based on SoftDog driver by Alan Cox <alan(a)lxorguk.ukuu.org.uk> + * + * Copyright (c) 2004 Texas Instruments. + * 1. Modified to support OMAP1610 32-KHz watchdog timer + * 2. Ported to 2.6 kernel + * + * Copyright (c) 2005 David Brownell + * Use the driver model and standard identifiers; handle bigger timeouts. + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/arch/cpu.h> + +/* Hardware timeout in seconds */ +#define WDT_HW_TIMEOUT 60 + +static unsigned int wdt_trgr_pattern = 0x1234; + +void hw_watchdog_reset(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* wait for posted write to complete */ + while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) + ; + + wdt_trgr_pattern = ~wdt_trgr_pattern; + writel(wdt_trgr_pattern, &wdt->wdtwtgr); + + /* wait for posted write to complete */ + while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR)) + ; +} + +static int omap_wdt_set_timeout(unsigned int timeout) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + u32 pre_margin = GET_WLDR_VAL(timeout); + + /* just count up at 32 KHz */ + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) + ; + + writel(pre_margin, &wdt->wdtwldr); + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) + ; + + return 0; +} + +void hw_watchdog_init(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* initialize prescaler */ + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) + ; + + writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr); + while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) + ; + + omap_wdt_set_timeout(WDT_HW_TIMEOUT); + + /* Sequence to enable the watchdog */ + writel(0xBBBB, &wdt->wdtwspr); + while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) + ; + + writel(0x4444, &wdt->wdtwspr); + while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) + ; +} + +void hw_watchdog_disable(void) +{ + struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; + + /* + * Disable watchdog + */ + writel(0xAAAA, &wdt->wdtwspr); + while (readl(&wdt->wdtwwps) != 0x0) + ; + writel(0x5555, &wdt->wdtwspr); + while (readl(&wdt->wdtwwps) != 0x0) + ; +} -- 1.7.11.7

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[U-Boot] [PATCH] powerpc/mpc85xx:Add iprot input arg in create_TLB0/1_entry
by Prabhakar Kushwaha 05 Jun '13

05 Jun '13

create_tlb1_entry and create_tlb0_entry creates TLB entries with IPROT bit set by default. Any TLB entries with IPROT = 1 can not be invalidated. Add IPROT as input argument for TLB entry creation APIs. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master arch/powerpc/cpu/mpc85xx/start.S | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 4f0480b..cbe166d 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -174,11 +174,11 @@ l2_disabled: mtspr DBSR,r1 /* Clear all valid bits */ - .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch + .macro create_tlb1_entry esel iprot ts tsize epn wimg rpn perm phy_high scratch lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l mtspr MAS0, \scratch - lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h + lis \scratch, FSL_BOOKE_MAS1(1, \iprot, 0, \ts, \tsize)@h ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l mtspr MAS1, \scratch lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h @@ -196,11 +196,11 @@ l2_disabled: isync .endm - .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch + .macro create_tlb0_entry esel iprot ts tsize epn wimg rpn perm phy_high scratch lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l mtspr MAS0, \scratch - lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h + lis \scratch, FSL_BOOKE_MAS1(1, \iprot, 0, \ts, \tsize)@h ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l mtspr MAS1, \scratch lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h @@ -357,7 +357,7 @@ l2_disabled: */ /* create a temp mapping TLB0[0] for LBCR */ - create_tlb0_entry 0, \ + create_tlb0_entry 0, 1,\ 0, BOOKE_PAGESZ_4K, \ CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \ CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \ @@ -484,14 +484,14 @@ nexti: mflr r1 /* R1 = our PC */ * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. * and this window is outside of 4K boot window. */ - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, 0,\ 0, BOOKE_PAGESZ_4M, \ CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, 0,\ 0, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -501,7 +501,7 @@ nexti: mflr r1 /* R1 = our PC */ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address * because "nexti" will resize TLB to 4K */ - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, 0,\ 0, BOOKE_PAGESZ_256K, \ CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \ CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -536,7 +536,7 @@ create_ccsr_new_tlb: ori r8, r8, CONFIG_SYS_CCSRBAR@l lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l - create_tlb0_entry 0, \ + create_tlb0_entry 0, 1,\ 0, BOOKE_PAGESZ_4K, \ CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ @@ -546,7 +546,7 @@ create_ccsr_new_tlb: * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: - create_tlb0_entry 1, \ + create_tlb0_entry 1, 1,\ 0, BOOKE_PAGESZ_4K, \ CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ @@ -712,7 +712,7 @@ create_ccsr_l2_tlb: * Create a TLB for the MMR location of CCSR * to access L2CSR0 register */ - create_tlb0_entry 0, \ + create_tlb0_entry 0, 1\ 0, BOOKE_PAGESZ_4K, \ CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ @@ -1041,7 +1041,7 @@ create_init_ram_area: #ifdef NOR_BOOT /* create a temp mapping in AS=1 to the 4M boot window */ - create_tlb1_entry 15, \ + create_tlb1_entry 15, 1,\ 1, BOOKE_PAGESZ_4M, \ CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -1051,7 +1051,7 @@ create_init_ram_area: /* create a temp mapping in AS = 1 for Flash mapping * created by PBL for ISBC code */ - create_tlb1_entry 15, \ + create_tlb1_entry 15, 1,\ 1, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -1061,7 +1061,7 @@ create_init_ram_area: * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. */ - create_tlb1_entry 15, \ + create_tlb1_entry 15, 1,\ 1, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -1071,14 +1071,14 @@ create_init_ram_area: /* create a temp mapping in AS=1 to the stack */ #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) - create_tlb1_entry 14, \ + create_tlb1_entry 14, 1,\ 1, BOOKE_PAGESZ_16K, \ CONFIG_SYS_INIT_RAM_ADDR, 0, \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 #else - create_tlb1_entry 14, \ + create_tlb1_entry 14, 1,\ 1, BOOKE_PAGESZ_16K, \ CONFIG_SYS_INIT_RAM_ADDR, 0, \ CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ -- 1.7.9.5

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[U-Boot] TPM patches to pull if you wish
by Simon Glass 05 Jun '13

05 Jun '13

Hi Tom, I pushed the TPM patches to a branch for you if you want to pick them up. I ended up squashing the config patch into the others - since otherwise snow will not build for one commit. Does that seem acceptable or should I resend the whole series again? Here are the original patches: http://patchwork.ozlabs.org/bundle/sjg/tpm/ The following changes since commit d6639d10dbfa42dc888f8917012550b632a88959: Merge branch 'master' of git://git.denx.de/u-boot-nand-flash (2013-05-31 18:28:47 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git tpm for you to fetch changes up to 1b393db5870927d68c42a46e6c5877c8d0d83910: tpm: Reorganize the I2C TPM driver (2013-06-03 01:31:23 -0700) ---------------------------------------------------------------- Che-liang Chiou (1): tpm: Rename generic_lpc_tpm to tpm_tis_lpc Tom Wai-Hong Tam (2): x86: config: Reflect the name changes of LPC TPM configs tpm: Reorganize the I2C TPM driver Vincent Palatin (1): tpm: Add support for new Infineon I2C TPM (SLB 9645 TT 1.2 I2C) README | 18 +++- drivers/tpm/Makefile | 7 +- drivers/tpm/slb9635_i2c/compatibility.h | 51 --------- drivers/tpm/tis_i2c.c | 4 + drivers/tpm/{slb9635_i2c => }/tpm.c | 280 ++++++++++++++++++++++++++++++++++++++--------- drivers/tpm/{slb9635_i2c/tpm.h => tpm_private.h} | 46 ++------ drivers/tpm/{slb9635_i2c => }/tpm_tis_i2c.c | 354 ++++++++++++++++++++++++++++++++++++------------------------ drivers/tpm/{generic_lpc_tpm.c => tpm_tis_lpc.c} | 0 include/configs/coreboot.h | 3 +- include/configs/exynos5250-dt.h | 6 +- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 12 files changed, 486 insertions(+), 285 deletions(-) delete mode 100644 drivers/tpm/slb9635_i2c/compatibility.h rename drivers/tpm/{slb9635_i2c => }/tpm.c (63%) rename drivers/tpm/{slb9635_i2c/tpm.h => tpm_private.h} (71%) rename drivers/tpm/{slb9635_i2c => }/tpm_tis_i2c.c (59%) rename drivers/tpm/{generic_lpc_tpm.c => tpm_tis_lpc.c} (100%) Regards, Simon

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[U-Boot] Please pull u-boot-ti/master
by Tom Rini 05 Jun '13

05 Jun '13

Hello, The following changes since commit 3da0e5750b24a9491058df6126c7be577a276c09: arm: factorize relocate_code routine (2013-05-30 20:24:38 +0200) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to 4596dcc1d4ea5763e0f92cf5becd9fc7d4c6e674: am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c (2013-06-05 08:46:49 -0400) ---------------------------------------------------------------- Tom Rini (3): omap-common/hwinit-common.c: Mark omap_rev_string as static am33xx: Correct NON_SECURE_SRAM_START/END am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c arch/arm/cpu/armv7/omap-common/boot-common.c | 39 ++++++++++++++++++++++++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 38 +---------------------- arch/arm/include/asm/arch-am33xx/omap.h | 4 +-- arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + board/isee/igep0033/board.c | 9 ++++++ board/phytec/pcm051/board.c | 9 ++++++ board/ti/am335x/board.c | 9 ++++++ board/ti/ti814x/evm.c | 9 ++++++ include/configs/am335x_evm.h | 10 ++++-- include/configs/igep0033.h | 10 ++++-- include/configs/pcm051.h | 10 ++++-- 13 files changed, 105 insertions(+), 45 deletions(-) -- Tom

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[U-Boot] [PATCH 1/1 RESEND] NET: Fix system hanging if NET device is not installed
by Jim Lin 05 Jun '13

05 Jun '13

If we try to boot from NET device, NetInitLoop in net.c will be invoked. If NET device is not installed, eth_get_dev() function will return eth_current value, which is NULL. When NetInitLoop is called, "eth_get_dev->enetaddr" will access restricted memory area and therefore cause hanging. This issue is found on Tegra30 Cardhu platform after adding CONFIG_CMD_NET and CONFIG_CMD_DHCP in config header file. Signed-off-by: Jim Lin <jilin(a)nvidia.com> --- net/net.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/net/net.c b/net/net.c index df94789..7663b9c 100644 --- a/net/net.c +++ b/net/net.c @@ -271,7 +271,8 @@ static void NetInitLoop(void) #endif env_changed_id = env_id; } - memcpy(NetOurEther, eth_get_dev()->enetaddr, 6); + if (eth_get_dev()) + memcpy(NetOurEther, eth_get_dev()->enetaddr, 6); return; } -- 1.7.7

2 1

[U-Boot] [U-BOOT] [PATCH] arm: da830: moved pinmux configurations to the arch tree
by Vishwanathrao Badarkhe, Manish 05 Jun '13

05 Jun '13

Move pinmux configurations for the DA830 SoCs from board file to the arch tree so that it can be used for all da830 based devices. Also, avoids duplicate pinmuxing in case of NAND. Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b(a)ti.com> --- Depends on: http://u-boot.10912.n7.nabble.com/PATCH-da830-add-MMC-support-td155590.html :100644 100644 dec7bfb... bba4671... M arch/arm/cpu/arm926ejs/davinci/Makefile :000000 100644 0000000... d0c964a... A arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c :100644 100644 a851f1f... beaf0d6... M arch/arm/include/asm/arch-davinci/pinmux_defs.h :100644 100644 bf014ae... a4e9254... M board/davinci/da8xxevm/da830evm.c :100644 100644 28995a0... 00e92a6... M include/configs/da830evm.h arch/arm/cpu/arm926ejs/davinci/Makefile | 1 + arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c | 151 +++++++++++++++++++++++ arch/arm/include/asm/arch-davinci/pinmux_defs.h | 15 ++- board/davinci/da8xxevm/da830evm.c | 145 ++-------------------- include/configs/da830evm.h | 1 + 5 files changed, 181 insertions(+), 132 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index dec7bfb..bba4671 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_SOC_DM646X) += dm646x.o +COBJS-$(CONFIG_SOC_DA830) += da830_pinmux.o COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c new file mode 100644 index 0000000..d0c964a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c @@ -0,0 +1,151 @@ +/* + * Pinmux configurations for the DA830 SoCs + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/arch/davinci_misc.h> +#include <asm/arch/hardware.h> +#include <asm/arch/pinmux_defs.h> + +/* SPI0 pin muxer settings */ +const struct pinmux_config spi0_pins_base[] = { + { pinmux(7), 1, 3 }, /* SPI0_SOMI */ + { pinmux(7), 1, 4 }, /* SPI0_SIMO */ + { pinmux(7), 1, 6 } /* SPI0_CLK */ +}; + +const struct pinmux_config spi0_pins_scs0[] = { + { pinmux(7), 1, 7 } /* SPI0_SCS[0] */ +}; + +const struct pinmux_config spi0_pins_ena[] = { + { pinmux(7), 1, 5 } /* SPI0_ENA */ +}; + +/* NAND pin muxer settings */ +const struct pinmux_config emifa_pins_cs0[] = { + { pinmux(18), 1, 2 } /* EMA_CS[0] */ +}; + +const struct pinmux_config emifa_pins_cs2[] = { + { pinmux(18), 1, 3 } /* EMA_CS[2] */ +}; + +const struct pinmux_config emifa_pins_cs3[] = { + { pinmux(18), 1, 4 } /* EMA_CS[3] */ +}; + +#ifdef CONFIG_USE_NAND +const struct pinmux_config emifa_pins[] = { + { pinmux(13), 1, 6 }, /* EMA_D[0] */ + { pinmux(13), 1, 7 }, /* EMA_D[1] */ + { pinmux(14), 1, 0 }, /* EMA_D[2] */ + { pinmux(14), 1, 1 }, /* EMA_D[3] */ + { pinmux(14), 1, 2 }, /* EMA_D[4] */ + { pinmux(14), 1, 3 }, /* EMA_D[5] */ + { pinmux(14), 1, 4 }, /* EMA_D[6] */ + { pinmux(14), 1, 5 }, /* EMA_D[7] */ + { pinmux(14), 1, 6 }, /* EMA_D[8] */ + { pinmux(14), 1, 7 }, /* EMA_D[9] */ + { pinmux(15), 1, 0 }, /* EMA_D[10] */ + { pinmux(15), 1, 1 }, /* EMA_D[11] */ + { pinmux(15), 1, 2 }, /* EMA_D[12] */ + { pinmux(15), 1, 3 }, /* EMA_D[13] */ + { pinmux(15), 1, 4 }, /* EMA_D[14] */ + { pinmux(15), 1, 5 }, /* EMA_D[15] */ + { pinmux(15), 1, 6 }, /* EMA_A[0] */ + { pinmux(15), 1, 7 }, /* EMA_A[1] */ + { pinmux(16), 1, 0 }, /* EMA_A[2] */ + { pinmux(16), 1, 1 }, /* EMA_A[3] */ + { pinmux(16), 1, 2 }, /* EMA_A[4] */ + { pinmux(16), 1, 3 }, /* EMA_A[5] */ + { pinmux(16), 1, 4 }, /* EMA_A[6] */ + { pinmux(16), 1, 5 }, /* EMA_A[7] */ + { pinmux(16), 1, 6 }, /* EMA_A[8] */ + { pinmux(16), 1, 7 }, /* EMA_A[9] */ + { pinmux(17), 1, 0 }, /* EMA_A[10] */ + { pinmux(17), 1, 1 }, /* EMA_A[11] */ + { pinmux(17), 1, 2 }, /* EMA_A[12] */ + { pinmux(17), 1, 3 }, /* EMA_BA[1] */ + { pinmux(17), 1, 4 }, /* EMA_BA[0] */ + { pinmux(17), 1, 5 }, /* EMA_CLK */ + { pinmux(17), 1, 6 }, /* EMA_SDCKE */ + { pinmux(17), 1, 7 }, /* EMA_CAS */ + { pinmux(18), 1, 0 }, /* EMA_CAS */ + { pinmux(18), 1, 1 }, /* EMA_WE */ + { pinmux(18), 1, 5 }, /* EMA_OE */ + { pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */ + { pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */ + { pinmux(10), 1, 0 } /* Tristate */ +}; +#endif + +/* EMAC PHY interface pins */ +const struct pinmux_config emac_pins_rmii[] = { + { pinmux(10), 2, 1 }, /* RMII_TXD[0] */ + { pinmux(10), 2, 2 }, /* RMII_TXD[1] */ + { pinmux(10), 2, 3 }, /* RMII_TXEN */ + { pinmux(10), 2, 4 }, /* RMII_CRS_DV */ + { pinmux(10), 2, 5 }, /* RMII_RXD[0] */ + { pinmux(10), 2, 6 }, /* RMII_RXD[1] */ + { pinmux(10), 2, 7 } /* RMII_RXER */ +}; + +const struct pinmux_config emac_pins_mdio[] = { + { pinmux(11), 2, 0 }, /* MDIO_CLK */ + { pinmux(11), 2, 1 } /* MDIO_D */ +}; + +const struct pinmux_config emac_pins_rmii_clk_source[] = { + { pinmux(9), 0, 5 } /* ref.clk from external source */ +}; + +/* UART2 pin muxer settings */ +const struct pinmux_config uart2_pins_txrx[] = { + { pinmux(8), 2, 7 }, /* UART2_RXD */ + { pinmux(9), 2, 0 } /* UART2_TXD */ +}; + +/* I2C0 pin muxer settings */ +const struct pinmux_config i2c0_pins[] = { + { pinmux(8), 2, 3 }, /* I2C0_SDA */ + { pinmux(8), 2, 4 } /* I2C0_SCL */ +}; + +/* USB0_DRVVBUS pin muxer settings */ +const struct pinmux_config usb_pins[] = { + { pinmux(9), 1, 1 } /* USB0_DRVVBUS */ +}; + +#ifdef CONFIG_DAVINCI_MMC +/* MMC0 pin muxer settings */ +const struct pinmux_config mmc0_pins_8bit[] = { + { pinmux(15), 2, 7 }, /* MMCSD0_CLK */ + { pinmux(16), 2, 0 }, /* MMCSD0_CMD */ + { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */ + { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */ + { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */ + { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */ + { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */ + { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */ + { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */ + { pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */ + /* DA830 supports 8-bit mode */ +}; +#endif diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h index a851f1f..beaf0d6 100644 --- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -22,8 +22,14 @@ #define __ASM_ARCH_PINMUX_DEFS_H #include <asm/arch/davinci_misc.h> +#include <config.h> -/* SPI pin muxer settings */ +/* SPI0 pin muxer settings */ +extern const struct pinmux_config spi0_pins_base[3]; +extern const struct pinmux_config spi0_pins_scs0[1]; +extern const struct pinmux_config spi0_pins_ena[1]; + +/* SPI1 pin muxer settings */ extern const struct pinmux_config spi1_pins_base[3]; extern const struct pinmux_config spi1_pins_scs0[1]; @@ -35,6 +41,7 @@ extern const struct pinmux_config uart2_pins_rtscts[2]; /* EMAC pin muxer settings*/ extern const struct pinmux_config emac_pins_rmii[7]; +extern const struct pinmux_config emac_pins_rmii_clk_source[1]; extern const struct pinmux_config emac_pins_mii[15]; extern const struct pinmux_config emac_pins_mdio[2]; @@ -43,13 +50,19 @@ extern const struct pinmux_config i2c0_pins[2]; extern const struct pinmux_config i2c1_pins[2]; /* EMIFA pin muxer settings */ +extern const struct pinmux_config emifa_pins[40]; +extern const struct pinmux_config emifa_pins_cs0[1]; extern const struct pinmux_config emifa_pins_cs2[1]; extern const struct pinmux_config emifa_pins_cs3[1]; extern const struct pinmux_config emifa_pins_cs4[1]; extern const struct pinmux_config emifa_pins_nand[12]; extern const struct pinmux_config emifa_pins_nor[43]; +/* USB pin mux setting */ +extern const struct pinmux_config usb_pins[1]; + /* MMC pin muxer settings */ +extern const struct pinmux_config mmc0_pins_8bit[10]; extern const struct pinmux_config mmc0_pins[6]; #endif diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index bf014ae..a4e9254 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -39,6 +39,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/emif_defs.h> #include <asm/arch/emac_defs.h> +#include <asm/arch/pinmux_defs.h> #include <asm/io.h> #include <nand.h> #include <asm/arch/nand_defs.h> @@ -51,148 +52,30 @@ DECLARE_GLOBAL_DATA_PTR; -/* SPI0 pin muxer settings */ -static const struct pinmux_config spi0_pins[] = { - { pinmux(7), 1, 3 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(7), 1, 6 }, - { pinmux(7), 1, 7 } -}; - -/* EMIF-A bus pins for 8-bit NAND support on CS3 */ -static const struct pinmux_config emifa_nand_pins[] = { - { pinmux(13), 1, 6 }, - { pinmux(13), 1, 7 }, - { pinmux(14), 1, 0 }, - { pinmux(14), 1, 1 }, - { pinmux(14), 1, 2 }, - { pinmux(14), 1, 3 }, - { pinmux(14), 1, 4 }, - { pinmux(14), 1, 5 }, - { pinmux(15), 1, 7 }, - { pinmux(16), 1, 0 }, - { pinmux(18), 1, 1 }, - { pinmux(18), 1, 4 }, - { pinmux(18), 1, 5 }, -}; - -/* EMAC PHY interface pins */ -static const struct pinmux_config emac_pins[] = { - { pinmux(9), 0, 5 }, - { pinmux(10), 2, 1 }, - { pinmux(10), 2, 2 }, - { pinmux(10), 2, 3 }, - { pinmux(10), 2, 4 }, - { pinmux(10), 2, 5 }, - { pinmux(10), 2, 6 }, - { pinmux(10), 2, 7 }, - { pinmux(11), 2, 0 }, - { pinmux(11), 2, 1 }, -}; - -/* UART pin muxer settings */ -static const struct pinmux_config uart_pins[] = { - { pinmux(8), 2, 7 }, - { pinmux(9), 2, 0 } -}; - -/* I2C pin muxer settings */ -static const struct pinmux_config i2c_pins[] = { - { pinmux(8), 2, 3 }, - { pinmux(8), 2, 4 } -}; - -#ifdef CONFIG_USE_NAND -/* NAND pin muxer settings */ -const struct pinmux_config aemif_pins[] = { - { pinmux(13), 1, 6 }, - { pinmux(13), 1, 7 }, - { pinmux(14), 1, 0 }, - { pinmux(14), 1, 1 }, - { pinmux(14), 1, 2 }, - { pinmux(14), 1, 3 }, - { pinmux(14), 1, 4 }, - { pinmux(14), 1, 5 }, - { pinmux(14), 1, 6 }, - { pinmux(14), 1, 7 }, - { pinmux(15), 1, 0 }, - { pinmux(15), 1, 1 }, - { pinmux(15), 1, 2 }, - { pinmux(15), 1, 3 }, - { pinmux(15), 1, 4 }, - { pinmux(15), 1, 5 }, - { pinmux(15), 1, 6 }, - { pinmux(15), 1, 7 }, - { pinmux(16), 1, 0 }, - { pinmux(16), 1, 1 }, - { pinmux(16), 1, 2 }, - { pinmux(16), 1, 3 }, - { pinmux(16), 1, 4 }, - { pinmux(16), 1, 5 }, - { pinmux(16), 1, 6 }, - { pinmux(16), 1, 7 }, - { pinmux(17), 1, 0 }, - { pinmux(17), 1, 1 }, - { pinmux(17), 1, 2 }, - { pinmux(17), 1, 3 }, - { pinmux(17), 1, 4 }, - { pinmux(17), 1, 5 }, - { pinmux(17), 1, 6 }, - { pinmux(17), 1, 7 }, - { pinmux(18), 1, 0 }, - { pinmux(18), 1, 1 }, - { pinmux(18), 1, 2 }, - { pinmux(18), 1, 3 }, - { pinmux(18), 1, 4 }, - { pinmux(18), 1, 5 }, - { pinmux(18), 1, 6 }, - { pinmux(18), 1, 7 }, - { pinmux(10), 1, 0 } -}; -#endif - - -/* USB0_DRVVBUS pin muxer settings */ -static const struct pinmux_config usb_pins[] = { - { pinmux(9), 1, 1 } -}; - -#ifdef CONFIG_DAVINCI_MMC -/* MMC0 pin muxer settings */ -const struct pinmux_config mmc0_pins[] = { - { pinmux(15), 2, 7 }, /* MMCSD0_CLK */ - { pinmux(16), 2, 0 }, /* MMCSD0_CMD */ - { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */ - { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */ - { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */ - { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */ - { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */ - { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */ - { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */ - { pinmux(14), 2, 5 }, /* MMCSD0_DAT_7 */ - /* DA830 supports 8-bit mode */ -}; -#endif - static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_SPI_FLASH - PINMUX_ITEM(spi0_pins), + PINMUX_ITEM(spi0_pins_base), + PINMUX_ITEM(spi0_pins_scs0), + PINMUX_ITEM(spi0_pins_ena), #endif - PINMUX_ITEM(uart_pins), - PINMUX_ITEM(i2c_pins), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(i2c0_pins), #ifdef CONFIG_USB_DA8XX PINMUX_ITEM(usb_pins), #endif #ifdef CONFIG_USE_NAND - PINMUX_ITEM(emifa_nand_pins), - PINMUX_ITEM(aemif_pins), + PINMUX_ITEM(emifa_pins), + PINMUX_ITEM(emifa_pins_cs0), + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_cs3), #endif #if defined(CONFIG_DRIVER_TI_EMAC) - PINMUX_ITEM(emac_pins), + PINMUX_ITEM(emac_pins_rmii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(emac_pins_rmii_clk_source), #endif #ifdef CONFIG_DAVINCI_MMC - PINMUX_ITEM(mmc0_pins), + PINMUX_ITEM(mmc0_pins_8bit) #endif }; diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 28995a0..00e92a6 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -36,6 +36,7 @@ #define CONFIG_MACH_DAVINCI_DA830_EVM #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA830 /* TI DA830 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -- 1.7.4.1

3 3

[U-Boot] [u-boot] spi/arm-pl022: Add support for ARM PL022 spi controller
by Armando Visconti 05 Jun '13

05 Jun '13

This patch adds the support for the ARM PL022 SPI controller for the standard variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO. Signed-off-by: Armando Visconti <armando.visconti(a)st.com> Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> --- This driver has been tested on the ST SPEAr1340 evaluation board. Patch has just been rebased on http://git.denx.de/u-boot-spi.git master branch and can be cleanly applied there. Armando drivers/spi/Makefile | 1 + drivers/spi/pl022_spi.c | 308 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 309 insertions(+) create mode 100644 drivers/spi/pl022_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d08609e..b6443b1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o +COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c new file mode 100644 index 0000000..3ea769a --- /dev/null +++ b/drivers/spi/pl022_spi.c @@ -0,0 +1,308 @@ +/* + * (C) Copyright 2012 + * Armando Visconti, ST Microelectronics, armando.visconti(a)st.com. + * + * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c + * by Atmel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* SSP registers mapping */ +#define SSP_CR0 0x000 +#define SSP_CR1 0x004 +#define SSP_DR 0x008 +#define SSP_SR 0x00C +#define SSP_CPSR 0x010 +#define SSP_IMSC 0x014 +#define SSP_RIS 0x018 +#define SSP_MIS 0x01C +#define SSP_ICR 0x020 +#define SSP_DMACR 0x024 +#define SSP_ITCR 0x080 +#define SSP_ITIP 0x084 +#define SSP_ITOP 0x088 +#define SSP_TDR 0x08C + +#define SSP_PID0 0xFE0 +#define SSP_PID1 0xFE4 +#define SSP_PID2 0xFE8 +#define SSP_PID3 0xFEC + +#define SSP_CID0 0xFF0 +#define SSP_CID1 0xFF4 +#define SSP_CID2 0xFF8 +#define SSP_CID3 0xFFC + +/* SSP Control Register 0 - SSP_CR0 */ +#define SSP_CR0_SPO (0x1 << 6) +#define SSP_CR0_SPH (0x1 << 7) +#define SSP_CR0_8BIT_MODE (0x07) +#define SSP_SCR_MAX (0xFF) +#define SSP_SCR_SHFT 8 + +/* SSP Control Register 0 - SSP_CR1 */ +#define SSP_CR1_MASK_SSE (0x1 << 1) + +#define SSP_CPSR_MAX (0xFE) + +/* SSP Status Register - SSP_SR */ +#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */ +#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */ +#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */ +#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */ +#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ + +struct pl022_spi_slave { + struct spi_slave slave; + void *regs; + unsigned int freq; +}; + +static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave) +{ + return container_of(slave, struct pl022_spi_slave, slave); +} + +/* + * Following three functions should be provided by the + * board support package. + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) + __attribute__((weak, alias("__spi_cs_is_valid"))); +void spi_cs_activate(struct spi_slave *slave) + __attribute__((weak, alias("__spi_cs_activate"))); +void spi_cs_deactivate(struct spi_slave *slave) + __attribute__((weak, alias("__spi_cs_deactivate"))); + +int __spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void __spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void __spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_init() +{ + /* do nothing */ +} + +/* + * ARM PL022 exists in different 'flavors'. + * This drivers currently support the standard variant (0x00041022), that has a + * 16bit wide and 8 locations deep TX/RX FIFO. + */ +static int pl022_is_supported(struct pl022_spi_slave *ps) +{ + /* PL022 version is 0x00041022 */ + if ((readw(ps->regs + SSP_PID0) == 0x22) && + (readw(ps->regs + SSP_PID1) == 0x10) && + ((readw(ps->regs + SSP_PID2) & 0xf) == 0x04) && + (readw(ps->regs + SSP_PID3) == 0x00)) + return 1; + + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct pl022_spi_slave *ps; + u16 scr = 1, prescaler, cr0 = 0, cpsr = 0; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ps = malloc(sizeof(*ps)); + if (!ps) + return NULL; + + ps->slave.bus = bus; + ps->slave.cs = cs; + ps->freq = max_hz; + + switch (bus) { + case 0: + ps->regs = (void *)CONFIG_SYS_SPI_BASE; + break; +#ifdef CONFIG_SYS_SPI_BASE1 + case 1: + ps->regs = (void *)CONFIG_SYS_SPI_BASE1; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE2 + case 2: + ps->regs = (void *)CONFIG_SYS_SPI_BASE2; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE3 + case 3: + ps->regs = (void *)CONFIG_SYS_SPI_BASE3; + break; +#endif + default: + free(ps); + return NULL; + } + + /* Check the PL022 version */ + if (!pl022_is_supported(ps)) { + free(ps); + return NULL; + } + + /* Set requested polarity and 8bit mode */ + cr0 = SSP_CR0_8BIT_MODE; + cr0 |= (mode & SPI_CPHA) ? SSP_CR0_SPH : 0; + cr0 |= (mode & SPI_CPOL) ? SSP_CR0_SPO : 0; + + writew(cr0, ps->regs + SSP_CR0); + + /* Program the SSPClk frequency */ + prescaler = CONFIG_SYS_SPI_CLK / ps->freq; + + if (prescaler <= 0xFF) + cpsr = prescaler; + else { + for (scr = 1; scr <= SSP_SCR_MAX; scr++) { + if (!(prescaler % scr)) { + cpsr = prescaler / scr; + if (cpsr <= SSP_CPSR_MAX) + break; + } + } + + if (scr > SSP_SCR_MAX) { + scr = SSP_SCR_MAX; + cpsr = prescaler / scr; + cpsr &= SSP_CPSR_MAX; + } + } + + if (cpsr & 0x1) + cpsr++; + + writew(cpsr, ps->regs + SSP_CPSR); + cr0 = readw(ps->regs + SSP_CR0); + writew(cr0 | (scr - 1) << SSP_SCR_SHFT, ps->regs + SSP_CR0); + + return &ps->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + + free(ps); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + + /* Enable the SPI hardware */ + writew(readw(ps->regs + SSP_CR1) | SSP_CR1_MASK_SSE, + ps->regs + SSP_CR1); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + + /* Disable the SPI hardware */ + writew(0x0, ps->regs + SSP_CR1); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + u32 len_tx = 0, len_rx = 0, len; + u32 ret = 0; + const u8 *txp = dout; + u8 *rxp = din, value; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * TODO: The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + ret = -1; + + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (len_tx < len) { + if (readw(ps->regs + SSP_SR) & SSP_SR_MASK_TNF) { + value = (txp != NULL) ? *txp++ : 0; + writew(value, ps->regs + SSP_DR); + len_tx++; + } + + if (readw(ps->regs + SSP_SR) & SSP_SR_MASK_RNE) { + value = readw(ps->regs + SSP_DR); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + + while (len_rx < len_tx) { + if (readw(ps->regs + SSP_SR) & SSP_SR_MASK_RNE) { + value = readw(ps->regs + SSP_DR); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} -- 1.7.11.7

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[U-Boot] [PATCH v2] arm: dra7xx: Update the EXTRA_ENV_SETTINGS
by Dan Murphy 05 Jun '13

05 Jun '13

Update the EXTRA_ENV_SETTING for the dra7xx. The console needs to be set to ttyO0 and the findfdt needs to be updated to load the dra7xx-evm.dtb file. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- v2 - Updated with side bar maintainer comments. include/configs/omap5_common.h | 12 ++++++++++-- 1 files changed, 10 insertions(+), 2 deletions(-) diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index deb5e9f..c5061dd 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -142,9 +142,15 @@ #define PARTS_DEFAULT #endif +#ifdef CONFIG_DRA7XX +#define CONFIG_CONSOLE_DEV "ttyO0" +#else +#define CONFIG_CONSOLE_DEV "ttyO2" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ + "console=" CONFIG_CONSOLE_DEV ",115200n8\0" \ "fdt_high=0xffffffff\0" \ "fdtaddr=0x80f80000\0" \ "bootpart=0:2\0" \ @@ -174,7 +180,9 @@ "bootz ${loadaddr} - ${fdtaddr}\0" \ "findfdt="\ "if test $board_name = omap5_uevm; then " \ - "setenv fdtfile omap5-uevm.dtb; fi;\0 " \ + "setenv fdtfile omap5-uevm.dtb; fi; " \ + "if test $board_name = dra7xx; then " \ + "setenv fdtfile dra7-evm.dtb; fi;\0 " \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ #define CONFIG_BOOTCOMMAND \ -- 1.7.5.4

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