June 2013 - U-Boot

[U-Boot] [PATCH 0/2] fix displaying IRQ stack info
by Masahiro Yamada 12 Jun '13

12 Jun '13

These series of patches fix the location of displaying IRQ stack infomation. Because ARM architecture supports generic_board, I separated my commit into 2 patches. The first one fix arch/arm/lib/board.c The second one fix common/board_f.c and common/board_r.c Masahiro Yamada (2): arm: fix displaying IRQ stack info common: arm: fix displaying IRQ stack info arch/arm/lib/board.c | 10 ++++++---- common/board_f.c | 4 ---- common/board_r.c | 10 ++++++++++ 3 files changed, 16 insertions(+), 8 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH v5] arm: dra7xx: Update the EXTRA_ENV_SETTINGS
by Dan Murphy 12 Jun '13

12 Jun '13

Update the EXTRA_ENV_SETTING for the dra7xx. The console needs to be set to ttyO0 and the findfdt needs to be updated to load the dra7xx-evm.dtb file. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- v5 - Fixed by adding the \0 to terminate the macro - http://patchwork.ozlabs.org/patch/249528/ v4 - Remove check for undefined fdtfile and save for another patch - http://patchwork.ozlabs.org/patch/249084/ v3 - Updated based on comments - http://patchwork.ozlabs.org/patch/248687/ v2 - Updated with side bar maintainer comments. include/configs/dra7xx_evm.h | 2 ++ include/configs/omap5_common.h | 6 ++++-- include/configs/omap5_uevm.h | 1 + 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 28a306b..2db0fbd 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -35,4 +35,6 @@ #define CONFIG_DRA7XX /* in a TI DRA7XX core */ #define CONFIG_SYS_PROMPT "DRA752 EVM # " +#define CONSOLEDEV "ttyO0" + #endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index deb5e9f..7ae546d 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -144,7 +144,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ + "console=" CONSOLEDEV ",115200n8\0" \ "fdt_high=0xffffffff\0" \ "fdtaddr=0x80f80000\0" \ "bootpart=0:2\0" \ @@ -174,7 +174,9 @@ "bootz ${loadaddr} - ${fdtaddr}\0" \ "findfdt="\ "if test $board_name = omap5_uevm; then " \ - "setenv fdtfile omap5-uevm.dtb; fi;\0 " \ + "setenv fdtfile omap5-uevm.dtb; fi; " \ + "if test $board_name = dra7xx; then " \ + "setenv fdtfile dra7-evm.dtb; fi;\0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 9e0339b..f2cbb02 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -55,6 +55,7 @@ #define CONFIG_CMD_PART #define CONFIG_SYS_PROMPT "OMAP5430 EVM # " +#define CONSOLEDEV "ttyO2" #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 #endif /* __CONFIG_OMAP5_EVM_H */ -- 1.7.5.4

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[U-Boot] [u-boot V4] spi/arm-pl022: Add support for ARM PL022 spi controller
by Armando Visconti 12 Jun '13

12 Jun '13

This patch adds the support for the ARM PL022 SPI controller for the standard variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO. Signed-off-by: Armando Visconti <armando.visconti(a)st.com> Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> Acked-by: Stefan Roese <sr(a)denx.de> --- v3->v4 Just removed all warnings when running checkpatch. Didn't find Jagan's feedback... So, pls, let me know if we need to change anything else... Armando drivers/spi/Makefile | 1 + drivers/spi/pl022_spi.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 311 insertions(+) create mode 100644 drivers/spi/pl022_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d08609e..b6443b1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o +COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c new file mode 100644 index 0000000..8a8b9ab --- /dev/null +++ b/drivers/spi/pl022_spi.c @@ -0,0 +1,310 @@ +/* + * (C) Copyright 2012 + * Armando Visconti, ST Microelectronics, armando.visconti(a)st.com. + * + * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c + * by Atmel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* SSP registers mapping */ +struct pl022 { + u32 ssp_cr0; /* 0x000 */ + u32 ssp_cr1; /* 0x004 */ + u32 ssp_dr; /* 0x008 */ + u32 ssp_sr; /* 0x00c */ + u32 ssp_cpsr; /* 0x010 */ + u32 ssp_imsc; /* 0x014 */ + u32 ssp_ris; /* 0x018 */ + u32 ssp_mis; /* 0x01c */ + u32 ssp_icr; /* 0x020 */ + u32 ssp_dmacr; /* 0x024 */ + u8 reserved_1[0x080 - 0x028]; + u32 ssp_itcr; /* 0x080 */ + u32 ssp_itip; /* 0x084 */ + u32 ssp_itop; /* 0x088 */ + u32 ssp_tdr; /* 0x08c */ + u8 reserved_2[0xFE0 - 0x090]; + u32 ssp_pid0; /* 0xfe0 */ + u32 ssp_pid1; /* 0xfe4 */ + u32 ssp_pid2; /* 0xfe8 */ + u32 ssp_pid3; /* 0xfec */ + u32 ssp_cid0; /* 0xff0 */ + u32 ssp_cid1; /* 0xff4 */ + u32 ssp_cid2; /* 0xff8 */ + u32 ssp_cid3; /* 0xffc */ +}; + +/* SSP Control Register 0 - SSP_CR0 */ +#define SSP_CR0_SPO (0x1 << 6) +#define SSP_CR0_SPH (0x1 << 7) +#define SSP_CR0_8BIT_MODE (0x07) +#define SSP_SCR_MAX (0xFF) +#define SSP_SCR_SHFT 8 + +/* SSP Control Register 0 - SSP_CR1 */ +#define SSP_CR1_MASK_SSE (0x1 << 1) + +#define SSP_CPSR_MAX (0xFE) + +/* SSP Status Register - SSP_SR */ +#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */ +#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */ +#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */ +#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */ +#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ + +struct pl022_spi_slave { + struct spi_slave slave; + void *regs; + unsigned int freq; +}; + +static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave) +{ + return container_of(slave, struct pl022_spi_slave, slave); +} + +/* + * Following three functions should be provided by the + * board support package. + */ +int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void __weak spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void __weak spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_init(void) +{ + /* do nothing */ +} + +/* + * ARM PL022 exists in different 'flavors'. + * This drivers currently support the standard variant (0x00041022), that has a + * 16bit wide and 8 locations deep TX/RX FIFO. + */ +static int pl022_is_supported(struct pl022_spi_slave *ps) +{ + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* PL022 version is 0x00041022 */ + if ((readl(&pl022->ssp_pid0) == 0x22) && + (readl(&pl022->ssp_pid1) == 0x10) && + ((readl(&pl022->ssp_pid2) & 0xf) == 0x04) && + (readl(&pl022->ssp_pid3) == 0x00)) + return 1; + + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct pl022_spi_slave *ps; + struct pl022 *pl022; + u16 scr = 1, prescaler, cr0 = 0, cpsr = 0; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ps = malloc(sizeof(*ps)); + if (!ps) + return NULL; + + ps->slave.bus = bus; + ps->slave.cs = cs; + ps->freq = max_hz; + + switch (bus) { + case 0: + ps->regs = (void *)CONFIG_SYS_SPI_BASE; + break; +#ifdef CONFIG_SYS_SPI_BASE1 + case 1: + ps->regs = (void *)CONFIG_SYS_SPI_BASE1; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE2 + case 2: + ps->regs = (void *)CONFIG_SYS_SPI_BASE2; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE3 + case 3: + ps->regs = (void *)CONFIG_SYS_SPI_BASE3; + break; +#endif + default: + free(ps); + return NULL; + } + + pl022 = (struct pl022 *)ps->regs; + + /* Check the PL022 version */ + if (!pl022_is_supported(ps)) { + free(ps); + return NULL; + } + + /* Set requested polarity and 8bit mode */ + cr0 = SSP_CR0_8BIT_MODE; + cr0 |= (mode & SPI_CPHA) ? SSP_CR0_SPH : 0; + cr0 |= (mode & SPI_CPOL) ? SSP_CR0_SPO : 0; + + writel(cr0, &pl022->ssp_cr0); + + /* Program the SSPClk frequency */ + prescaler = CONFIG_SYS_SPI_CLK / ps->freq; + + if (prescaler <= 0xFF) { + cpsr = prescaler; + } else { + for (scr = 1; scr <= SSP_SCR_MAX; scr++) { + if (!(prescaler % scr)) { + cpsr = prescaler / scr; + if (cpsr <= SSP_CPSR_MAX) + break; + } + } + + if (scr > SSP_SCR_MAX) { + scr = SSP_SCR_MAX; + cpsr = prescaler / scr; + cpsr &= SSP_CPSR_MAX; + } + } + + if (cpsr & 0x1) + cpsr++; + + writel(cpsr, &pl022->ssp_cpsr); + cr0 = readl(&pl022->ssp_cr0); + writel(cr0 | (scr - 1) << SSP_SCR_SHFT, &pl022->ssp_cr0); + + return &ps->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + + free(ps); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Enable the SPI hardware */ + setbits_le32(&pl022->ssp_cr1, SSP_CR1_MASK_SSE); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Disable the SPI hardware */ + writel(0x0, &pl022->ssp_cr1); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + u32 len_tx = 0, len_rx = 0, len; + u32 ret = 0; + const u8 *txp = dout; + u8 *rxp = din, value; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * TODO: The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + ret = -1; + + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (len_tx < len) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_TNF) { + value = (txp != NULL) ? *txp++ : 0; + writel(value, &pl022->ssp_dr); + len_tx++; + } + + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + + while (len_rx < len_tx) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} -- 1.7.11.7

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[U-Boot] [u-boot V5] spi: arm-pl022: Add support for ARM PL022 spi controller
by Armando Visconti 12 Jun '13

12 Jun '13

This patch adds the support for the ARM PL022 SPI controller for the standard variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO. Signed-off-by: Armando Visconti <armando.visconti(a)st.com> Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> Acked-by: Stefan Roese <sr(a)denx.de> --- V4->V5: Changed the commit message to a more standard format. Armando drivers/spi/Makefile | 1 + drivers/spi/pl022_spi.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 311 insertions(+) create mode 100644 drivers/spi/pl022_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d08609e..b6443b1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o +COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c new file mode 100644 index 0000000..8a8b9ab --- /dev/null +++ b/drivers/spi/pl022_spi.c @@ -0,0 +1,310 @@ +/* + * (C) Copyright 2012 + * Armando Visconti, ST Microelectronics, armando.visconti(a)st.com. + * + * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c + * by Atmel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* SSP registers mapping */ +struct pl022 { + u32 ssp_cr0; /* 0x000 */ + u32 ssp_cr1; /* 0x004 */ + u32 ssp_dr; /* 0x008 */ + u32 ssp_sr; /* 0x00c */ + u32 ssp_cpsr; /* 0x010 */ + u32 ssp_imsc; /* 0x014 */ + u32 ssp_ris; /* 0x018 */ + u32 ssp_mis; /* 0x01c */ + u32 ssp_icr; /* 0x020 */ + u32 ssp_dmacr; /* 0x024 */ + u8 reserved_1[0x080 - 0x028]; + u32 ssp_itcr; /* 0x080 */ + u32 ssp_itip; /* 0x084 */ + u32 ssp_itop; /* 0x088 */ + u32 ssp_tdr; /* 0x08c */ + u8 reserved_2[0xFE0 - 0x090]; + u32 ssp_pid0; /* 0xfe0 */ + u32 ssp_pid1; /* 0xfe4 */ + u32 ssp_pid2; /* 0xfe8 */ + u32 ssp_pid3; /* 0xfec */ + u32 ssp_cid0; /* 0xff0 */ + u32 ssp_cid1; /* 0xff4 */ + u32 ssp_cid2; /* 0xff8 */ + u32 ssp_cid3; /* 0xffc */ +}; + +/* SSP Control Register 0 - SSP_CR0 */ +#define SSP_CR0_SPO (0x1 << 6) +#define SSP_CR0_SPH (0x1 << 7) +#define SSP_CR0_8BIT_MODE (0x07) +#define SSP_SCR_MAX (0xFF) +#define SSP_SCR_SHFT 8 + +/* SSP Control Register 0 - SSP_CR1 */ +#define SSP_CR1_MASK_SSE (0x1 << 1) + +#define SSP_CPSR_MAX (0xFE) + +/* SSP Status Register - SSP_SR */ +#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */ +#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */ +#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */ +#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */ +#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ + +struct pl022_spi_slave { + struct spi_slave slave; + void *regs; + unsigned int freq; +}; + +static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave) +{ + return container_of(slave, struct pl022_spi_slave, slave); +} + +/* + * Following three functions should be provided by the + * board support package. + */ +int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void __weak spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void __weak spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_init(void) +{ + /* do nothing */ +} + +/* + * ARM PL022 exists in different 'flavors'. + * This drivers currently support the standard variant (0x00041022), that has a + * 16bit wide and 8 locations deep TX/RX FIFO. + */ +static int pl022_is_supported(struct pl022_spi_slave *ps) +{ + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* PL022 version is 0x00041022 */ + if ((readl(&pl022->ssp_pid0) == 0x22) && + (readl(&pl022->ssp_pid1) == 0x10) && + ((readl(&pl022->ssp_pid2) & 0xf) == 0x04) && + (readl(&pl022->ssp_pid3) == 0x00)) + return 1; + + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct pl022_spi_slave *ps; + struct pl022 *pl022; + u16 scr = 1, prescaler, cr0 = 0, cpsr = 0; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ps = malloc(sizeof(*ps)); + if (!ps) + return NULL; + + ps->slave.bus = bus; + ps->slave.cs = cs; + ps->freq = max_hz; + + switch (bus) { + case 0: + ps->regs = (void *)CONFIG_SYS_SPI_BASE; + break; +#ifdef CONFIG_SYS_SPI_BASE1 + case 1: + ps->regs = (void *)CONFIG_SYS_SPI_BASE1; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE2 + case 2: + ps->regs = (void *)CONFIG_SYS_SPI_BASE2; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE3 + case 3: + ps->regs = (void *)CONFIG_SYS_SPI_BASE3; + break; +#endif + default: + free(ps); + return NULL; + } + + pl022 = (struct pl022 *)ps->regs; + + /* Check the PL022 version */ + if (!pl022_is_supported(ps)) { + free(ps); + return NULL; + } + + /* Set requested polarity and 8bit mode */ + cr0 = SSP_CR0_8BIT_MODE; + cr0 |= (mode & SPI_CPHA) ? SSP_CR0_SPH : 0; + cr0 |= (mode & SPI_CPOL) ? SSP_CR0_SPO : 0; + + writel(cr0, &pl022->ssp_cr0); + + /* Program the SSPClk frequency */ + prescaler = CONFIG_SYS_SPI_CLK / ps->freq; + + if (prescaler <= 0xFF) { + cpsr = prescaler; + } else { + for (scr = 1; scr <= SSP_SCR_MAX; scr++) { + if (!(prescaler % scr)) { + cpsr = prescaler / scr; + if (cpsr <= SSP_CPSR_MAX) + break; + } + } + + if (scr > SSP_SCR_MAX) { + scr = SSP_SCR_MAX; + cpsr = prescaler / scr; + cpsr &= SSP_CPSR_MAX; + } + } + + if (cpsr & 0x1) + cpsr++; + + writel(cpsr, &pl022->ssp_cpsr); + cr0 = readl(&pl022->ssp_cr0); + writel(cr0 | (scr - 1) << SSP_SCR_SHFT, &pl022->ssp_cr0); + + return &ps->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + + free(ps); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Enable the SPI hardware */ + setbits_le32(&pl022->ssp_cr1, SSP_CR1_MASK_SSE); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Disable the SPI hardware */ + writel(0x0, &pl022->ssp_cr1); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + u32 len_tx = 0, len_rx = 0, len; + u32 ret = 0; + const u8 *txp = dout; + u8 *rxp = din, value; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * TODO: The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + ret = -1; + + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (len_tx < len) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_TNF) { + value = (txp != NULL) ? *txp++ : 0; + writel(value, &pl022->ssp_dr); + len_tx++; + } + + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + + while (len_rx < len_tx) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} -- 1.7.11.7

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[U-Boot] [PATCH v4] sf: Add bank addr code in CONFIG_SPI_FLASH_BAR
by Jagannadha Sutradharudu Teki 12 Jun '13

12 Jun '13

Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the size for existing boards which has < 16Mbytes SPI flashes. It's upto user which has provision to use the bank addr code for flashes which has > 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- Changes for v4: - init bank_curr to 0 for < 16Mbytes if CONFIG_SPI_FLASH_BAR defined Changes for v4: - none Changes for v4: - none README | 5 ++++ drivers/mtd/spi/spi_flash.c | 45 +++++++++++++++++++++++------------- drivers/mtd/spi/spi_flash_internal.h | 14 ++++++----- include/spi_flash.h | 3 ++- 4 files changed, 44 insertions(+), 23 deletions(-) diff --git a/README b/README index 3d81092..a2b956e 100644 --- a/README +++ b/README @@ -2489,6 +2489,11 @@ CBFS (Coreboot Filesystem) support Define this option to include a destructive SPI flash test ('sf test'). + CONFIG_SPI_FLASH_BAR Ban/Extended Addr Reg + + Define this option to use the Bank addr/Extended addr + support on SPI flashes which has size > 16Mbytes. + - SystemACE Support: CONFIG_SYSTEMACE diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 40c0389..2307f2b 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -74,7 +74,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, unsigned long page_addr, byte_addr, page_size; size_t chunk_len, actual; int ret; - u8 cmd[4], bank_sel; + u8 cmd[4]; page_size = flash->page_size; @@ -86,6 +86,9 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, cmd[0] = CMD_PAGE_PROGRAM; for (actual = 0; actual < len; actual += chunk_len) { +#ifdef CONFIG_SPI_FLASH_BAR + u8 bank_sel; + bank_sel = offset / SPI_FLASH_16MB_BOUN; ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); @@ -93,7 +96,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, debug("SF: fail to set bank%d\n", bank_sel); return ret; } - +#endif page_addr = offset / page_size; byte_addr = offset % page_size; chunk_len = min(len - actual, page_size - byte_addr); @@ -162,6 +165,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, cmd[4] = 0x00; while (len) { +#ifdef CONFIG_SPI_FLASH_BAR bank_sel = offset / SPI_FLASH_16MB_BOUN; ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); @@ -169,7 +173,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, debug("SF: fail to set bank%d\n", bank_sel); return ret; } - +#endif remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset); if (len < remain_len) read_len = len; @@ -240,7 +244,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) { u32 erase_size; int ret; - u8 cmd[4], bank_sel; + u8 cmd[4]; erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { @@ -260,6 +264,9 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) cmd[0] = CMD_ERASE_64K; while (len) { +#ifdef CONFIG_SPI_FLASH_BAR + u8 bank_sel; + bank_sel = offset / SPI_FLASH_16MB_BOUN; ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); @@ -267,7 +274,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) debug("SF: fail to set bank%d\n", bank_sel); return ret; } - +#endif spi_flash_addr(offset, cmd); debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], @@ -321,6 +328,7 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) return 0; } +#ifdef CONFIG_SPI_FLASH_BAR int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { u8 cmd, idcode0; @@ -379,6 +387,7 @@ int spi_flash_cmd_bankaddr_read(struct spi_flash *flash, void *data) return spi_flash_read_common(flash, &cmd, 1, data, 1); } +#endif #ifdef CONFIG_OF_CONTROL int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) @@ -481,7 +490,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash = NULL; int ret, i, shift; u8 idcode[IDCODE_LEN], *idp; - u8 curr_bank = 0; spi = spi_setup_slave(bus, cs, max_hz, spi_mode); if (!spi) { @@ -525,9 +533,24 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, goto err_manufacturer_probe; } +#ifdef CONFIG_SPI_FLASH_BAR + u8 curr_bank = 0; + /* store the manuf id, for performing specific flash ops */ flash->idcode0 = *idp; + /* read bankaddr, which bank the flash is operated currently */ + if (flash->size > SPI_FLASH_16MB_BOUN) { + if (spi_flash_cmd_bankaddr_read(flash, &curr_bank)) { + debug("SF: fail to read bank addr register\n"); + goto err_manufacturer_probe; + } + flash->bank_curr = curr_bank; + } else { + flash->bank_curr = curr_bank; + } +#endif + #ifdef CONFIG_OF_CONTROL if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { debug("SF: FDT decode error\n"); @@ -541,16 +564,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, printf(", mapped at %p", flash->memory_map); puts("\n"); - if (flash->size > SPI_FLASH_16MB_BOUN) { - if (spi_flash_cmd_bankaddr_read(flash, &curr_bank)) { - debug("SF: fail to read bank addr register\n"); - goto err_manufacturer_probe; - } - flash->bank_curr = curr_bank; - } else { - flash->bank_curr = curr_bank; - } - spi_release_bus(spi); return flash; diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 455dc02..12d49a8 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -12,8 +12,6 @@ #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) -#define SPI_FLASH_16MB_BOUN 0x1000000 - /* Common commands */ #define CMD_READ_ID 0x9f @@ -30,11 +28,15 @@ #define CMD_ERASE_64K 0xd8 #define CMD_ERASE_CHIP 0xc7 +#define SPI_FLASH_16MB_BOUN 0x1000000 + /* Bank addr acess commands */ -#define CMD_BANKADDR_BRWR 0x17 -#define CMD_BANKADDR_BRRD 0x16 -#define CMD_EXTNADDR_WREAR 0xC5 -#define CMD_EXTNADDR_RDEAR 0xC8 +#ifdef CONFIG_SPI_FLASH_BAR +# define CMD_BANKADDR_BRWR 0x17 +# define CMD_BANKADDR_BRRD 0x16 +# define CMD_EXTNADDR_WREAR 0xC5 +# define CMD_EXTNADDR_RDEAR 0xC8 +#endif /* Common status */ #define STATUS_WIP 0x01 diff --git a/include/spi_flash.h b/include/spi_flash.h index acac17a..5de50c2 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -38,11 +38,12 @@ struct spi_flash { u32 page_size; /* Erase (sector) size */ u32 sector_size; +#ifdef CONFIG_SPI_FLASH_BAR /* ID code0 */ u8 idcode0; /* Current flash bank */ u8 bank_curr; - +#endif void *memory_map; /* Address of read-only SPI flash access */ int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); -- 1.8.3

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[U-Boot] [PATCH] fdt: remove unaligned access in fdt_fixup_ethernet()
by Stephen Warren 12 Jun '13

12 Jun '13

Some ARM compilers may emit code that makes unaligned accesses when faced with constructs such as: char mac[16] = "ethaddr"; Replace this with a strcpy() call instead to avoid this. strcpy() is used here, rather than replacing all usage of the mac variable with the string itself, since the loop itself sprintf()s to the variable each iteration, so strcpy() is doing basically the same thing. Reported-by: Florian Meier Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- common/fdt_support.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 812acb4..89e7883 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -454,7 +454,7 @@ void fdt_fixup_ethernet(void *fdt) { int node, i, j; char enet[16], *tmp, *end; - char mac[16] = "ethaddr"; + char mac[16]; const char *path; unsigned char mac_addr[6]; @@ -463,6 +463,7 @@ void fdt_fixup_ethernet(void *fdt) return; i = 0; + strcpy(mac, "ethaddr"); while ((tmp = getenv(mac)) != NULL) { sprintf(enet, "ethernet%d", i); path = fdt_getprop(fdt, node, enet, NULL); -- 1.7.10.4

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[U-Boot] : sf: spansion: Add support for S25FL128S
by Jagan Teki 12 Jun '13

12 Jun '13

Hi, Request for few details here. I am not understanding why this is applied on tree, [even i din't see the applied note on mailing list, may be i am missing] I was asked Xie Xiaobo to send v2 fo updating the name to - .name = "S25FL129P_64K/S25FL128S", + .name = "S25FL129P_64K/S25FL128S_64K", Even i sent a patch on be of Xie Xiaobo http://patchwork.ozlabs.org/patch/247607/ Any comments, was the notion i used on patch was wrong. -- Thanks, Jagan.

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[U-Boot] [PATCH RFC] NET: TSEC: make PHY addresses software configurable
by Wolfgang Denk 12 Jun '13

12 Jun '13

Some systems use a SoM (system on module) in such a way that the PHY addresses depend on the carrier board used, or even on the geographic position of the SoM on the carrier board. This patch adds support for runtime assignment of the PHY addresses for the TSEC ports through environment variables "tsec_1_phy_addr", "tsec_2_phy_addr", ... Signed-off-by: Wolfgang Denk <wd(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> --- This is a RFC patch to have a base for discussing the approach. There are a few things I dislike - all comments welcome: - It would be nice if there was a generic approach that works for all types of network interfaces instead of only TSEC ports, but I could not find a good generic place for such a hook. - I'm not sure if "tsec_1_phy_addr" etc. is a good name ;-) - Maybe there is another way to address this issue? I can't believe we're the first to run into this type of problem? drivers/net/tsec.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index f5e314b..e86e48c 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -567,6 +567,26 @@ static phy_interface_t tsec_get_interface(struct tsec_private *priv) return PHY_INTERFACE_MODE_MII; } +static void update_phy_addr(int phy_nr) +{ + char *str, buf[32]; + + sprintf(buf, "tsec_%d_phy_addr", phy_nr); + + str = getenv(buf); + + if (str) { + ulong val = simple_strtoul(str, NULL, 16); + + debug("FIX TSEC%d_PHY_ADDR : %d => %ld\n", + phy_nr, tsec_info[phy_nr].phyaddr, val); + + tsec_info[phy_nr].phyaddr = val; + } else { + debug("FIX TSEC%d_PHY_ADDR : %s not set\n", + phy_nr, buf); + } +} /* Discover which PHY is attached to the device, and configure it * properly. If the PHY is not recognized, then return 0 @@ -671,7 +691,10 @@ int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) int i; int ret, count = 0; + debug ("tsec_eth_init()\n"); for (i = 0; i < num; i++) { + update_phy_addr(i); + ret = tsec_initialize(bis, &tsecs[i]); if (ret > 0) count += ret; -- 1.7.11.7

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[U-Boot] [PATCH] ppc: ppmc7xx: Fix possible out-of-bound access
by Marek Vasut 11 Jun '13

11 Jun '13

The flash_info_t->start[] field is limited in size by CONFIG_SYS_MAX_FLASH_SECT macro, which is set to 19 for this board in the board config file. If we inspect the board/ppmc7xx/flash.c closely, especially the flash_get_size() function, we can notice the "switch ((long)flashtest)" at around line 80 having a few results which will set flash_info_t->sector_count to value higher than 19, for example "case AMD_ID_LV640U" will set it to 128. Notice that right underneath, iteration over flash_info_t->start[] happens and the upper bound for the interation is flash_info_t->sector_count. Now if the sector_count is 128 as it is for the AMD_ID_LV640U case, but the CONFIG_SYS_MAX_FLASH_SECT limiting the start[] is only 19, an access past the start[] array much happen. Moreover, during this iteration, the field is written to, so memory corruption is inevitable. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Richard Danter <richard.danter(a)windriver.com> --- include/configs/ppmc7xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index 5cd6609..d4d7f9e 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -233,7 +233,7 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 250000 #define CONFIG_SYS_FLASH_WRITE_TOUT 5000 #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 19 +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* -- 1.7.10.4

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[U-Boot] [PATCH v3 0/6] Update gdsys ppc4xx-based boards
by dirk.eibach＠gdsys.cc 11 Jun '13

11 Jun '13

From: Dirk Eibach <dirk.eibach(a)gdsys.cc> This series depends on the "Bring in new I2C framework" series by Heiko Schocher. Patch "powerpc/ppc4xx: Add bitbang i2c interface for gdsys boards" was dropped in favor of using the new framework. Changes in v3: - adapt to "powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA" - squashed with "Add generic accessor functions for gdsys FPGA" - squashed with "powerpc/ppc4xx: Increase timeout for gdsys mclink bus startup" - squashed with powerpc/ppc4xx: Fixup phy erratum on gdsys iocon hardware - strictly replace base address plus offset with proper C structs Changes in v2: - fpga_state has been moved to arch_global_data - include cmd_fpgad in iocon - move cmd_fpgad to common and fix whitespace issues - update email account - use multibus soft-i2c in iocon Dirk Eibach (6): powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA powerpc/ppc4xx: Add gdsys mclink interface powerpc/ppc4xx: Add fpgad command for dumping gdsys fpga registers powerpc/ppc4xx: Support gdsys multichannel iocon hardware powerpc/ppc4xx: Consider gdsys FPGA OSD size powerpc/ppc4xx: Remove CONFIG_SYS_FLASH_PROTECTION from gdsys boards board/gdsys/405ep/405ep.c | 20 +- board/gdsys/405ep/dlvision-10g.c | 32 ++- board/gdsys/405ep/io.c | 30 ++- board/gdsys/405ep/iocon.c | 485 +++++++++++++++++++++++++++++++++++---- board/gdsys/405ep/neo.c | 27 ++- board/gdsys/405ex/405ex.c | 20 +- board/gdsys/405ex/io64.c | 48 ++-- board/gdsys/common/Makefile | 2 +- board/gdsys/common/mclink.c | 153 ++++++++++++ board/gdsys/common/mclink.h | 31 +++ board/gdsys/common/osd.c | 118 ++++++---- common/Makefile | 1 + common/cmd_fpgad.c | 100 ++++++++ include/configs/dlvision-10g.h | 7 +- include/configs/dlvision.h | 3 +- include/configs/io.h | 6 +- include/configs/io64.h | 4 + include/configs/iocon.h | 60 ++++- include/configs/neo.h | 6 +- include/gdsys_fpga.h | 58 ++++- 20 files changed, 1040 insertions(+), 171 deletions(-) create mode 100644 board/gdsys/common/mclink.c create mode 100644 board/gdsys/common/mclink.h create mode 100644 common/cmd_fpgad.c -- 1.8.3

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