April 2013 - U-Boot

[U-Boot] [PATCH] nitrogen6x: Setup CCM_CCOSR register
by Fabio Estevam 25 Apr '13

25 Apr '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> CKO1 drives sgtl5000 codec clock on nitrogen boards and wandboard. Doing this setup in the bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c from the mainline kernel. Also, according to Eric Nelson: "enabling the clock <in the bootloader> will remove squeal after an ungraceful reboot (watchdog) if hooked up to speakers." Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- arch/arm/include/asm/arch-mx6/crm_regs.h | 1 + board/boundary/nitrogen6x/clocks.cfg | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 7676457..ca732af 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -20,6 +20,7 @@ #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ +#define CCM_CCOSR 0x020c4060 #define CCM_CCGR0 0x020C4068 #define CCM_CCGR1 0x020C406c #define CCM_CCGR2 0x020C4070 diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg index e7d1f86..0a3b47b 100644 --- a/board/boundary/nitrogen6x/clocks.cfg +++ b/board/boundary/nitrogen6x/clocks.cfg @@ -44,3 +44,14 @@ DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4, MX6_IOMUXC_GPR6, 0x007F007F DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb -- 1.7.9.5

2 1

[U-Boot] [PATCH] imx: mx6q_4x_mt41j128.cfg: Setup CCM_CCOSR register
by Fabio Estevam 25 Apr '13

25 Apr '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> Setup CCM_CCOSR register to provide a CKO1 clock frequency of 16.5 MHz. CKO1 drives sgtl5000 codec clock on mx6qsabrelite and doing this setup in the bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c from the mainline kernel. mx6q_4x_mt41j128.cfg is also used by mx6qsabresd, and it is safe to use it for this board as well. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index f4cae5e..4661775 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -172,3 +172,14 @@ DATA 4 0x020e0010 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb -- 1.7.9.5

4 5

[U-Boot] [PATCH] mx35 iomux: correct input select register index
by Philip Paeps 25 Apr '13

25 Apr '13

Prior to this fix, calls to mxc_iomux_set_input() for registers after MUX_IN_GPIO2_IN_19 would write to the wrong registers, possibly resulting in unexpected behaviour. Signed-off-by: Philip Paeps <philip(a)paeps.cx> --- arch/arm/include/asm/arch-mx35/iomux.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx35/iomux.h b/arch/arm/include/asm/arch-mx35/iomux.h index 52c15bc..7f17ed6 100644 --- a/arch/arm/include/asm/arch-mx35/iomux.h +++ b/arch/arm/include/asm/arch-mx35/iomux.h @@ -141,6 +141,7 @@ typedef enum iomux_input_select { MUX_IN_GPIO2_IN_17, MUX_IN_GPIO2_IN_18, MUX_IN_GPIO2_IN_19, + MUX_IN_GPIO2_IN_1, MUX_IN_GPIO2_IN_20, MUX_IN_GPIO2_IN_21, MUX_IN_GPIO2_IN_22, -- 1.7.2.5

2 1

[U-Boot] [PATCH] arm: imx: Codingstyle enhancement of include/asm/arch-mx6/crm_regs.h
by Stefan Roese 25 Apr '13

25 Apr '13

Add spaces before and after "<<". Please note that I intentionally didn't wrap the > 80 lines for the sake of better readability. Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/arm/include/asm/arch-mx6/crm_regs.h | 172 +++++++++++++++---------------- 1 file changed, 86 insertions(+), 86 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index cf5c694..87e0889 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -415,183 +415,183 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR_CG_MASK 3 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 -#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) +#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 -#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) +#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 -#define MXC_CCM_CCGR0_APBHDMA_MASK (3<<MXC_CCM_CCGR0_APBHDMA_OFFSET) +#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) #define MXC_CCM_CCGR0_ASRC_OFFSET 6 -#define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET) +#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 -#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) +#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 -#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) +#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 -#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) +#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) #define MXC_CCM_CCGR0_CAN1_OFFSET 14 -#define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET) +#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 -#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) +#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) #define MXC_CCM_CCGR0_CAN2_OFFSET 18 -#define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET) +#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 -#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) +#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 -#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) +#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 -#define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET) +#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 -#define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET) +#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) #define MXC_CCM_CCGR0_DTCP_OFFSET 28 -#define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET) +#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 -#define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 -#define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 -#define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 -#define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 -#define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET) +#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 -#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) +#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 -#define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET) +#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 -#define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET) +#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 -#define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET) +#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 -#define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET) +#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 -#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) +#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 -#define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET) +#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 -#define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET) +#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 -#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) +#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 -#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) +#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 -#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) +#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 -#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) +#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 -#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) +#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 -#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) +#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 -#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) +#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 -#define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET) +#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 -#define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET) +#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 -#define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET) +#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 -#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) +#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 -#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) +#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 -#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET) +#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 -#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) +#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 -#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) +#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 -#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET) +#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 -#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) +#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 -#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) +#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 -#define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET) +#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 -#define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET) +#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 -#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) +#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) #define MXC_CCM_CCGR3_MLB_OFFSET 18 -#define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET) +#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 -#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 -#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) +#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 -#define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET) +#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 -#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) +#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) #define MXC_CCM_CCGR4_PCIE_OFFSET 0 -#define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET) +#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 -#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) +#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 -#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) +#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 -#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) +#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) #define MXC_CCM_CCGR4_PWM1_OFFSET 16 -#define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET) +#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) #define MXC_CCM_CCGR4_PWM2_OFFSET 18 -#define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET) +#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) #define MXC_CCM_CCGR4_PWM3_OFFSET 20 -#define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET) +#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) #define MXC_CCM_CCGR4_PWM4_OFFSET 22 -#define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET) +#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 -#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 -#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) +#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) #define MXC_CCM_CCGR5_ROM_OFFSET 0 -#define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET) +#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) #define MXC_CCM_CCGR5_SATA_OFFSET 4 -#define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET) +#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) #define MXC_CCM_CCGR5_SDMA_OFFSET 6 -#define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET) +#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) #define MXC_CCM_CCGR5_SPBA_OFFSET 12 -#define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET) +#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 -#define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET) +#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) #define MXC_CCM_CCGR5_SSI1_OFFSET 18 -#define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET) +#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) #define MXC_CCM_CCGR5_SSI2_OFFSET 20 -#define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET) +#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) #define MXC_CCM_CCGR5_SSI3_OFFSET 22 -#define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET) +#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) #define MXC_CCM_CCGR5_UART_OFFSET 24 -#define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET) +#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 -#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET) +#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 -#define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET) +#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 -#define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET) +#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 -#define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET) +#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 -#define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET) +#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 -#define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET) +#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 -#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET) +#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 -#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET) +#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 #define BP_ANADIG_PLL_SYS_RSVD0 20 -- 1.8.2.1

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[U-Boot] Power Savings on ARM/OMAP4
by Michael Cashwell 25 Apr '13

25 Apr '13

Greetings, I've been playing with controlling a bq2415x battery charger chip on I2C on a custom OMAP4 board. In USB/OTG charging mode the code currently monitors the charger chip in a loop to which I added a msleep(2000) call. I did that thinking that since battery parameters don't change very fast I'd slow things down and save power. But it doesn't seem to. That delay ends up in an ARMv7/omap-common/timer.c function that is a full-speed read/compare loop targeting a CPU timer register. It seems to leave precious little USB power for the battery. Is there any way to make use of the ARM idle instruction and, I assume, an interrupt from a timer? I don't want anything complicated but *something* that would help reduce the power being wasted by the _udelay() routine would be nice. If there is I'd like to find a way to apply it to the interactive console so sitting at a u-boot prompt (instead of in _udelay()) would also not suck power like crazy. Any ideas? Is there some solution perhaps on one of the other architectures? -Mike

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[U-Boot] [PATCH 0/11] Update gdsys ppc4xx-based boards
by Dirk Eibach 25 Apr '13

25 Apr '13

Dirk Eibach (11): powerpc/ppc4xx: Add generic accessor functions for gdsys FPGA powerpc/ppc4xx: Add gdsys mclink interface powerpc/ppc4xx: Add fpgad command for dumping gdsys fpga registers powerpc/ppc4xx: Add bitbang i2c interface for gdsys boards powerpc/ppc4xx: Use generic FPGA accessors in gdsys common code powerpc/ppc4xx: Support gdsys multichannel iocon hardware powerpc/ppc4xx: Use generic FPGA accessors on all gdsys 405ep/ex boards powerpc/ppc4xx: Fixup phy erratum on gdsys iocon hardware powerpc/ppc4xx: Increase timeout for gdsys mclink bus startup powerpc/ppc4xx: Consider gdsys FPGA OSD size powerpc/ppc4xx: Remove CONFIG_SYS_FLASH_PROTECTION from gdsys boards board/gdsys/405ep/405ep.c | 12 +- board/gdsys/405ep/dlvision-10g.c | 20 +- board/gdsys/405ep/io.c | 20 +- board/gdsys/405ep/iocon.c | 467 ++++++++++++++++++++++++++++++++++---- board/gdsys/405ep/neo.c | 17 +- board/gdsys/405ex/405ex.c | 14 +- board/gdsys/405ex/io64.c | 38 ++-- board/gdsys/common/Makefile | 2 +- board/gdsys/common/bb_i2c.c | 304 +++++++++++++++++++++++++ board/gdsys/common/bb_i2c.h | 76 +++++++ board/gdsys/common/cmd_fpga.c | 94 ++++++++ board/gdsys/common/mclink.c | 142 ++++++++++++ board/gdsys/common/mclink.h | 31 +++ board/gdsys/common/osd.c | 105 +++++---- include/configs/dlvision-10g.h | 3 +- include/configs/dlvision.h | 3 +- include/configs/io.h | 3 +- include/configs/iocon.h | 43 ++-- include/configs/neo.h | 3 +- include/gdsys_fpga.h | 20 +- 20 files changed, 1249 insertions(+), 168 deletions(-) create mode 100644 board/gdsys/common/bb_i2c.c create mode 100644 board/gdsys/common/bb_i2c.h create mode 100644 board/gdsys/common/cmd_fpga.c create mode 100644 board/gdsys/common/mclink.c create mode 100644 board/gdsys/common/mclink.h -- 1.7.10.4

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[U-Boot] [PATCH 0/3] usb: ss: Fixes for super speed framework
by Vivek Gautam 25 Apr '13

25 Apr '13

This patch series fixes changes for Super speed framework which got pulled-in 'u-boot-usb/next'. First patch fixes Port Status and Port feature macro constants, then next patch parallelizes power-cycling of power on root-hub ports. 3rd patch in this series also sync the min3/max3 definitions with Linux kernel. Based on u-boot-usb/next branch with following patch reverted: usb: hub: Reset only usb 2.0 ports Vivek Gautam (3): usb: hub: Parallelize power-cycling of root-hub ports usb: fix: Fixing Port status and feature number constants usb: common: Use a global definition for 'min3' common/usb_hub.c | 63 ++++++++++++++++++++++++++++-------------- drivers/usb/host/ehci-hcd.c | 10 ------- include/common.h | 25 ++++++++++++++--- include/usb_defs.h | 39 +++++++++++++++----------- 4 files changed, 86 insertions(+), 51 deletions(-) -- 1.7.6.5

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[U-Boot] CONFIG_ARM_ERRATA_7XXXX question
by TigerLiu＠viatech.com.cn 25 Apr '13

25 Apr '13

Hi, experts: I found some macro definitions, such as: #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 So, my question is: Where do i get these errata descriptions? Are there related to specific ARM SOC Vendors? Or just ARM Core's common errata? Best wishes,

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[U-Boot] CONFIG_ARM_ERRATA_7XXXX question
by TigerLiu＠viatech.com.cn 25 Apr '13

25 Apr '13

Hi, experts: I found some macro definitions, such as: #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 So, my question is: Where do i get these errata descriptions? Are there related to specific ARM SOC Vendors? Or just ARM Core's common errata? Best wishes,

1 0

[U-Boot] [PATCH RESEND] arm: bootm: call udc_disable() before booting linux
by Mike Dunn 25 Apr '13

25 Apr '13

On the pxa270, if the udc device is not disabled before jumping to linux, the device fails to initialize in linux because it was left in a running state, and the linux driver assumes that it is in a disabled state. Signed-off-by: Mike Dunn <mikedunn(a)newsguy.com> --- Arguably, this is a bug in the linux driver, but it seemed pretty simple and benign to just disable it in u-boot. I'll also send a patch to upstream kernel to fix its udc driver. arch/arm/include/asm/bootm.h | 1 + arch/arm/lib/bootm.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h index db2ff94..68189cc 100644 --- a/arch/arm/include/asm/bootm.h +++ b/arch/arm/include/asm/bootm.h @@ -21,6 +21,7 @@ #ifdef CONFIG_USB_DEVICE extern void udc_disconnect(void); +extern void udc_disable(void); #endif #endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index f3b30c5..6daa7bf 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -105,6 +105,7 @@ static void announce_and_cleanup(void) #ifdef CONFIG_USB_DEVICE udc_disconnect(); + udc_disable(); #endif cleanup_before_linux(); } -- 1.7.8.6

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