April 2013 - U-Boot

[U-Boot] [PATCH] exynos: change indentation of defines in cpu.h
by Minkyu Kang 04 Apr '13

04 Apr '13

Fix the indentation of some defines by tab. Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> --- arch/arm/include/asm/arch-exynos/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 2a20558..f76e489 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -93,9 +93,9 @@ #define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE /* EXYNOS5 Common*/ -- 1.7.9.5 -- Thanks, Minkyu Kang.

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[U-Boot] USB3.0 Interrupt transfer in u-boot
by Puneet Sharma 04 Apr '13

04 Apr '13

Hello, I want to test USB keyboard for XHCI in u-boot and to do that i need the Interrupt transfer code in XHCI controller driver in u-boot. If possible, can you help me to give that piece of code or can you help me to figure out in kernel where can i find it so that i can try to replicate it in u-boot and make it work. Thanks & Regards -- Puneet Sharma <puneet.sharma(a)moschip.com> The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system.

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[U-Boot] [PATCH 0/5] ARM: vexpress: add support for more core tiles
by Andre Przywara 04 Apr '13

04 Apr '13

This series adds support for the Cortex-A5 and Cortex-A15 core tiles for the ARM Versatile Express boards. The first three patches have been around for about one and a half years in the Linaro tree now, they refactor the A9 support and add support for A5. I kept the original commits and authors, just resolved some trivial merge conflicts and checkpatch complaints. Patch 4/5 adds support for the A15 core tile, this is actually the same as the A5 for now, but will be extended later. Patch 5/5 enables bootz and hush parser for all boards, just for convenience. Regards, Andre. -- Andre Przywara Linaro Virtualization Team

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[U-Boot] [PULL] : Please pull u-boot-imx
by Stefano Babic 04 Apr '13

04 Apr '13

Hi Albert, last iMX fixes for the release. Please pull from u-boot-imx, thanks. The following changes since commit b27673ccbd3d5435319b5c09c3e7061f559f925d: Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' (2013-03-15 20:50:43 +0100) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to d36b39bf0d1dbe4ef03f7fc1f20b2e52eb90acf5: spi: mxc_spi: Fix ECSPI reset handling (2013-04-04 10:23:09 +0200) ---------------------------------------------------------------- Abbas Raza (1): mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board Alexandre Pereira da Silva (1): mx23_olinuxino: Fix netboot console Benoît Thébaudeau (1): mx25pdk: Enable imxdi RTC Dirk Behme (1): spi: mxc_spi: Fix ECSPI reset handling Eric Nelson (2): i.MX6: Add hdmidet command to detect attached HDMI monitor i.MX6: mx6qsabrelite: discard override of CONFIG_ARP_TIMEOUT Fabio Estevam (10): mxs: spl_mem_init: Align DDR2 init with FSL bootlets source configs: mx28evk: Use single-line comments mx28evk: Disable CONFIG_CMD_I2C Add initial support for Wandboard dual lite and solo. mx28evk: Introduce a new target for saving env vars to NAND mx6qsabrelite: README: No need to pass 'u-boot.imx' mx6: Fix get_board_rev() for the mx6 solo case wandboard: Remove duplicate 'mmc dev' mx6qsabrelite: Remove duplicate 'mmc dev' wandboard: Remove CONFIG_SYS_FSL_USDHC_NUM Javier Martinez Canillas (1): i.MX6: mx6qsabrelite: README: don't pass chip-select to sf probe command Knut Wohlrab (1): imx-common: timer: fix 32-bit overflow Otavio Salvador (4): mx6qsabresd: Document the mapping of USDHC[2-4] mx6qsabresd: Fix card detection for invalid card id case mx6qsabre{sd,auto}: Add boot mode select mx23_olinuxino: Change definitions to use spaces instead of tabs MAINTAINERS | 1 + arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 18 +-- arch/arm/cpu/armv7/mx6/soc.c | 12 ++ arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/cmd_hdmidet.c | 37 +++++ arch/arm/imx-common/timer.c | 26 +-- arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 3 + board/boundary/nitrogen6x/nitrogen6x.c | 8 +- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 18 +++ board/freescale/mx6qsabrelite/README | 4 +- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 8 +- board/freescale/mx6qsabresd/mx6qsabresd.c | 48 ++++-- board/wandboard/Makefile | 29 ++++ board/wandboard/README | 40 +++++ board/wandboard/wandboard.c | 178 +++++++++++++++++++++ boards.cfg | 5 +- doc/README.mx28evk | 18 +++ drivers/mmc/fsl_esdhc.c | 7 + drivers/spi/mxc_spi.c | 8 +- include/configs/mx23_olinuxino.h | 162 +++++++++---------- include/configs/mx25pdk.h | 4 + include/configs/mx28evk.h | 92 ++++++----- include/configs/mx6qsabre_common.h | 2 + include/configs/mx6qsabrelite.h | 3 - include/configs/wandboard.h | 209 +++++++++++++++++++++++++ include/fsl_esdhc.h | 1 + 26 files changed, 757 insertions(+), 185 deletions(-) create mode 100644 arch/arm/imx-common/cmd_hdmidet.c create mode 100644 board/wandboard/Makefile create mode 100644 board/wandboard/README create mode 100644 board/wandboard/wandboard.c create mode 100644 include/configs/wandboard.h -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[U-Boot] [PATCH] spi: mxc_spi: Fix ECSPI reset handling
by Dirk Behme 04 Apr '13

04 Apr '13

Reviewing the ECSPI reset handling shows two issues: 1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg (ECSPIx_CONGREG) the i.MX6 technical reference manual states: -- cut -- ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block and resets the internal logic with the exception of the ECSPI_CONREG. -- cut -- Note the exception mentioned: The CONREG itself isn't reset. Fix this by manually writing the reset value 0 to the whole register. This sets the EN bit to zero, too (i.e. includes the old ~MXC_CSPICTRL_EN). 2. We want to reset the whole SPI block here. So it makes no sense to first read the old value of the CONREG and write it back, later. This will give us the old (historic/random) value of the CONREG back. And doesn't reset the CONREG. To get a clean CONREG after the reset of the block, too, don't use the old (historic/random) value of the CONREG while doing the reset. And read the clean CONREG after the reset. This was found while working on a SPI boot device where the i.MX6 boot ROM has already initialized the SPI block. The initialization by the boot ROM might be different to what the U-Boot driver wants to configure. I.e. we need a clean reset of SPI block, including the CONREG. Signed-off-by: Dirk Behme <dirk.behme(a)de.bosch.com> CC: Stefano Babic <sbabic(a)denx.de> CC: Fabio Estevam <fabio.estevam(a)freescale.com> --- drivers/spi/mxc_spi.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index d792d8d..cb48019 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -137,11 +137,11 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, return -1; } - reg_ctrl = reg_read(&regs->ctrl); - /* Reset spi */ - reg_write(&regs->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN)); - reg_write(&regs->ctrl, (reg_ctrl | MXC_CSPICTRL_EN)); + reg_write(&regs->ctrl, 0); + reg_write(&regs->ctrl, MXC_CSPICTRL_EN); + + reg_ctrl = reg_read(&regs->ctrl); /* * The following computation is taken directly from Freescale's code. -- 1.7.0.4

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[U-Boot] [PATCH V2] ARM: bcm2835: fix get_timer() to return ms
by Stephen Warren 04 Apr '13

04 Apr '13

Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer driver to conform to this. Have the timer implementation export a custom API get_timer_us() for use by the BCM2835 MMC API, which needs us resolution for a HW workaround. Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- v2: Export custom API get_timer_us() to allow the MMC driver to maintain its current workaround implementation. --- arch/arm/cpu/arm1176/bcm2835/timer.c | 14 +++++++++++--- arch/arm/include/asm/arch-bcm2835/timer.h | 2 ++ drivers/mmc/bcm2835_sdhci.c | 5 +++-- include/configs/rpi_b.h | 2 +- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c index d232d7e..2edd671 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/cpu/arm1176/bcm2835/timer.c @@ -23,7 +23,7 @@ int timer_init(void) return 0; } -ulong get_timer(ulong base) +ulong get_timer_us(ulong base) { struct bcm2835_timer_regs *regs = (struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR; @@ -31,6 +31,14 @@ ulong get_timer(ulong base) return readl(&regs->clo) - base; } +ulong get_timer(ulong base) +{ + ulong us = get_timer_us(0); + us /= (1000000 / CONFIG_SYS_HZ); + us -= base; + return us; +} + unsigned long long get_ticks(void) { return get_timer(0); @@ -46,10 +54,10 @@ void __udelay(unsigned long usec) ulong endtime; signed long diff; - endtime = get_timer(0) + usec; + endtime = get_timer_us(0) + usec; do { - ulong now = get_timer(0); + ulong now = get_timer_us(0); diff = endtime - now; } while (diff >= 0); } diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/include/asm/arch-bcm2835/timer.h index 30c70e0..c2001b6 100644 --- a/arch/arm/include/asm/arch-bcm2835/timer.h +++ b/arch/arm/include/asm/arch-bcm2835/timer.h @@ -34,4 +34,6 @@ struct bcm2835_timer_regs { #define BCM2835_TIMER_CS_M1 (1 << 1) #define BCM2835_TIMER_CS_M0 (1 << 0) +extern ulong get_timer_us(ulong base); + #endif diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index b0afc3c..54cfabf 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -39,6 +39,7 @@ #include <common.h> #include <malloc.h> #include <sdhci.h> +#include <asm/arch/timer.h> /* 400KHz is max freq for card ID etc. Use that as min */ #define MIN_FREQ 400000 @@ -67,11 +68,11 @@ static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val, * (Which is just as well - otherwise we'd have to nobble the DMA engine * too) */ - while (get_timer(bcm_host->last_write) < bcm_host->twoticks_delay) + while (get_timer_us(bcm_host->last_write) < bcm_host->twoticks_delay) ; writel(val, host->ioaddr + reg); - bcm_host->last_write = get_timer(0); + bcm_host->last_write = get_timer_us(0); } static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg) diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 3d55d36..c18b35b 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -31,7 +31,7 @@ #define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 /* Timer */ -#define CONFIG_SYS_HZ 1000000 +#define CONFIG_SYS_HZ 1000 /* Memory layout */ #define CONFIG_NR_DRAM_BANKS 1 -- 1.7.10.4

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[U-Boot] [PATCH] cfi_flash: Use uintptr_t for casts from u32 to void *
by Stefan Roese 04 Apr '13

04 Apr '13

This fixes this build warning: Configuring for qemu_mips64 - Board: qemu-mips64, Options: SYS_BIG_ENDIAN text data bss dec hex filename 215344 13082 218720 447146 6d2aa qemu_mips64/u-boot cfi_flash.c: In function 'flash_map': cfi_flash.c:217:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)ti.com> --- drivers/mtd/cfi_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 328c76d..cf10b0d 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -214,7 +214,7 @@ flash_map (flash_info_t * info, flash_sect_t sect, uint offset) unsigned int addr = (info->start[sect] + byte_offset); unsigned int mask = 0xffffffff << (info->portwidth - 1); - return (void *)(addr & mask); + return (void *)(uintptr_t)(addr & mask); } static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, -- 1.8.2

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[U-Boot] [PATCH] Tegra114: Initialize System Counter (TSC) with osc frequency
by Tom Warren 04 Apr '13

04 Apr '13

T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/cpu/tegra-common/clock.c | 3 +++ arch/arm/cpu/tegra114-common/clock.c | 22 ++++++++++++++++++ arch/arm/cpu/tegra20-common/clock.c | 4 ++++ arch/arm/cpu/tegra30-common/clock.c | 4 ++++ arch/arm/include/asm/arch-tegra/clock.h | 3 +++ arch/arm/include/asm/arch-tegra114/sysctr.h | 35 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + 7 files changed, 72 insertions(+) create mode 100644 arch/arm/include/asm/arch-tegra114/sysctr.h diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 49a0633..9156d00 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -557,4 +557,7 @@ void clock_init(void) debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); + + /* Do any special system timer/TSC setup */ + arch_timer_init(); } diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index 9b29ce1..5c4305a 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -19,6 +19,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/timer.h> @@ -653,3 +654,24 @@ void clock_early_init(void) writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); udelay(2); } + +void arch_timer_init(void) +{ + struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; + u32 freq, val; + + freq = clock_get_rate(CLOCK_ID_OSC); + debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + + /* ARM CNTFRQ */ + asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); + + /* Only T114 has the System Counter regs */ + debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); + writel(freq, &sysctr->cntfid0); + + val = readl(&sysctr->cntcr); + val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; + writel(val, &sysctr->cntcr); + debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); +} diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c index ec93894..4afb205 100644 --- a/arch/arm/cpu/tegra20-common/clock.c +++ b/arch/arm/cpu/tegra20-common/clock.c @@ -559,3 +559,7 @@ void clock_early_init(void) break; } } + +void arch_timer_init(void) +{ +} diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c index a93f2c9..74bd22b 100644 --- a/arch/arm/cpu/tegra30-common/clock.c +++ b/arch/arm/cpu/tegra30-common/clock.c @@ -616,3 +616,7 @@ void clock_early_init(void) break; } } + +void arch_timer_init(void) +{ +} diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c8677bd..c7a696c 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -317,4 +317,7 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ (id) < PERIPHC_COUNT) +/* SoC-specific TSC init */ +void arch_timer_init(void); + #endif /* _TEGRA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h new file mode 100644 index 0000000..c05e2c3 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/sysctr.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA114_SYSCTR_H_ +#define _TEGRA114_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA114_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index a3d12d6..5d426b5 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -18,6 +18,7 @@ #define _TEGRA114_H_ #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ #include <asm/arch-tegra/tegra.h> -- 1.8.1.5

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[U-Boot] [PATCH] Tegra: Fix MSELECT clock divisors for T30/T114.
by Tom Warren 04 Apr '13

04 Apr '13

A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/cpu/arm720t/tegra114/cpu.c | 10 ++++------ arch/arm/cpu/arm720t/tegra30/cpu.c | 4 ++-- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 6a94179..51ecff7 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -170,15 +170,13 @@ void t114_init_clocks(void) clock_set_enable(PERIPH_ID_MC1, 1); clock_set_enable(PERIPH_ID_DVFS, 1); - /* Switch MSELECT clock to PLLP (00) */ - clock_ll_set_source(PERIPH_ID_MSELECT, 0); - /* - * Clock divider request for 102MHz would setup MSELECT clock as - * 102MHz for PLLP base 408MHz + * Set MSELECT clock source as PLLP (00), and ask for a clock + * divider that would set the MSELECT clock at 102MHz for a + * PLLP base of 408MHz. */ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, - (NVBL_PLLP_KHZ/102000)); + CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index dedcdd9..e162357 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -110,8 +110,8 @@ void t30_init_clocks(void) reset_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); - /* Switch MSELECT clock to PLLP (00) */ - clock_ll_set_source(PERIPH_ID_MSELECT, 0); + /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */ + clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2); /* * Our high-level clock routines are not available prior to -- 1.8.1.5

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[U-Boot] [PATCH] patman: Ignore all Gerrit Commit-* tags
by Simon Glass 04 Apr '13

04 Apr '13

These tags are used by Gerrit, so let's ignore all of them. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- tools/patman/patchstream.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index 9d8a918..926b586 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -31,7 +31,7 @@ from series import Series # Tags that we detect and remove re_remove = re.compile('^BUG=|^TEST=|^BRANCH=|^Change-Id:|^Review URL:' - '|Reviewed-on:|Commit-Ready:') + '|Reviewed-on:|Commit-\w*:') # Lines which are allowed after a TEST= line re_allowed_after_test = re.compile('^Signed-off-by:') -- 1.8.1.3

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