April 2013 - U-Boot

[U-Boot] "No status update" errors in OMAP mmc_send_cmd()
by Michael Cashwell 10 May '13

10 May '13

Greetings, I've been fighting an odd problem with a custom OMAP4 board throwing MMC errors. It seems that a 4-bit-wide uSD card on MMC1 works but an 8-bit-wide eMMC part on MMC2 has problems. As sometimes happens, in trying to track down the problem the presence of a debugging printf() masked the error. Just now I've finally gotten a good trace on this. In drivers/mmc/omap_hsmmc.c near line 380, if I have: writel(cmd->cmdarg, &mmc_base->arg); writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); printf("%s : @ %p cmd 0x%08x arg 0x%08x\n", __func__, mmc_base, cmd->cmdidx, cmd->cmdarg); With or without that printf() the code fails when I select MMC2 (eMMC): u-boot # mmc dev 1 mmc_send_cmd : @ 480b4100 cmd 0x00000000 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x000001aa mmc_send_cmd : @ 480b4100 cmd 0x00000037 arg 0x00000000 mmc_send_cmd : timeout on cmd 55. No status update (base 480b4100) << 1s delay mmc_send_cmd : @ 480b4100 cmd 0x00000000 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000002 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000003 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000009 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x0000000d arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000007 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000006 arg 0x03b90100 mmc_send_cmd : @ 480b4100 cmd 0x0000000d arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000006 arg 0x03b70100 mmc_send_cmd : @ 480b4100 cmd 0x0000000d arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000010 arg 0x00000200 mmc_send_cmd : @ 480b4100 cmd 0x00000011 arg 0x00000000 mmc1(part 0) is current device If I instead put the printf() or a udelay(20) (anything less than 20 still failed) *between* the two writel() calls it works: u-boot # mmc dev 1 mmc_send_cmd : @ 480b4100 cmd 0x00000000 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x000001aa mmc_send_cmd : @ 480b4100 cmd 0x00000037 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000000 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000001 arg 0x40300080 mmc_send_cmd : @ 480b4100 cmd 0x00000002 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000003 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000009 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x0000000d arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000007 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000006 arg 0x03b90100 mmc_send_cmd : @ 480b4100 cmd 0x0000000d arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000006 arg 0x03b70100 mmc_send_cmd : @ 480b4100 cmd 0x0000000d arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000008 arg 0x00000000 mmc_send_cmd : @ 480b4100 cmd 0x00000010 arg 0x00000200 mmc_send_cmd : @ 480b4100 cmd 0x00000011 arg 0x00000000 mmc1(part 0) is current device So writing to the command register "too soon" after writing to the dependent data registers sometimes fails. Obviously a magic-number udelay() is a hack. I'm going to dive into the data sheet but wanted to ask here if this is familiar to anyone. Thanks, -Michael Cashwell

2 1

[U-Boot] [PATCH 1/1] OMAP4/5: I2C: New read/write/probe functions
by Lubomir Popov 09 May '13

09 May '13

These new functions are built for OMAP4 and OMAP5 only. The major improvement is that the new i2c_read fixes the inability to read correctly from certain types of I2C chips. - Rewritten i2c_read to operate correctly with all types of chips. - Optimized i2c_write. Both read/write functions try to identify unconfigured bus. - New i2c_probe performs write access vs read. Optionally selectable via CONFIG_I2C_PROBE_WRITE. - Driver supports up to I2C5 (OMAP5; I2C_BASE5 must be defined). Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- drivers/i2c/omap24xx_i2c.c | 332 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 315 insertions(+), 17 deletions(-) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 54e9b15..6890d3c 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -18,6 +18,14 @@ * * Adapted for OMAP2420 I2C, r-woodruff2(a)ti.com * + * Copyright (c) 2013 Lubomir Popov <lpopov(a)mm-sol.com>, MM Solutions + * New i2c_read, i2c_write and i2c_probe functions for OMAP4/5 only. + * - Rewritten i2c_read to operate correctly with all types of chips. + * - Optimized i2c_write. Both read/write functions try to identify + * unconfigured bus. + * - New i2c_probe performs write access vs read. Optionally selectable + * via CONFIG_I2C_PROBE_WRITE. + * - Driver supports up to I2C5 (OMAP5; I2C_BASE5 must be defined). */ #include <common.h> @@ -31,6 +39,12 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_TIMEOUT 1000 +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) +#define I2C_WAIT 200 /* Absolutely safe for status update at 100 kHz I2C */ +#else +#define I2C_WAIT 1000 +#endif + static int wait_for_bb(void); static u16 wait_for_pin(void); static void flush_fifo(void); @@ -150,6 +164,7 @@ void i2c_init(int speed, int slaveadd) bus_initialized[current_bus] = 1; } +#if !(defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)) static int i2c_read_byte(u8 devaddr, u16 regoffset, u8 alen, u8 *value) { int i2c_error = 0; @@ -231,6 +246,7 @@ read_exit: writew(0, &i2c_base->cnt); return i2c_error; } +#endif static void flush_fifo(void) { u16 stat; @@ -255,6 +271,52 @@ static void flush_fifo(void) } } +#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)) && \ + defined(CONFIG_I2C_PROBE_WRITE) +/* i2c_probe: Use write access. Allows to identify addresses that are + * write-only (like the config register of dual-port EEPROMs) + */ +int i2c_probe(uchar chip) +{ + u16 status; + int res = 1; /* default = fail */ + + if (chip == readw(&i2c_base->oa)) + return res; + + /* Wait until bus is free */ + if (wait_for_bb()) + return res; + + /* No data transfer, slave addr only */ + writew(0, &i2c_base->cnt); + /* set slave address */ + writew(chip, &i2c_base->sa); + /* stop bit needed here */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, &i2c_base->con); + + status = wait_for_pin(); + + if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) + goto pr_exit; /* If pads are not configured for I2C */ + + /* check for ACK (!NAK) */ + if (!(status & I2C_STAT_NACK)) { + res = 0; /* Device found */ + /* abort transfer (force idle state) */ + writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset cntrlr */ + udelay(1000); + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | + I2C_CON_STP, &i2c_base->con); /* STP */ + } +pr_exit: + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); + return res; +} +#else int i2c_probe(uchar chip) { u16 status; @@ -314,7 +376,132 @@ probe_exit: writew(0xFFFF, &i2c_base->stat); return res; } +#endif + +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) +/* i2c_read: Function now uses a single I2C read transaction with bulk transfer + * of the requested number of bytes (note that the 'i2c md' command + * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is + * defined in the board config header, this transaction shall be with + * Repeated Start (Sr) between the address and data phases; otherwise + * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). + * The address (reg offset) may be 0, 1 or 2 bytes long. + * Function now reads correctly from chips that return more than one + * byte of data per addressed register (like TI temperature sensors), + * or that do not need a register address at all (such as some clock + * distributors). + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i2c_error = 0; + u16 status; + + if (alen < 0) { + printf("I2C read: addr len < 0\n"); + return 1; + } + if (len < 0) { + printf("I2C read: data len < 0\n"); + return 1; + } + if (buffer == NULL) { + printf("I2C read: NULL pointer passed\n"); + return 1; + } + + if (alen > 2) { + printf("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > (1 << 16)) { + puts("I2C read: address out of range\n"); + return 1; + } + + /* Wait until bus not busy */ + if (wait_for_bb()) + return 1; + + /* Zero, one or two bytes reg address (offset) */ + writew(alen, &i2c_base->cnt); + /* Set slave address */ + writew(chip, &i2c_base->sa); + + if (alen) { + /* Must write reg offset first */ +#ifdef CONFIG_I2C_REPEATED_START + /* No stop bit, use Repeated Start (Sr) */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | + I2C_CON_TRX, &i2c_base->con); +#else + /* Stop - Start (P-S) */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | + I2C_CON_TRX, &i2c_base->con); +#endif + /* Send register offset */ + while (1) { + status = wait_for_pin(); + /* Try to identify bus that is not padconf'd for I2C */ + if (status == I2C_STAT_XRDY) { + i2c_error = 2; + printf("i2c_read: pads on bus %d probably not configured (status=0x%x)\n", + current_bus, status); + goto rd_exit; + } + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", + status); + goto rd_exit; + } + if (alen) { + if (status & I2C_STAT_XRDY) { + alen--; + /* Do we have to use byte access? */ + writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data); + writew(I2C_STAT_XRDY, &i2c_base->stat); + } + } + if (status & I2C_STAT_ARDY) { + writew(I2C_STAT_ARDY, &i2c_base->stat); + break; + } + } + } + /* Set slave address */ + writew(chip, &i2c_base->sa); + /* Read len bytes from slave */ + writew(len, &i2c_base->cnt); + /* Need stop bit here */ + writew(I2C_CON_EN | I2C_CON_MST | + I2C_CON_STT | I2C_CON_STP, + &i2c_base->con); + + /* Receive data */ + while (1) { + status = wait_for_pin(); + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + goto rd_exit; + } + if (status & I2C_STAT_RRDY) { + *buffer++ = readb(&i2c_base->data); + writew(I2C_STAT_RRDY, &i2c_base->stat); + } + if (status & I2C_STAT_ARDY) { + writew(I2C_STAT_ARDY, &i2c_base->stat); + break; + } + } +rd_exit: + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); + return i2c_error; +} +#else int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { int i; @@ -339,7 +526,109 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) return 0; } +#endif + +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) +/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i; + u16 status; + int i2c_error = 0; + + if (alen < 0) { + printf("I2C write: addr len < 0\n"); + return 1; + } + + if (len < 0) { + printf("I2C write: data len < 0\n"); + return 1; + } + + if (buffer == NULL) { + printf("I2C write: NULL pointer passed\n"); + return 1; + } + + if (alen > 2) { + printf("I2C write: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > (1 << 16)) { + printf("I2C write: address 0x%x + 0x%x out of range\n", + addr, len); + return 1; + } + + /* Wait until bus not busy */ + if (wait_for_bb()) + return 1; + + /* Start address phase - will write regoffset + len bytes data */ + writew(alen + len, &i2c_base->cnt); + /* Set slave address */ + writew(chip, &i2c_base->sa); + /* Stop bit needed here */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, &i2c_base->con); + while (alen) { + /* Must write reg offset (one or two bytes) */ + status = wait_for_pin(); + /* Try to identify bus that is not padconf'd for I2C */ + if (status == I2C_STAT_XRDY) { + i2c_error = 2; + printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", + current_bus, status); + goto wr_exit; + } + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", + status); + goto wr_exit; + } + if (status & I2C_STAT_XRDY) { + alen--; + writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data); + writew(I2C_STAT_XRDY, &i2c_base->stat); + } + else { + i2c_error = 1; + printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n", + status); + goto wr_exit; + } + } + /* Address phase is over, now write data */ + for (i = 0; i < len; i++) { + status = wait_for_pin(); + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + printf("i2c_write: error waiting for data ACK (status=0x%x)\n", + status); + goto wr_exit; + } + if (status & I2C_STAT_XRDY) { + writeb(buffer[i], &i2c_base->data); + writew(I2C_STAT_XRDY, &i2c_base->stat); + } + else { + i2c_error = 1; + printf("i2c_write: bus not ready for data Tx (i=%d)\n", i); + goto wr_exit; + } + } + +wr_exit: + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); + return i2c_error; +} +#else int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { int i; @@ -404,6 +693,7 @@ write_exit: writew(0xFFFF, &i2c_base->stat); return i2c_error; } +#endif static int wait_for_bb(void) { @@ -413,7 +703,7 @@ static int wait_for_bb(void) writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { writew(stat, &i2c_base->stat); - udelay(1000); + udelay(I2C_WAIT); } if (timeout <= 0) { @@ -431,7 +721,7 @@ static u16 wait_for_pin(void) int timeout = I2C_TIMEOUT; do { - udelay(1000); + udelay(I2C_WAIT); status = readw(&i2c_base->stat); } while (!(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | @@ -455,23 +745,31 @@ int i2c_set_bus_num(unsigned int bus) return -1; } -#if I2C_BUS_MAX == 4 - if (bus == 3) - i2c_base = (struct i2c *)I2C_BASE4; - else - if (bus == 2) - i2c_base = (struct i2c *)I2C_BASE3; - else + switch (bus) { + default: + bus = 0; /* Fall through */ + case 0: + i2c_base = (struct i2c *)I2C_BASE1; + break; + case 1: + i2c_base = (struct i2c *)I2C_BASE2; + break; +#if (I2C_BUS_MAX > 2) + case 2: + i2c_base = (struct i2c *)I2C_BASE3; + break; +#if (I2C_BUS_MAX > 3) + case 3: + i2c_base = (struct i2c *)I2C_BASE4; + break; +#if (I2C_BUS_MAX > 4) && defined(I2C_BASE5) + case 4: + i2c_base = (struct i2c *)I2C_BASE5; + break; #endif -#if I2C_BUS_MAX == 3 - if (bus == 2) - i2c_base = (struct i2c *)I2C_BASE3; - else #endif - if (bus == 1) - i2c_base = (struct i2c *)I2C_BASE2; - else - i2c_base = (struct i2c *)I2C_BASE1; +#endif + } current_bus = bus; -- 1.7.9.5

2 2

[U-Boot] [PATCH] EXYNOS: SPI: Support word transfers
by Rajeshwari Shinde 09 May '13

09 May '13

Since SPI register access is so expensive, it is worth transferring data a word at a time if we can. This complicates the driver unfortunately. Use the byte-swapping feature to avoid having to convert to/from big endian in software. This change increases speed from about 2MB/s to about 4.5MB/s. Based on "EXYNOS: SPI: Minimise access to SPI FIFO level" link: http://patchwork.ozlabs.org/patch/230034/ Signed-off-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> --- arch/arm/include/asm/arch-exynos/spi.h | 11 ++++- drivers/spi/exynos_spi.c | 77 +++++++++++++++++++++++++------ 2 files changed, 72 insertions(+), 16 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h index 7cab1e9..e67ad27 100644 --- a/arch/arm/include/asm/arch-exynos/spi.h +++ b/arch/arm/include/asm/arch-exynos/spi.h @@ -34,7 +34,7 @@ struct exynos_spi { unsigned int rx_data; /* 0x1c */ unsigned int pkt_cnt; /* 0x20 */ unsigned char reserved2[4]; - unsigned char reserved3[4]; + unsigned int swap_cfg; /* 0x28 */ unsigned int fb_clk; /* 0x2c */ unsigned char padding[0xffd0]; }; @@ -74,5 +74,14 @@ struct exynos_spi { /* Packet Count */ #define SPI_PACKET_CNT_EN (1 << 16) +/* Swap config */ +#define SPI_TX_SWAP_EN (1 << 0) +#define SPI_TX_BYTE_SWAP (1 << 2) +#define SPI_TX_HWORD_SWAP (1 << 3) +#define SPI_TX_BYTE_SWAP (1 << 2) +#define SPI_RX_SWAP_EN (1 << 4) +#define SPI_RX_BYTE_SWAP (1 << 6) +#define SPI_RX_HWORD_SWAP (1 << 7) + #endif /* __ASSEMBLY__ */ #endif diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 7bbf9ce..d1918cf 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -218,12 +218,29 @@ static void spi_get_fifo_levels(struct exynos_spi *regs, * * @param regs SPI peripheral registers * @param count Number of bytes to transfer + * @param step Number of bytes to transfer in each packet (1 or 4) */ -static void spi_request_bytes(struct exynos_spi *regs, int count) +static void spi_request_bytes(struct exynos_spi *regs, int count, int step) { + /* For word address we need to swap bytes */ + if (step == 4) { + setbits_le32(&regs->mode_cfg, + SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); + count /= 4; + setbits_le32(&regs->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN | + SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP | + SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP); + } else { + /* Select byte access and clear the swap configuration */ + clrbits_le32(&regs->mode_cfg, + SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); + writel(0, &regs->swap_cfg); + } + assert(count && count < (1 << 16)); setbits_le32(&regs->ch_cfg, SPI_CH_RST); clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt); } @@ -238,6 +255,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, int toread, preamable_count = 0; unsigned start = get_timer(0); int stopping; + int step; out_bytes = in_bytes = todo; @@ -245,10 +263,19 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, !(spi_slave->mode & SPI_SLAVE); /* + * Try to transfer words if we can. This helps read performance at + * SPI clock speeds above about 20MHz. + */ + step = 1; + if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) && + !spi_slave->skip_preamble) + step = 4; + + /* * If there's something to send, do a software reset and set a * transaction size. */ - spi_request_bytes(regs, todo); + spi_request_bytes(regs, todo, step); /* * Bytes are transmitted/received in pairs. Wait to receive all the @@ -260,28 +287,44 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, /* Keep the fifos full/empty. */ spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl); + + /* + * Don't completely fill the txfifo, since we don't want our + * rxfifo to overflow, and it may already contain data. + */ while (tx_lvl < spi_slave->fifo_size / 2 && out_bytes) { - temp = txp ? *txp++ : 0xff; + if (!txp) + temp = -1; + else if (step == 4) + temp = *(uint32_t *)txp; + else + temp = *txp; writel(temp, &regs->tx_data); - out_bytes--; - tx_lvl++; + out_bytes -= step; + if (txp) + txp += step; + tx_lvl += step; } - if (rx_lvl > 0 && in_bytes) { - while (rx_lvl > 0 && in_bytes) { + if (rx_lvl >= step && in_bytes) { + while (rx_lvl >= step && in_bytes) { temp = readl(&regs->rx_data); if (!rxp && !stopping) { - in_bytes--; + in_bytes -= step; } else if (spi_slave->skip_preamble) { if (temp == SPI_PREAMBLE_END_BYTE) { spi_slave->skip_preamble = 0; stopping = 0; } } else { - *rxp++ = temp; - in_bytes--; + if (step == 4) + *(uint32_t *)rxp = temp; + else + *rxp = temp; + in_bytes -= step; + rxp += step; } - toread--; - rx_lvl--; + toread -= step; + rx_lvl -= step; } /* * We have run out of input data, but haven't read enough @@ -293,7 +336,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, assert(!out_bytes); toread = out_bytes = in_bytes; txp = NULL; - spi_request_bytes(regs, toread); + spi_request_bytes(regs, toread, step); } if (spi_slave->skip_preamble && get_timer(start) > 100) { printf("SPI timeout: in_bytes=%d, out_bytes=%d, ", @@ -336,10 +379,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, if ((flags & SPI_XFER_BEGIN)) spi_cs_activate(slave); - /* Exynos SPI limits each transfer to 65535 bytes */ + /* + * Exynos SPI limits each transfer to 65535 transfers. To keep + * things simple, allow a maximum of 65532 bytes. We could allow + * more in word mode, but the performance difference is small. + */ bytelen = bitlen / 8; for (upto = 0; !ret && upto < bytelen; upto += todo) { - todo = min(bytelen - upto, (1 << 16) - 1); + todo = min(bytelen - upto, (1 << 16) - 4); ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags); } -- 1.7.4.4

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[U-Boot] [PATCH 0/3] Tegra: USB: EHCI: add Tegra30 compatible support
by Jim Lin 08 May '13

08 May '13

Tegra114 USB EHCI is compatible with Tegra30 USB EHCI except: 1. Port Reset - Tegra30 takes 55ms, Tegra114 takes 50 ms to finish. 2. PLL parameters. Jim Lin (3): ARM: Tegra: FDT: Add USB support for T20/T30/T114 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114 Tegra: Config: Enable Tegra30/Tegra114 USB function arch/arm/dts/tegra114.dtsi | 105 ++++++++ arch/arm/dts/tegra20.dtsi | 81 ++++++ arch/arm/dts/tegra30.dtsi | 108 ++++++++ arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra20/usb.h | 279 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra30/usb.h | 294 ++++++++++++++++++++++ board/nvidia/common/board.c | 2 +- board/nvidia/dts/tegra114-dalmore.dts | 7 + board/nvidia/dts/tegra30-cardhu.dts | 6 + drivers/usb/host/ehci-hcd.c | 40 ++- drivers/usb/host/ehci-tegra.c | 376 ++++++++++++++++++++------- include/configs/cardhu.h | 14 + include/configs/dalmore.h | 14 + include/configs/tegra114-common.h | 3 + include/configs/tegra30-common.h | 3 + include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 20 files changed, 1523 insertions(+), 360 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/usb.h create mode 100644 arch/arm/include/asm/arch-tegra114/usb.h create mode 100644 arch/arm/include/asm/arch-tegra20/usb.h create mode 100644 arch/arm/include/asm/arch-tegra30/usb.h -- 1.7.7

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[U-Boot] [PATCH] ARM: cfi_flash: Avoid generation of unaligned accesses
by Andrew Gabbasov 08 May '13

08 May '13

Packed structure cfi_qry contains unaligned 16- and 32-bits members, accessing which causes problems when cfi_flash driver is compiled with -munaligned-access option: flash initialization hangs, probably due to data error. Since fixing the code to use some other way of accessing those fields seems quite expensive, just force the compiler to use -mno-unaligned-access. Signed-off-by: Andrew Gabbasov <andrew_gabbasov(a)mentor.com> --- drivers/mtd/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 543c845..a120f0b 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -46,6 +46,9 @@ all: $(LIB) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +# SEE README.arm-unaligned-accesses +$(obj)cfi_flash.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) + ######################################################################### # defines $(obj).depend target -- 1.7.10.4

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[U-Boot] [PATCH] nds32: Use sections header to obtain link symbols
by ken kuo 08 May '13

08 May '13

From: Kuan-Yu Kuo <ken.kuoky(a)gmail.com> Include this header to get access to link symbols, which are otherwise removed. Signed-off-by: Kuan-Yu Kuo <ken.kuoky(a)gmail.com> Cc: Macpaul Lin <macpaul(a)gmail.com> --- arch/nds32/include/asm/u-boot-nds32.h | 5 ----- arch/nds32/lib/board.c | 3 ++- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h index f3c7b27..d22eb5b 100644 --- a/arch/nds32/include/asm/u-boot-nds32.h +++ b/arch/nds32/include/asm/u-boot-nds32.h @@ -30,11 +30,6 @@ #define _U_BOOT_NDS32_H_ 1 /* for the following variables, see start.S */ -extern char __bss_start[]; /* BSS start relative to _start */ -extern ulong __bss_end; /* BSS end relative to _start */ -extern char _end[]; /* end of image relative to _start */ -extern void _start(void); /* start of image relative to _start */ -extern ulong _TEXT_BASE; /* code start */ extern ulong IRQ_STACK_START; /* top of IRQ stack */ extern ulong FIQ_STACK_START; /* top of FIQ stack */ diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index a7d27fc..340d157 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -36,6 +36,7 @@ #include <nand.h> #include <onenand_uboot.h> #include <mmc.h> +#include <asm/sections.h> DECLARE_GLOBAL_DATA_PTR; @@ -300,7 +301,7 @@ void board_init_r(gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - monitor_flash_len = &_end - &_start; + monitor_flash_len = (ulong)&_end - (ulong)&_start; debug("monitor flash len: %08lX\n", monitor_flash_len); board_init(); /* Setup chipselects */ -- 1.7.9.5

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[U-Boot] [Patch v2, batch 1 01/10] doc/ramboot.mpc85xx: Documented the RAMBOOT for MPC85xx
by York Sun 08 May '13

08 May '13

From: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> There could be scenarios where the user would like to manually(via JTAG) configure the DDR/L2SRAM and load the bootloader binary onto DDR/L2SRAM. This document explains thse usecases and the detailed explanation of what needs to be done to use it. Most of the code from CONFIG_SYS_RAMBOOT will be used except for small changes of CCSRBAR etc. The changes are not very large, but it is good to document them so that user can get it working at once. Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> --- doc/README.ramboot-ppc85xx | 102 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 doc/README.ramboot-ppc85xx diff --git a/doc/README.ramboot-ppc85xx b/doc/README.ramboot-ppc85xx new file mode 100644 index 0000000..8ed45fb --- /dev/null +++ b/doc/README.ramboot-ppc85xx @@ -0,0 +1,102 @@ + RAMBOOT for MPC85xx Platforms + ============================== + +RAMBOOT literally means boot from DDR. But since DDR is volatile memory some +pre-mechanism is required to load the DDR with the bootloader binary. +- In case of SD and SPI boot this is done by BootROM code inside the chip + itself. +- In case of NAND boot FCM supports loading initial 4K code from NAND flash + which can initialize the DDR and get the complete bootloader copied to DDR. + +In addition to the above there could be some more methods to initialize the DDR +and load it manually. +Two of them are described below.There is also an explanation as to where these +methods could be handy. +1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then + execute the bootloader from DDR. + This may be handy in the following cases: + - In very early stage of platform bringup where other boot options are not + functional because of various reasons. + - In case the support to program the flashes on the board is not available. + +2. Load the RAM based bootloader onto DDR using already existing bootloader on + the board.And then execute the bootloader from DDR. + Some usecases where this may be used: + - While developing some new feature of u-boot, for example USB driver or + SPI driver. + Suppose the board already has a working bootloader on it. And you would + prefer to keep it intact, at the same time want to test your bootloader. + In this case you can get your test bootloader binary into DDR via tftp + for example. Then execute the test bootloader. + - Suppose a platform already has a propreitery bootloader which does not + support for example AMP boot. In this case also RAM boot loader can be + utilized. + + So basically when the original bootloader is required to be kept intact + RAM based bootloader can offer an updated bootloader on the system. + +Both the above Bootloaders are slight variants of SDcard or SPI Flash +bootloader or for that matter even NAND bootloader. +All of them define CONFIG_SYS_RAMBOOT. +The main difference among all of them is the way the pre-environment is getting +configured and who is doing that. +- In case of SD card and SPI flash bootloader this is done by On Chip BootROM inside the Si itself. +- In case of NAND boot SPL/TPL code does it with some support from Si itself. +- In case of the pure RAM based bootloaders we have to do it by JTAG manually or already existing bootloader. + +How to use them: +1. Using JTAG + Boot up in core hold off mode or stop the core after reset using JTAG + interface. + Preconfigure DDR/L2SRAM through JTAG interface. + - setup DDR controller registers. + - setup DDR LAWs + - setup DDR TLB + Load the RAM based boot loader to the proper location in DDR/L2SRAM. + set up IAR (Instruction counter properly) + Enable the core to execute. + +2. Using already existing bootloader. + get the rambased boot loader binary into DDR/L2SRAM via tftp. + execute the RAM based bootloader. + => tftp 11000000 u-boot-ram.bin + => go 1107f000 + +Please note that L2SRAM can also be used instead of DDR if the SOC has +sufficient size of L2SRAM. + +Necessary Code changes Required: +===================================== +Please note that below mentioned changes are for 85xx platforms. +They have been tested on P1020/P2020/P1010 RDB. + +The main difference between the above two methods from technical perspective is +that in 1st case SOC is just out of reset so it is in default configuration. +(CCSRBAR is at 0xff700000). +In the 2nd case bootloader has already re-located CCSRBAR to 0xffe00000 + +1. File name-> boards.cfg + There can be added specific Make options for RAMBoot. We can keep different + options for the two cases mentioned above. + for example + P1020RDB_JTAG_RAMBOOT and P1020RDB_GO_RAMBOOT. + +2. platform config file + for example include/configs/P1_P2_RDB.h + + #ifdef CONFIG_RAMBOOT + #define CONFIG_SDCARD + #endif + + This will finally use the CONFIG_SYS_RAMBOOT. + +3. File name-> arch/powerpc/include/asm/config_mpc85xx.h + In the section of the particular SOC, for example P1020, + + #if defined(CONFIG_GO) + #define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000 + #else + #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 + #endif + +For JTAG RAMBOOT this is not required because CCSRBAR is at ff700000. -- 1.7.9.5

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[U-Boot] [PATCH 1/7] powerpc/doc: Update the README.srio-pcie-boot-corenet
by Liu Gang 07 May '13

07 May '13

1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet file when the tabs are set to 8 characters. And the standard for u-boot should be 8 character tabs! So this issue should be amended. 2. Add a NOTE for the ENV parameters of the Slave. Signed-off-by: Liu Gang <Gang.Liu(a)freescale.com> --- doc/README.srio-pcie-boot-corenet | 34 ++++++++++++++++++++-------------- 1 files changed, 20 insertions(+), 14 deletions(-) diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet index cd7e7ee..2b1f76b 100644 --- a/doc/README.srio-pcie-boot-corenet +++ b/doc/README.srio-pcie-boot-corenet @@ -21,13 +21,13 @@ Environment of the SRIO or PCIE boot: e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set the boot location to SRIO or PCIE, and holdoff all the cores. - ---------- ----------- ----------- - | | | | | | - | | | | | | + ----------- ----------- ----------- + | | | | | | + | | | | | | | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM] - | | | |<===========>| | - | | | | | | - ---------- ----------- ----------- + | | | |<===========>| | + | | | | | | + ----------- ----------- ----------- The example based on P4080DS platform: Two P4080DS platforms can be used to implement the boot from SRIO or PCIE. @@ -87,26 +87,32 @@ How to use this feature: Please refer to the examples given above. 2. U-Boot image's compilation. - For master, U-Boot image should be generated normally. + For master, U-Boot image should be generated normally. - For example, master U-Boot image used on P4080DS should be compiled with + For example, master U-Boot image used on P4080DS should be compiled with make P4080DS_config. - For slave, U-Boot image should be generated specifically by + For slave, U-Boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. - For example, slave U-Boot image used on P4080DS should be compiled with + For example, slave U-Boot image used on P4080DS should be compiled with make P4080DS_SRIO_PCIE_BOOT_config. 3. Necessary modifications based on a specific environment. - For a specific environment, the addresses of the slave's U-Boot image, - UCode, ENV stored in master's NorFlash, and any other configurations - can be modified in the file: - include/configs/corenet_ds.h. + For a specific environment, the addresses of the slave's U-Boot image, + UCode, ENV stored in master's NorFlash, and any other configurations + can be modified in the file: + include/configs/corenet_ds.h. 4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2" or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to perform the role as a master for boot from SRIO or PCIE. + +NOTE: When the Slave's ENV parameters are stored in Master's NorFlash, + it can fetch them through PCIE or SRIO interface. But the ENV + parameters can not be modified by "saveenv" or other commands under + the Slave's u-boot environment, because the Slave can not erase, + write Master's NorFlash by PCIE or SRIO link. -- 1.7.1

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[U-Boot] [PATCH v3 0/17] sandbox: Generic board support and other improvements
by Simon Glass 07 May '13

07 May '13

This series adds generic board support to sandbox and switches to use this always. With sandbox it was noticed that turning CONFIG_SYS_GENERIC_BOARD off can cause a build failure if a previous autoconf.mk exists which indicates that generic board is not supported, so a patch is provided to fix this. It is useful to convert a pointer into an 'address' in the sandbox RAM buffer - the opposite of map_sysmem(). This is added in this series and used in several places. With sandbox it is easier to read a file from the host than to use the CONFIG_OF_SEPARATE option, since this option requires knowledge of the executable image structure which is not really appropriate on the host system. A new CONFIG_OF_HOSTFILE provides this. A few related FDT changes are included in this series also. The -c option is enhanced to support passing entire scripts to sandbox. This is useful when writing non-trivial test code. Most of these patches were previously submitted as part of the verified boot effort. This series collects the independent sandbox-related patches together to make it easier to review. THe whole series is marked as version 3 for this reason. Changes in v3: - Rebase on master, to take account of generic board - Add CONFIG_OF_HOSTFILE support to generic board instead of sandbox - Remove #ifdefs which are not needed now that we have generic global_data Changes in v2: - Use gd->arch.ram_buf instead of gd->ram_buf (now that generic board is in) - Fix typo "os defined" -> "is defined" - Use gd->arch.ram_buf instead of gd->ram_buf (now that generic board is in) - Fix checkpatch warnings about split strings - fdt_valid() sets the FDT pointer to NULL on error, to simplify callers - Allow the control FDT to be set even if there is currently no control FDT - Correct bug in setting control FDT - Fix checkpatch checks about parenthesis alignment - Rebase to use updated fdt_valid() function - Fix checkpatch checks about parenthesis alignment - Revert the whole change including the set_working_fdt_addr() part - Move sandbox's command list patch from a later series Simon Glass (17): Trigger generic board error only when building sandbox: Provide a way to map from host RAM to U-Boot RAM sandbox: Add support for generic board sandbox: Use generic board init sandbox: Remove old board init code sandbox: Add CONFIG_OF_HOSTFILE to read FDT from host file fdt: Add a parameter to fdt_valid() Add getenv_hex() to return an environment variable as hex fdt: Allow fdt command to check and update control FDT sandbox: fdt: Support fdt command for sandbox fdt: Skip checking FDT if the pointer is NULL Revert "fdt- Tell the FDT library where the device tree is" sandbox: Allow -c argument to provide a command list sandbox: Support 'source' command fs: Add support for saving data to filesystems sandbox: fs: Add support for saving files to host filesystem sandbox: config: Enable CONFIG_FIT and CONFIG_CMD_FIT Makefile | 10 ++ arch/sandbox/config.mk | 5 +- arch/sandbox/cpu/cpu.c | 5 + arch/sandbox/cpu/start.c | 9 +- arch/sandbox/include/asm/io.h | 8 ++ arch/sandbox/include/asm/state.h | 1 + arch/sandbox/include/asm/u-boot.h | 22 +-- arch/sandbox/lib/Makefile | 1 - arch/sandbox/lib/board.c | 285 -------------------------------------- board/sandbox/sandbox/sandbox.c | 2 +- common/board_f.c | 106 ++++++++++++-- common/board_r.c | 8 +- common/cmd_fdt.c | 87 ++++++++---- common/cmd_nvedit.c | 15 ++ common/cmd_sandbox.c | 18 ++- common/cmd_source.c | 11 +- common/main.c | 8 -- config.mk | 4 +- doc/README.fdt-control | 6 +- fs/fs.c | 75 ++++++++++ fs/sandbox/sandboxfs.c | 33 +++++ include/asm-generic/sections.h | 2 +- include/common.h | 18 +++ include/configs/sandbox.h | 11 +- include/fs.h | 2 + include/sandboxfs.h | 1 + lib/fdtdec.c | 5 +- 27 files changed, 383 insertions(+), 375 deletions(-) delete mode 100644 arch/sandbox/lib/board.c -- 1.8.2.1

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[U-Boot] Fwd: Your message to U-Boot awaits moderator approval
by Сергей Янович 06 May '13

06 May '13

How long does usually moderation take? ---------- Forwarded message ---------- From: <u-boot-bounces(a)lists.denx.de> Date: 18 February 2013 21:39 Subject: Your message to U-Boot awaits moderator approval To: ynvich(a)gmail.com Your mail to 'U-Boot' with the subject [PATCH] arm: pxa: Add support for ICP DAS LP-8x4x Is being held until the list moderator can review it for approval. The reason it is being held: Post to moderated list Either the message will get posted to the list, or you will receive notification of the moderator's decision. If you would like to cancel this posting, please visit the following URL: http://lists.denx.de/mailman/confirm/u-boot/9c7f34e253b98128a0b73d945a10d78…

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