April 2013 - U-Boot

[U-Boot] [PATCH] Exynos: uart: s5p: enabling the uart tx/rx fifo
by Akshay Saraswat 21 May '13

21 May '13

This patch enables the uart tx/rx fifo. Now that fifo is enabled, the uart read/write functions are modfied to check the UFSTAT register for fifo status instead of UTRSTAT (as required with fifo's enabled). Tested by booting linux kernel. Before enabling tx/rx fifo "Uncompressing linux" message is garbled and after enabling it is proper. Signed-off-by: Alim Akhtar <alim.akhtar(a)samsung.com> Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- drivers/serial/serial_s5p.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 3c41242..e65125c 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -30,6 +30,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define RX_FIFO_COUNT_MASK 0xff +#define RX_FIFO_FULL_MASK (1 << 8) +#define TX_FIFO_FULL_MASK (1 << 24) + static inline struct s5p_uart *s5p_get_base_uart(int dev_index) { u32 offset = dev_index * sizeof(struct s5p_uart); @@ -87,8 +91,8 @@ int serial_init_dev(const int dev_index) { struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - /* reset and enable FIFOs, set triggers to the maximum */ - writel(0, &uart->ufcon); + /* enable FIFOs */ + writel(0x1, &uart->ufcon); writel(0, &uart->umcon); /* 8N1 */ writel(0x3, &uart->ulcon); @@ -130,7 +134,8 @@ int serial_getc_dev(const int dev_index) struct s5p_uart *const uart = s5p_get_base_uart(dev_index); /* wait for character to arrive */ - while (!(readl(&uart->utrstat) & 0x1)) { + while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | + RX_FIFO_FULL_MASK))) { if (serial_err_check(dev_index, 0)) return 0; } @@ -146,7 +151,7 @@ void serial_putc_dev(const char c, const int dev_index) struct s5p_uart *const uart = s5p_get_base_uart(dev_index); /* wait for room in the tx FIFO */ - while (!(readl(&uart->utrstat) & 0x2)) { + while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { if (serial_err_check(dev_index, 1)) return; } -- 1.8.0

3 2

[U-Boot] [PATCH 1/3] fw_env: fix type of len
by Mike Frysinger 21 May '13

21 May '13

This variable is assigned by a size_t, and is printed that way, but is incorrectly declared as an int. Which means we get warnings: fw_env.c: In function 'fw_setenv': fw_env.c:409:5: warning: format '%zu' expects argument of type 'size_t', but argument 3 has type 'int' [-Wformat] Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- tools/env/fw_env.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 9b023e8..02f97c0 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -379,7 +379,8 @@ int fw_env_write(char *name, char *value) */ int fw_setenv(int argc, char *argv[]) { - int i, len; + int i; + size_t len; char *name; char *value = NULL; -- 1.7.12.4

6 11

[U-Boot] [PATCH] Exynos5: clock: Update the equation to calculate PLL output frequency
by Akshay Saraswat 21 May '13

21 May '13

According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali <hatim.rv(a)samsung.com> Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- arch/arm/cpu/armv7/exynos/clock.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 956427c..5299bc7 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -73,10 +73,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ fout = (m + k / 1024) * (freq / (p * (1 << s))); } else { - if (s < 1) - s = 1; - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ - fout = m * (freq / (p * (1 << (s - 1)))); + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ + fout = m * (freq / (p * (1 << s))); } return fout; -- 1.8.0

3 2

[U-Boot] [PATCH] arm: pxa: Add support for ICP DAS LP-8x4x
by Sergey Yanovich 21 May '13

21 May '13

LP-8x4x is a programmable automation controller by ICP DAS. It is shipped with outdated U-Boot v1.3.0 This patch adds enough supports to boot the board: - 128M of 128M SDRAM - 32M of 48M NOR Flash memory - 1 of 4 Serial console (PXA FFUART) - 1 of 2 Ethernet controller (DM9000) Signed-off-by: Sergey Yanovich <ynvich(a)gmail.com> --- arch/arm/include/asm/mach-types.h | 13 ++ board/icpdas/lp8x4x/Makefile | 41 ++++++ board/icpdas/lp8x4x/lp8x4x.c | 133 ++++++++++++++++++ boards.cfg | 1 + include/configs/lp8x4x.h | 272 +++++++++++++++++++++++++++++++++++++ 5 files changed, 460 insertions(+) create mode 100644 board/icpdas/lp8x4x/Makefile create mode 100644 board/icpdas/lp8x4x/lp8x4x.c create mode 100644 include/configs/lp8x4x.h diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index a676b6d..644b937 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1107,6 +1107,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP5_SEVM 3777 #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 +#define MACH_TYPE_LP8X4X 4539 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14248,6 +14249,18 @@ extern unsigned int __machine_arch_type; # define machine_is_kzm9g() (0) #endif +#ifdef CONFIG_MACH_LP8X4X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LP8X4X +# endif +# define machine_is_lp8x4x() (machine_arch_type == MACH_TYPE_LP8X4X) +#else +# define machine_is_lp8x4x() (0) +#endif + /* * These have not yet been registered */ diff --git a/board/icpdas/lp8x4x/Makefile b/board/icpdas/lp8x4x/Makefile new file mode 100644 index 0000000..cbe6aa9 --- /dev/null +++ b/board/icpdas/lp8x4x/Makefile @@ -0,0 +1,41 @@ +# +# ICPDAS LP-8x4x Support +# +# Copyright (C) 2013 Sergey Yanovich <ynvich(a)gmail.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := lp8x4x.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c new file mode 100644 index 0000000..abdb84a --- /dev/null +++ b/board/icpdas/lp8x4x/lp8x4x.c @@ -0,0 +1,133 @@ +/* + * ICP DAS LP-8x4x Support + * + * Copyright (C) 2010 Marek Vasut <marek.vasut(a)gmail.com> + * adapted from Voipac PXA270 Support by + * Copyright (C) 2013 Sergey Yanovich <ynvich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/regs-mmc.h> +#include <asm/arch/pxa.h> +#include <netdev.h> +#include <serial.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ +int board_init(void) +{ + /* We have RAM, disable cache */ + dcache_disable(); + icache_disable(); + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* Arch number of lp8x4x */ + gd->bd->bi_arch_number = MACH_TYPE_LP8X4X; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int dram_init(void) +{ + pxa2xx_dram_init(); + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + +#ifdef CONFIG_CMD_USB +int usb_board_init(void) +{ + writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); + + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); + + while (readl(UHCHR) & UHCHR_FSBIR) + ; + + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); + + /* Clear any OTG Pin Hold */ + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); + + writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); + writel(readl(UHCRHDA) | 0x100, UHCRHDA); + + /* Set port power control mask bits, only 3 ports. */ + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); + + /* enable port 2 */ + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | + UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); + + return 0; +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); + udelay(11); + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); + + writel(readl(UHCCOMS) | 1, UHCCOMS); + udelay(10); + + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); + + return; +} +#endif + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/boards.cfg b/boards.cfg index b1319aa..2ca437e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1123,5 +1123,6 @@ gr_ep2s60 sparc leon3 - gaisler grsim sparc leon3 - gaisler gr_xc3s_1500 sparc leon3 - gaisler coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000 +lp8x4x arm pxa lp8x4x icpdas # Target ARCH CPU Board name Vendor SoC Options ######################################################################################################################## diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h new file mode 100644 index 0000000..57a8916 --- /dev/null +++ b/include/configs/lp8x4x.h @@ -0,0 +1,272 @@ +/* + * ICP DAS LP-8x4x configuration file + * + * Copyright (C) 2013 Sergey Yanovich <ynvich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_MACH_LP8X4X 1 /* ICP DAS LP-8x4x */ +#define CONFIG_SYS_TEXT_BASE 0x00000000 + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ethaddr=00:c0:26:28:96:30\0" \ + "ipaddr=192.168.0.10\0" \ + "netmask=255.255.255.0\0" \ + "serverip=192.168.0.1\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOOTCOMMAND \ + "mmcinfo; tftp a0008000 zImage; go a0008000;" + +#define CONFIG_BOOTARGS \ + "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \ + "init=/sbin/init rootfstype=ext3" + +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_LZMA /* LZMA compression support */ +#define CONFIG_OF_LIBFDT + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_CONS_INDEX 3 +#define CONFIG_BAUDRATE 115200 + +/* + * Bootloader Components Configuration + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_USB +#undef CONFIG_LCD +#undef CONFIG_CMD_IDE + +/* + * Networking Configuration + * chip on the ICPDAS LINPAC board + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x0C000000 +#define DM9000_IO 0x0C000000 +#define DM9000_DATA 0x0C004000 +#define CONFIG_NET_RETRY_COUNT 10 + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#endif + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 + +#undef CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE 1 + +/* + * Clock Configuration + */ +#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0xa0008000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +/* Use first 64kb bank of the internal SRAM */ +#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 + +/* + * NOR FLASH + */ +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x40000 + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } + +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_PROTECTION 1 + +#define CONFIG_ENV_IS_IN_FLASH 1 + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPSR0_VAL 0x08008004 +#define CONFIG_SYS_GPSR1_VAL 0x00cf0002 +#define CONFIG_SYS_GPSR2_VAL 0x0221c000 +#define CONFIG_SYS_GPSR3_VAL 0x00020000 + +#define CONFIG_SYS_GPCR0_VAL 0x0 +#define CONFIG_SYS_GPCR1_VAL 0x0000ab80 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPCR3_VAL 0x0 + +#define CONFIG_SYS_GPDR0_VAL 0xc0a18df4 +#define CONFIG_SYS_GPDR1_VAL 0xfcdfab83 +#define CONFIG_SYS_GPDR2_VAL 0x02e1ffff +#define CONFIG_SYS_GPDR3_VAL 0x00021b81 + +#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018 +#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402 +#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c +#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 + +#define CONFIG_SYS_PSSR_VAL 0x32 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x005002c0 +#define CONFIG_SYS_CCCR 0x02000290 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2 +#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc +#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9 +#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 +#define CONFIG_SYS_MDREFR_VAL 0x2093e018 +#define CONFIG_SYS_MDCNFG_VAL 0x810009d1 +#define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000001 +#define CONFIG_SYS_MCMEM0_VAL 0x0000c497 +#define CONFIG_SYS_MCMEM1_VAL 0x0000c497 +#define CONFIG_SYS_MCATT0_VAL 0x0000c497 +#define CONFIG_SYS_MCATT1_VAL 0x0000c497 +#define CONFIG_SYS_MCIO0_VAL 0x00008407 +#define CONFIG_SYS_MCIO1_VAL 0x00008407 + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_VOIPAC_LCD +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_BOARD_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x" +#define CONFIG_USB_STORAGE +#endif + +#endif /* __CONFIG_H */ -- 1.7.10.4

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[U-Boot] [PATCH 0/3 V5] EXYNOS5: Add GPIO numbering feature
by Rajeshwari Shinde 21 May '13

21 May '13

Changes in V2: - Enabled CMD_GPIO as suggested by Simon Glass and supported same for EXYNOS5 Changes in V3: - New patch added to rename S5P GPIO definitions to S5P_GPIO - GPIO Table added to calculate the base address of input gpio bank. Changes in V4: - To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them. - Function and table to support gpio command moved to s5p-gpio driver - Rebased on latest u-boot-samsung tree Changes in V5: - Rebased on latest u-boot-samsung tree - Removed Exynos5 specific code in gpio driver api to get bank. - Added #define HAVE_GENERIC_GPIO in config file to remove conditinal CPU check in gpio driver. Rajeshwari Shinde (3): EXYNOS5: Add gpio pin numbering feature S5P: Rename GPIO definitions EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 arch/arm/cpu/armv7/exynos/pinmux.c | 206 ++++++------- arch/arm/include/asm/arch-exynos/cpu.h | 10 +- arch/arm/include/asm/arch-exynos/gpio.h | 486 ++++++++++++++++++++++++++---- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 26 +- board/samsung/goni/goni.c | 4 +- board/samsung/origen/origen.c | 8 +- board/samsung/smdk5250/smdk5250.c | 24 +- board/samsung/smdkc100/smdkc100.c | 2 +- board/samsung/smdkv310/smdkv310.c | 10 +- board/samsung/trats/trats.c | 17 +- board/samsung/universal_c210/universal.c | 36 ++-- drivers/gpio/s5p_gpio.c | 111 ++++++- include/configs/exynos5250-dt.h | 2 + 13 files changed, 683 insertions(+), 259 deletions(-) -- 1.7.4.4

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[U-Boot] [PATCH] OMAP5: Add support for the SOM5_EVB board (OMAP5430-based)
by Lubomir Popov 15 May '13

15 May '13

Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- The som5_evb is an evaluation board for the APM-5 - a OMAP5430-based SOM (system On a Module) designed by MMS and manufactured under license by Jorjin Technologies. arch/arm/include/asm/mach-types.h | 13 ++ board/mms/som5_evb/Makefile | 49 +++++ board/mms/som5_evb/s5evb_mux_data.h | 376 +++++++++++++++++++++++++++++++++++ board/mms/som5_evb/som5_evb.c | 200 +++++++++++++++++++ boards.cfg | 1 + include/configs/omap5_som5_evb.h | 336 +++++++++++++++++++++++++++++++ 6 files changed, 975 insertions(+) create mode 100644 board/mms/som5_evb/Makefile create mode 100644 board/mms/som5_evb/s5evb_mux_data.h create mode 100644 board/mms/som5_evb/som5_evb.c create mode 100644 include/configs/omap5_som5_evb.h diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index a676b6d..236fa17 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1107,6 +1107,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP5_SEVM 3777 #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 +#define MACH_TYPE_SOM5_EVB 4545 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14248,6 +14249,18 @@ extern unsigned int __machine_arch_type; # define machine_is_kzm9g() (0) #endif +#ifdef CONFIG_MACH_SOM5_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOM5_EVB +# endif +# define machine_is_som5_evb() (machine_arch_type == MACH_TYPE_SOM5_EVB) +#else +# define machine_is_som5_evb() (0) +#endif + /* * These have not yet been registered */ diff --git a/board/mms/som5_evb/Makefile b/board/mms/som5_evb/Makefile new file mode 100644 index 0000000..248e5cc --- /dev/null +++ b/board/mms/som5_evb/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := som5_evb.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mms/som5_evb/s5evb_mux_data.h b/board/mms/som5_evb/s5evb_mux_data.h new file mode 100644 index 0000000..791a4ad --- /dev/null +++ b/board/mms/som5_evb/s5evb_mux_data.h @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2013 MM Solutions AD, <www.mm-sol.com> + * + * Lubomir Popov <lpopov(a)mm-sol.com> <l-popov(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _SOM5_EVB_MUX_DATA_H +#define _SOM5_EVB_MUX_DATA_H + +#include <asm/arch/mux_omap5.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + + {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */ + {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */ + {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */ + {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */ + {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */ + {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */ + {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */ + {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */ + {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */ + {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */ + + {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */ + {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */ + {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0 */ + {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1 */ + {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2 */ + {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3 */ + + {UART3_RX_IRRX, (PTU | IEN | M0)},/* UART3_RX_IRRX */ + {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */ + + {HSI2_CAREADY, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_CLK */ + {HSI2_ACREADY, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_NXT */ + {HSI2_CAWAKE, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_DIR */ + {HSI2_ACWAKE, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_STP */ + {HSI2_CAFLAG, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_DATA0 */ + {HSI2_CADATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_DATA1 */ + {HSI2_ACFLAG, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_DATA2 */ + {HSI2_ACDATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_DATA3 */ + {UART2_RTS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_DATA4 */ + {UART2_CTS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_DATA5 */ + {UART2_RX, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_DATA6 */ + {UART2_TX, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* USBB1_ULPIPHY_DATA7 */ + + {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ + {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ + + {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE */ + {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ + + {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ + {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ + {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX (LP: WTF is this for?) */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + + {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ + {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ + + {SYS_32K, (IEN | M0)}, /* SYS_32K */ + +}; + +const struct pad_conf_entry core_padconf_array_non_essential[] = { +#if 0 +/* GPMC is actually not useable directly as we don't have + the GPMC_NOE_NRE signal available, and some external logic + shall be needed. Anyway, M4 is the reset default. +*/ + {C2C_DATAIN0, (IEN | M4)}, /* GPMC_AD0 */ + {C2C_DATAIN1, (IEN | M4)}, /* GPMC_AD1 */ + {C2C_DATAIN2, (IEN | M4)}, /* GPMC_AD2 */ + {C2C_DATAIN3, (IEN | M4)}, /* GPMC_AD3 */ + {C2C_DATAIN4, (IEN | M4)}, /* GPMC_AD4 */ + {C2C_DATAIN5, (IEN | M4)}, /* GPMC_AD5 */ + {C2C_DATAIN6, (IEN | M4)}, /* GPMC_AD6 */ + {C2C_DATAIN7, (IEN | M4)}, /* GPMC_AD7 */ + {C2C_CLKIN1, (IEN | M4)}, /* GPMC_CLK */ + {C2C_CLKIN0, (M5)}, /* GPMC_NBE1 */ + {C2C_CLKOUT0, (M4)}, /* GPMC_NADV_ALE */ + {C2C_CLKOUT1, (M4)}, /* GPMC_NBE0_CLE */ + {C2C_DATAOUT0, (IEN | M4)}, /* GPMC_AD8 */ + {C2C_DATAOUT1, (IEN | M4)}, /* GPMC_AD9 */ + {C2C_DATAOUT2, (IEN | M4)}, /* GPMC_AD10 */ + {C2C_DATAOUT3, (IEN | M4)}, /* GPMC_AD11 */ + {C2C_DATAOUT4, (IEN | M4)}, /* GPMC_AD12 */ + {C2C_DATAOUT5, (IEN | M4)}, /* GPMC_AD13 */ + {C2C_DATAOUT6, (IEN | M4)}, /* GPMC_AD14 */ + {C2C_DATAOUT7, (IEN | M4)}, /* GPMC_AD15 */ + {C2C_DATA8, (M4)}, /* GPMC_A16 */ + {C2C_DATA9, (M4)}, /* GPMC_A17 */ + {C2C_DATA10, (M4)}, /* GPMC_A18 */ + {C2C_DATA11, (M4)}, /* GPMC_A19 */ + {C2C_DATA12, (M4)}, /* GPMC_A20 */ + {C2C_DATA13, (M4)}, /* GPMC_A21 */ + {C2C_DATA14, (M4)}, /* GPMC_A22 */ + {C2C_DATA15, (M4)}, /* GPMC_A23 */ + {LLIA_WAKEREQOUT, (PTU | IEN | M4)}, /* GPMC_WAIT0 */ + {UART1_RTS, (M4)}, /* GPMC_NCS7 */ +#else +/* Test in GPIO mode. Convention: left (odd) pins on connector are + outputs (initialized to PD), right (even) pins are inputs with PU. +*/ + {C2C_DATAIN0, (IEN | PTU | M6)}, /* GPIO2_37 In J201:06 */ + {C2C_DATAIN1, (IEN | PTU | M6)}, /* GPIO2_38 In J201:04 */ + {C2C_DATAIN2, (IEN | PTU | M6)}, /* GPIO2_39 In J201:10 */ + {C2C_DATAIN3, (IEN | PTU | M6)}, /* GPIO2_40 In J201:08 */ + {C2C_DATAIN4, (IEN | PTU | M6)}, /* GPIO2_41 In J201:16 */ + {C2C_DATAIN5, (IEN | PTU | M6)}, /* GPIO2_42 In J201:12 */ + {C2C_DATAIN6, (IEN | PTU | M6)}, /* GPIO2_43 In J201:20 */ + {C2C_DATAIN7, (IEN | PTU | M6)}, /* GPIO2_44 In J201:18 */ + {C2C_CLKIN1, (PTD | M6)}, /* GPIO2_36 Out J201:03 */ + {C2C_CLKIN0, (PTD | M6)}, /* GPIO2_35 Out J201:11 */ + {C2C_CLKOUT0, (PTD | M6)}, /* GPIO2_33 Out J201:17 */ + {C2C_CLKOUT1, (PTD | M6)}, /* GPIO2_34 Out J201:09 */ + {C2C_DATAOUT0, (PTD | M6)}, /* GPIO2_56 Out J201:31 */ + {C2C_DATAOUT1, (PTD | M6)}, /* GPIO2_57 Out J201:23 */ + {C2C_DATAOUT2, (PTD | M6)}, /* GPIO2_58 Out J201:25 */ + {C2C_DATAOUT3, (PTD | M6)}, /* GPIO2_59 Out J201:15 */ + {C2C_DATAOUT4, (PTD | M6)}, /* GPIO2_60 Out J201:29 */ + {C2C_DATAOUT5, (PTD | M6)}, /* GPIO2_61 Out J201:21 */ + {C2C_DATAOUT6, (IEN | PTU | M6)}, /* GPIO2_62 In J201:22 */ + {C2C_DATAOUT7, (IEN | PTU | M6)}, /* GPIO2_63 In J201:24 */ + {C2C_DATA8, (IEN | PTU | M6)}, /* GPIO4_113 In J201:32 */ + {C2C_DATA9, (IEN | PTU | M6)}, /* GPIO4_114 In J201:30 */ + {C2C_DATA10, (IEN | PTU | M6)}, /* GPIO4_115 In J201:36 */ + {C2C_DATA11, (IEN | PTU | M6)}, /* GPIO4_116 In J201:26 */ + {C2C_DATA12, (PTD | M6)}, /* GPIO4_117 Out J201:35 */ + {C2C_DATA13, (PTD | M6)}, /* GPIO4_118 Out J201:33 */ + {C2C_DATA14, (IEN | PTU | M6)}, /* GPIO4_119 In J201:38 */ + {C2C_DATA15, (IEN | PTU | M6)}, /* GPIO4_120 In J201:34 */ + {LLIA_WAKEREQOUT, (PTD | M6)}, /* GPIO2_45 Out J201:07 */ + {UART1_RTS, (PTD | M6)}, /* GPIO3_75 Out J201:37 */ +#endif + {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 In I/O Exp Int */ + + {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 Out J701:28 */ + {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 Out J701:26 */ + {HSI1_ACWAKE, (PTD | M6)}, /* GPIO3_66 Out J801:25 */ + {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 In SDcard:CD */ + {HSI1_ACFLAG, (PTU | IEN | M6)}, /* GPIO3_68 In J801:22 */ + {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 Out J801:21 */ + {HSI1_CAFLAG, (PTU | IEN | M6)}, /* GPIO3_70 In J801:32 */ + {HSI1_CADATA, (PTD | M6)}, /* GPIO3_71 Out J801:29 */ + {UART1_TX, (PTU | IEN | M6)}, /* GPIO3_72 In J801:26 */ + {UART1_CTS, (PTD | M6)}, /* GPIO3_73 Out J801:31 */ + {UART1_RX, (PTU | IEN | M6)}, /* GPIO3_74 In J801:30 */ + + {USBB1_HSIC_STROBE, (PTU | IEN | M6)}, /* GPIO3_92 In NU */ + {USBB1_HSIC_DATA, (PTU | IEN | M6)}, /* GPIO3_93 In NU */ + + {TIMER10_PWM_EVT, (PTD | M6)}, /* GPIO6_188 Out J802:11 */ + {DSIPORTA_TE0, (PTU | IEN | M6)}, /* GPIO6_189 In J802:26 */ + {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X J704 */ + {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y J704 */ + {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X J704 */ + {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y J704 */ + {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X J704 */ + {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y J704 */ + {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X J704 */ + {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y J704 */ + {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X J704 */ + {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y J704 */ + + {TIMER9_PWM_EVT, (PTU | IEN | M6)}, /* GPIO6_190 In J802:12 */ + {DSIPORTC_TE0, (PTD | M6)}, /* GPIO6_191 Out J802:15 */ + {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X J702 */ + {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y J702 */ + {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X J702 */ + {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y J702 */ + {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X J702 */ + {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y J702 */ + {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X J702 */ + {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y J702 */ + {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X J702 */ + {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y J702 */ + + {RFBI_HSYNC0, (M4)}, /* KBD_COL5 (Out) HOME */ + {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 Out J704:24 3D_MODE_EN */ + {RFBI_WE, (PTD | M5)}, /* DRM_EMU2 (Out) */ + {RFBI_CS0, (PTD | M5)}, /* DRM_EMU3 (Out) */ + {RFBI_RE, (M4)}, /* KBD_COL4 (Out) SEND */ + {RFBI_A0, (PTU | IEN | M6)}, /* GPIO6_165 In SH2_SENS_INT */ + {RFBI_DATA0, (PTD | M5)}, /* DRM_EMU4 (Out) */ + {RFBI_DATA1, (PTD | M5)}, /* DRM_EMU5 (Out) */ + {RFBI_DATA2, (PTD | M5)}, /* DRM_EMU6 (Out) */ + {RFBI_DATA3, (PTD | M6)}, /* GPIO6_169 Out J704:22 3D_LCD_BANK_SEL */ + {RFBI_DATA4, (PTU | IEN | M6)}, /* GPIO6_170 In TEMP_ALERT on SOM (OD) */ + {RFBI_DATA5, (PTU | IEN | M6)}, /* GPIO6_171 In J802:30 */ + {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 Out LAN9730 nRESET */ + {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 Out USB4640 nRESET */ + {RFBI_DATA8, (M4)}, /* KBD_COL3 (Out) VOL- */ + {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 Out MCLK_1E */ + {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 Out MCLK_2E */ + {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 Out MCLK_3E */ + {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 Out J703:25 CAM_SUBPM_EN */ + {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 In J704:27 TSCR_INT (OD) */ + {RFBI_DATA14, (M4)}, /* KBD_COL7 (Out) SEARCH */ + {RFBI_DATA15, (M4)}, /* KBD_COL6 (Out) END */ + + {GPIO6_182, (PTU | IEN | M6)}, /* GPIO6_182 In J802:28 */ + {GPIO6_183, (PTD | M6)}, /* GPIO6_183 Out J704:25 nLCD_RESET */ + {GPIO6_184, (M4)}, /* KBD_COL2 (Out) VOL+ */ + {GPIO6_185, (PTU | IEN | M6)}, /* GPIO6_185 In J802:32 */ + {GPIO6_186, (PTD | M6)}, /* GPIO6_186 Out J802:25 */ + {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 (In) All btns*/ +#if 0 + {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 J802:31 */ + {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK J802:23 */ + {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO J802:29 */ + {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI J802:18 */ +#else + {MCSPI2_CS0, (PTD | M6)}, /* GPIO7_196 Out J802:31 */ + {MCSPI2_CLK, (PTD | M6)}, /* GPIO7_197 Out J802:23 */ + {MCSPI2_SIMO, (PTD | M6)}, /* GPIO7_198 Out J802:29 */ + {MCSPI2_SOMI, (PTU | IEN | M6)}, /* GPIO7_199 In J802:18 */ +#endif + {I2C4_SCL, (IEN | PTU | M0)}, /* I2C4_SCL */ + {I2C4_SDA, (IEN | PTU | M0)}, /* I2C4_SDA */ + + {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ + {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ + {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ + {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ + + {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ + {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ + {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ + {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ + {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ + {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ + {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ + {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ + {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ + {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ + + {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ + {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ + {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ + {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ + {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ + {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ + + {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ + {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ + {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ + {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ + + {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER/224 J701:22 */ + {CAM_STROBE, (M0)}, /* CAM_STROBE/225 J701:24 */ + {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET/226 J701:20 */ + {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 Out J703:26 PRIMARY_5M_RESET_N */ + {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 Out J703:28 SECONDARY_5M_RESET_N */ + {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 Out J701:18 */ + {TIMER8_PWM_EVT, (PTD | M6)}, /* GPIO8_230 Out J701:16 */ + + {I2C3_SCL, (IEN | PTU | M0)}, /* I2C3_SCL */ + {I2C3_SDA, (IEN | PTU | M0)}, /* I2C3_SDA */ + + {GPIO8_233, (PTD | M6)}, /* GPIO8_233 Out J701:25 */ + + {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ + {ABEDMIC_DIN1, (PTD | M6)}, /* GPIO4_97 Out J801:13 */ + {ABEDMIC_DIN2, (PTU | IEN | M6)}, /* GPIO4_98 In J801:12 */ + {ABEDMIC_DIN3, (PTD | M6)}, /* GPIO4_99 Out J801:11 */ + {ABEDMIC_CLK1, (PTU | IEN | M6)}, /* GPIO4_100 In J801:14 */ + + {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX BT Aud */ + {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX BT Aud */ + {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX BT Aud */ + {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR BT Aud */ + + {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR FM Aud */ + {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX FM Aud */ + {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX FM Aud */ + {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX FM Aud */ + + {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ + {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ + {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ + {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ + + {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ + {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ + {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0 */ + {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1 */ + {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2 */ + {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3 */ + + {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX BT HCI */ + {UART5_TX, (M0)}, /* UART5_TX BT HCI */ + {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS BT HCI */ + {UART5_RTS, (M0)}, /* UART5_RTS BT HCI */ + + {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ + {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ + + {MCSPI1_CLK, (PTD | M6)}, /* GPIO5_140 Out WLAN EN */ + {MCSPI1_SOMI, (PTD | M6)}, /* GPIO5_141 Out J802:17 */ + {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 Out BT EN */ + {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 Out BT Wkup */ + {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 In Host WU */ + + {I2C5_SCL, (IEN | PTU | M0)}, /* I2C5_SCL */ + {I2C5_SDA, (IEN | PTU | M0)}, /* I2C5_SDA */ + + {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 Out AUDPWRON*/ + {PERSLIMBUS2_DATA, (PTD | M6)}, /* GPIO5_146 Out J802:27 */ + {UART6_TX, (PTD | M6)}, /* GPIO5_149 Out J802:13 */ + {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 In J802:20 */ + {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 In J802:21 EXCEPTION TO RULE, SHORT WITH PIN 23 */ + {UART6_RTS, (PTD | M6)}, /* GPIO5_152 Out J802:19 */ + {UART3_CTS_RCTX, (PTD | IEN | M6)}, /* GPIO5_153 In J802:14 or SATA_ACTLED Out (M1). PTD! */ + {UART3_RTS_IRSD, (PTU | IEN | M6)}, /* GPIO5_154 In J802:16 */ + + {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ + {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ + +}; + +const struct pad_conf_entry wkup_padconf_array_non_essential[] = { + + {LLIA_WAKEREQIN, (PTU | IEN | M6)}, /* GPIO1_WK14 In J201:19 */ + {LLIB_WAKEREQIN, (PTU | IEN | M6)}, /* GPIO1_WK15 In J801:18 */ + {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ + {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ + {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ + {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ + {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ + {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ + {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ + {JTAG_TDO, (M0)}, /* JTAG_TDO */ + {FREF_CLK_IOREQ, (PTU | IEN | M6)}, /* GPIO1_WK13 In ETH_WAKE */ + {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ + {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ + {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ + {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 In WiLink Int */ + {FREF_CLK1_REQ, (PTU | IEN | M6)}, /* GPIO1_WK8 In SH2_MSP_INT */ + {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ + {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ + {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ + {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ + {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ + {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ + {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ + {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ + {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ + {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ + +}; + +#endif /* _SOM5_EVB_MUX_DATA_H */ + diff --git a/board/mms/som5_evb/som5_evb.c b/board/mms/som5_evb/som5_evb.c new file mode 100644 index 0000000..a84672e --- /dev/null +++ b/board/mms/som5_evb/som5_evb.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2013 MM Solutions AD, <www.mm-sol.com> + * + * 02/2013 Derived from OMAP5 EVM and modified for the SOM5 EVB + * by Lubomir Popov <lpopov(a)mm-sol.com> <l-popov(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl6035.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/gpio.h> +#include <asm/omap_common.h> + +#include "s5evb_mux_data.h" + +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/arch/ehci.h> +#include <asm/ehci-omap.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: MM Solutions SOM5 EVB\n" +}; + +/** + * @brief board_init + * + * @return 0 + */ +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_arch_number = MACH_TYPE_SOM5_EVB; + gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +/** + * @brief misc_init_r - Configure SOM5 EVB board specific features + * such as power configurations, ethernet initialization as phase2 + * of boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ +#ifdef CONFIG_TWL6035_POWER + twl6035_init_settings(); +#ifdef CONFIG_TWL6035_AUDPWR + /* Useful for measuring voltages around the codec. + * Works with a TWL604x only. + */ + twl6035_audio_power(1); /* Power on 2.1 V SMPS, enable 32 kHz */ + udelay(1000); /* Allow ramp-up */ + /* Start TWL6040 internal power on sequence: */ + gpio_request(CONFIG_OMAP_AUDPWRON_GPIO, "AUDPWRON"); + gpio_direction_output(CONFIG_OMAP_AUDPWRON_GPIO, 1); +#endif +#ifdef CONFIG_BB_CHRG + /* Board has a 3 V super-cap for BB */ + twl6035_enable_bb_charge(BB_HIGH_ICHRG | BB_VSEL_3V0 | BB_CHRG_EN); +#endif +#endif /* CONFIG_TWL6035_POWER */ +#ifdef CONFIG_SYSCLK_OUT_EN + /* Enable FREF_XTAL_CLK output (19.2 MHz). + * Used as Audio MCLK; for measurement only. + * TODO: Use proper defines + * control_ckobuffer + */ + writel(0x10000000, 0x4ae0cdb4); +#endif + return 0; +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + /* Set the MSECURE Mode for GPIO234 pin */ + if (get_device_type() == DEVICE_GP) { + u32 msecure_pad = CONTROL_PADCONF_CORE + GPIO8_234; + writew((readw(msecure_pad) & ~M7) | M1, msecure_pad); + } +#ifdef CONFIG_I2C_INTERNAL_PULLUPS + /* Enable internal I2C-compatible pullups on all buses + * TODO: Replace this ugly hardcoding with proper defines (omap.h) + * control_smart3io_padconf_0, control_i2c_0 + */ + writel(0x00554000, 0x4a002dc0); /* First set drive strength */ + writel(0, 0x4a002e04); /* Now enable pull-ups */ +#endif +} + +void set_muxconf_regs_non_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + sizeof(core_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + sizeof(wkup_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI + +#define USB_HOST_HS_CLKCTRL_MASK 0x0100D7C0 /* CM_L3INIT_USB_HOST_HS_CLKCTRL */ +#define USB_TLL_HS_CLKCTRL_MASK 0x00000700 /* CM_L3INIT_USB_TLL_HS_CLKCTRL */ + +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, /* USBB1: ULPI PHY TUSB1210 */ + .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, /* USBB2: HSIC USB4640 hub */ + .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, /* USBB3: HSIC LAN9730 Ethernet ctrl */ +}; + +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + int ret; + + /* Enbale all 3 USB ports UHH, UTMI and HSIC clocks */ + setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, + USB_HOST_HS_CLKCTRL_MASK); + + /* Enbale all 3 USB host ports TLL clocks */ + setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, + USB_TLL_HS_CLKCTRL_MASK); + + /* USBB1 ULPI PHY uses OMAP FREF_CLK0_OUT. Must turn it on. + * TODO: Replace this ugly hardcoding with proper defines + */ + writel(0x0100, 0x4ae0a310); + udelay(1000); /* Let PHY PLL lock */ + + ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); + if (ret < 0) + return ret; + + return 0; +} + +int ehci_hcd_stop(void) +{ + int ret; + + ret = omap_ehci_hcd_stop(); + + clrbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, + USB_HOST_HS_CLKCTRL_MASK); + clrbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, + USB_TLL_HS_CLKCTRL_MASK); + + /* TODO: Replace this ugly hardcoding with proper defines + */ + writel(0, 0x4ae0a310); /* Stop FREF_CLK0_OUT */ + return ret; +} +#endif /* CONFIG_USB_EHCI */ + diff --git a/boards.cfg b/boards.cfg index 5fc70be..337dc42 100644 --- a/boards.cfg +++ b/boards.cfg @@ -292,6 +292,7 @@ twister arm armv7 twister technex nokia_rx51 arm armv7 rx51 nokia omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 +omap5_som5_evb arm armv7 som5_evb mms omap5 omap5_evm arm armv7 omap5_evm ti omap5 dra7xx_evm arm armv7 dra7xx ti omap5 s5p_goni arm armv7 goni samsung s5pc1xx diff --git a/include/configs/omap5_som5_evb.h b/include/configs/omap5_som5_evb.h new file mode 100644 index 0000000..46a9c0c --- /dev/null +++ b/include/configs/omap5_som5_evb.h @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2013 MM Solutions AD, <www.mm-sol.com> + * + * 02/2013 Derived from OMAP5 EVM and modified for the SOM5 EVB + * by Lubomir Popov <lpopov(a)mm-sol.com> <l-popov(a)ti.com> + * + * Configuration settings for the MMS SOM5 (APM-5) Evaluation Board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP54XX /* which is a 54XX */ +#define CONFIG_OMAP5430 /* which is in a 5430 */ +#define CONFIG_SOM5EVB /* working with the SOM5 EVB */ +/* Machine type for Linux */ +#define CONFIG_MACH_TYPE MACH_TYPE_SOM5_EVB + +#define CONFIG_OMAP_GPIO + +/* Get CPU defs */ +#include <asm/arch/cpu.h> +#include <asm/arch/omap.h> + +/* Display CPU and Board Info */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 19200000 /* Clock output from T2 */ +#define V_SCLK V_OSCK +/* Enable all clocks: */ +/*#define CONFIG_SYS_CLOCKS_ENABLE_ALL*/ + +#define CONFIG_SYS_ENABLE_PADS_ALL /* Enable all PADS for now */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + * Total Size Environment - 128k + * Malloc - add 256k + */ +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) +/* Vector Base */ +#define CONFIG_SYS_CA15_VECTOR_BASE SRAM_ROM_VECT_BASE + +/* + * Hardware drivers + */ + +/* + * serial port - NS16550 compatible + */ +#define V_NS16550_CLK 48000000 + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 UART3_BASE + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, \ + 57600, 115200} + +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x00 /* Own slave addr */ +#define CONFIG_DRIVER_OMAP54XX_I2C +#define CONFIG_I2C_MULTI_BUS +/* MUST be defined if external pullups are not populated: */ +#define CONFIG_I2C_INTERNAL_PULLUPS +/* Define to use Repeated Start by i2c_read (otherwise Stop-Start + * shall be used between the address and data phases): + */ +#undef CONFIG_I2C_REPEATED_START +/* Used by i2c mm/mw; needed for correct write to EEPROM: */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* TWL6035 */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_TWL6035_POWER +/* Undef to disable forced PWM mode for the 1.8 V SMPS: */ +#define CONFIG_TWL6035_SMPS7_FPWM +/* Following define enables testing of the TWL6040 audio codec power + * supply environment: the PMIC 2.1 V SMPS, and the codec's internal + * REF, NCP and HS/LS LDOs. Undef to disable powering up codec. */ +#define CONFIG_TWL6035_AUDPWR + +#ifdef CONFIG_TWL6035_AUDPWR +#define CONFIG_OMAP_AUDPWRON_GPIO 145 +#endif +/* Undef to disable BB (super-cap) charging: */ +#define CONFIG_BB_CHRG +#endif /* CONFIG_SPL_BUILD */ + +/* For Audio MCLK test/measurement only; enables the + * OMAP5 FREF_XTAL_CLK output: */ +#define CONFIG_SYSCLK_OUT_EN + +/* MMC */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_NOWHERE +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_CMD_SAVEENV +#endif + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* Flash */ +#define CONFIG_SYS_NO_FLASH + +/* Cache */ +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CACHELINE_SHIFT 6 + +/* USB UHH support options */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +/* No signals to reset external PHYs on this board: */ +/*#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO xxx */ + +/* Due to HSIC connect ussues, device reset is required upon + * applying port power. A GPIO is needed per HSIC device: + */ +#define CONFIG_OMAP_HSIC_PORT2_RESET_GPIO 173 /* Combo hub */ +#define CONFIG_OMAP_HSIC_PORT3_RESET_GPIO 172 /* Ethernet Ctrlr */ + +/* USB Networking options */ + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +/* Commands to include */ +#include <config_cmd_default.h> + +/* Enabled commands */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_DHCP /* DHCP support */ +#define CONFIG_CMD_PING /* PING support */ +#define CONFIG_NET_MULTI + +#define CONFIG_CMD_EXT2 /* EXT2 support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_GPIO /* GPIO support */ + +/* Disabled commands */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +/* + * Environment setup + */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usbethaddr=9e:77:39:1b:c4:2d\0" \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "usbtty=cdc_acm\0" \ + "vram=16M\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "vram=${vram} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan ; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi " + +#define CONFIG_AUTO_COMPLETE 1 + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_PROMPT "SOM5_EVB # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +/* + * memtest setup + */ +#define CONFIG_SYS_MEMTEST_START 0xb8000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (256 << 20)) +/* Undef following two for simple mtest */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 + +/* Default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x80000000 + +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * SDRAM Memory Map + * Even though we use two CS all the memory + * is mapped to one contiguous block + */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + +/* Defines for SDRAM init */ +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40300350 +#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_DISPLAY_PRINT + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x80E7FFC0--0x80E80000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80E80000 + +/* + * BSS and malloc area 64MB into memory to allow enough + * space for the kernel at the beginning of memory + */ +#define CONFIG_SPL_BSS_START_ADDR 0x84000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SPL_GPIO_SUPPORT + +#endif /* __CONFIG_H */ -- 1.7.9.5

3 17

[U-Boot] u-boot UBI support
by Paul B. Henson 15 May '13

15 May '13

I'm trying to get u-boot to read from a ubifs volume on an mx28evk board, and failing :(. I've got the nand partitioned: MX28EVK U-Boot > mtdparts device nand0 <gpmi-nand>, # parts = 3 #: name size offset mask_flags 0: bootloader 0x00300000 0x00000000 0 1: recovery 0x03200000 0x00300000 0 2: rootfs_config 0x04b00000 0x03500000 0 and u-boot attaches the partition fine: MX28EVK U-Boot > ubi part recovery UBI: attaching mtd1 to ubi0 UBI: physical eraseblock size: 131072 bytes (128 KiB) UBI: logical eraseblock size: 126976 bytes UBI: smallest flash I/O unit: 2048 UBI: VID header offset: 2048 (aligned 2048) UBI: data offset: 4096 UBI: attached mtd1 to ubi0 UBI: MTD device name: "mtd=1" UBI: MTD device size: 50 MiB UBI: number of good PEBs: 400 UBI: number of bad PEBs: 0 UBI: max. allowed volumes: 128 UBI: wear-leveling threshold: 4096 UBI: number of internal volumes: 1 UBI: number of user volumes: 1 UBI: available PEBs: 16 UBI: total number of reserved PEBs: 384 UBI: number of PEBs reserved for bad PEB handling: 4 UBI: max/mean erase counter: 5/2 but it fails to mount the filesystem: MX28EVK U-Boot > ubifsmount recovery UBIFS error (pid 0): ubifs_get_sb: cannot open "recovery", error -22 UBIFS error (pid 0): ubifs_mount: Error reading superblock on volume 'recovery' errno=-22! It looks like it sees the volume: MX28EVK U-Boot > ubi info l UBI: volume information dump: UBI: vol_id 0 UBI: reserved_pebs 376 UBI: alignment 1 UBI: data_pad 0 UBI: vol_type 3 UBI: name_len 8 UBI: usable_leb_size 126976 UBI: used_ebs 376 UBI: used_bytes 47742976 UBI: last_eb_bytes 126976 UBI: corrupted 0 UBI: upd_marker 0 UBI: name recovery UBI: volume information dump: UBI: vol_id 2147479551 UBI: reserved_pebs 2 UBI: alignment 1 UBI: data_pad 0 UBI: vol_type 3 UBI: name_len 13 UBI: usable_leb_size 126976 UBI: used_ebs 2 UBI: used_bytes 253952 UBI: last_eb_bytes 2 UBI: corrupted 0 UBI: upd_marker 0 UBI: name layout volume but just won't mount it. The same volume mounts from linux fine: / # ubiattach -m 1 /dev/ubi_ctrl [ 15.837687] UBI: attaching mtd1 to ubi0 [ 16.704968] UBI: scanning is finished [ 16.750187] UBI: attached mtd1 (name "recovery", size 50 MiB) to ubi0 [ 16.756906] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 16.763968] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 16.770718] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 16.777781] UBI: good PEBs: 400, bad PEBs: 0, corrupted PEBs: 0 [ 16.783875] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128 [ 16.791062] UBI: max/mean erase counter: 5/2, WL threshold: 4096, image sequence number: 2129180187 [ 16.800281] UBI: available PEBs: 0, total reserved PEBs: 400, PEBs reserved for bad PEB handling: 20 [ 16.810031] UBI: background thread "ubi_bgt0d" started, PID 32 / # mount -t ubifs ubi0:recovery /mnt [ 29.049343] UBIFS: background thread "ubifs_bgt0_0" started, PID 34 [ 29.359312] UBIFS: mounted UBI device 0, volume 0, name "recovery"(null) [ 29.366343] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes [ 29.375687] UBIFS: FS size: 46473216 bytes (44 MiB, 366 LEBs), journal size 6348800 bytes (6 MiB, 50 LEBs) [ 29.385531] UBIFS: reserved for root: 0 bytes (0 KiB) [ 29.390625] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 4058B2E3-BA45-4D0D-8A7E-B95D4DCF7E72, small LPT model / # ls /mnt emdebian-rootfs.tar.gz recovery_dtb.itb zImage imx28-evk.dtb recovery_initramfs.itb libmodules.tgz recovery_kernel.itb Am I missing something here? u-boot is from the git arm branch as of a few days ago. The ubi stuff was created using linux 3.8.4. Is it too new for the ubi code in u-boot? Thanks for any pointers...

4 12

[U-Boot] [PATCH] OMAP5: Enable USB Ethernet support with LAN9730
by Lubomir Popov 15 May '13

15 May '13

Added the LAN9730 to list of supported devices. This chip is used in the sEVM, uEVM and som5_evb. Tested on the som5_evb with dhcp and ping. Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- NOTE: For things to work, 'usb start' must be executed first, and we must have the Ethernet device found. Otherwise any Ethernet command shall cause a Data Abort (to be fixed ;) ). drivers/usb/eth/smsc95xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index fd8f8a7..685702e 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -798,6 +798,7 @@ struct smsc95xx_dongle { static const struct smsc95xx_dongle smsc95xx_dongles[] = { { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ + { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */ { 0x0000, 0x0000 } /* END - Do not remove */ }; -- 1.7.9.5

2 1

[U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count
by York Sun 14 May '13

14 May '13

From: Mingkai Hu <Mingkai.hu(a)freescale.com> Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. move ifc bank count to config_mpc85xx.h to support 8 bank count There's no IFC controller instead of eLBC controller on some platforms, such as MPC8536, P2041, P3041, P4080 etc, so there's no macro definition for the number of IFC chip select(CONFIG_SYS_FSL_IFC_BANK_COUNT) which is used in the IFC controller header file fsl_ifc.h on these platforms. Signed-off-by: Mingkai Hu <Mingkai.hu(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 58 ++++++++++++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 7 ++++ arch/powerpc/include/asm/fsl_ifc.h | 42 +++++++++++++++------ 4 files changed, 96 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index df2ab6d..379a7df 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -34,8 +34,8 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_ifc.h> -#include <asm/fsl_law.h> #include <asm/fsl_lbc.h> +#include <asm/fsl_law.h> #include <post.h> #include <asm/processor.h> #include <asm/fsl_ddr_sdram.h> diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index 56b319f..f0da355 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -26,7 +26,7 @@ void print_ifc_regs(void) int i, j; printf("IFC Controller Registers\n"); - for (i = 0; i < FSL_IFC_BANK_COUNT; i++) { + for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", i, get_ifc_cspr(i), i, get_ifc_amask(i), i, get_ifc_csor(i)); @@ -94,4 +94,60 @@ void init_early_memctl_regs(void) set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); #endif + +#ifdef CONFIG_SYS_CSPR4_EXT + set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); +#endif +#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) + set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); + set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); + set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); + set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); + + set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); + set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); + set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); +#endif + +#ifdef CONFIG_SYS_CSPR5_EXT + set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); +#endif +#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) + set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); + set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); + set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2); + set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3); + + set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5); + set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5); + set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); +#endif + +#ifdef CONFIG_SYS_CSPR6_EXT + set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); +#endif +#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) + set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); + set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); + set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); + set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); + + set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); + set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); + set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); +#endif + +#ifdef CONFIG_SYS_CSPR7_EXT + set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); +#endif +#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) + set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); + set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); + set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); + set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); + + set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); + set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); + set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); +#endif } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 5def364..7a1cdc7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -139,6 +139,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -491,6 +492,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 @@ -504,6 +506,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 @@ -529,6 +532,7 @@ #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -562,6 +566,7 @@ #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -590,6 +595,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -612,6 +618,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index ba41b73..debcb6b 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -21,6 +21,7 @@ #ifndef __ASM_PPC_FSL_IFC_H #define __ASM_PPC_FSL_IFC_H +#ifdef CONFIG_FSL_IFC #include <config.h> #include <common.h> @@ -798,13 +799,15 @@ extern void init_early_memctl_regs(void); #define set_ifc_ftim(i, j, v) \ (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) -#define FSL_IFC_BANK_COUNT 4 - enum ifc_chip_sel { IFC_CS0, IFC_CS1, IFC_CS2, IFC_CS3, + IFC_CS4, + IFC_CS5, + IFC_CS6, + IFC_CS7, }; enum ifc_ftims { @@ -907,6 +910,22 @@ struct fsl_ifc_gpcm { u32 res4[0x1F3]; }; +#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT +#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) +#define CONFIG_SYS_FSL_IFC_CSPR_RES \ + (0x25 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3) +#define CONFIG_SYS_FSL_IFC_AMASK_RES \ + (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3) +#define CONFIG_SYS_FSL_IFC_CSOR_RES \ + (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3) +#define CONFIG_SYS_FSL_IFC_FTIM_RES \ + (0x90 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 0xc) +#else +#error IFC BANK count not vaild +#endif +#else +#error IFC BANK count not defined +#endif /* * IFC Controller Registers @@ -918,24 +937,24 @@ struct fsl_ifc { u32 cspr_ext; u32 cspr; u32 res2; - } cspr_cs[FSL_IFC_BANK_COUNT]; - u32 res3[0x19]; + } cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u32 res3[CONFIG_SYS_FSL_IFC_CSPR_RES]; struct { u32 amask; u32 res4[0x2]; - } amask_cs[FSL_IFC_BANK_COUNT]; - u32 res5[0x17]; + } amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u32 res5[CONFIG_SYS_FSL_IFC_AMASK_RES]; struct { - u32 csor_ext; u32 csor; + u32 csor_ext; u32 res6; - } csor_cs[FSL_IFC_BANK_COUNT]; - u32 res7[0x19]; + } csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u32 res7[CONFIG_SYS_FSL_IFC_CSOR_RES]; struct { u32 ftim[4]; u32 res8[0x8]; - } ftim_cs[FSL_IFC_BANK_COUNT]; - u32 res9[0x60]; + } ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u32 res9[CONFIG_SYS_FSL_IFC_FTIM_RES]; u32 rb_stat; u32 res10[0x2]; u32 ifc_gcr; @@ -961,6 +980,7 @@ struct fsl_ifc { #undef CSPR_MSEL_NOR #define CSPR_MSEL_NOR CSPR_MSEL_GPCM #endif +#endif /* CONFIG_FSL_IFC */ #endif /* __ASSEMBLY__ */ #endif /* __ASM_PPC_FSL_IFC_H */ -- 1.7.9.5

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[U-Boot] [Patch v2, batch 3 01/17] common: Update cmd_bdinfo for PPC
by York Sun 14 May '13

14 May '13

Add board detail function to print more individual board information. Signed-off-by: York Sun <yorksun(a)freescale.com> CC: Wolfgang Denk <wd(a)denx.de> CC: Tom Rini <trini(a)ti.com> --- common/cmd_bdinfo.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 85279d5..3bf8cf2 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -84,6 +84,12 @@ static void print_mhz(const char *name, unsigned long hz) } #if defined(CONFIG_PPC) +static void __board_detail(void) +{ + /* Please define boot_detail() for your platform */ +} + +void board_detail(void) __attribute__((weak, alias("__board_detail"))); int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -169,6 +175,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("IP addr = %s\n", getenv("ipaddr")); printf("baudrate = %6u bps\n", bd->bi_baudrate); print_num("relocaddr", gd->relocaddr); + board_detail(); return 0; } -- 1.7.9.5

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