December 2013 - U-Boot

[U-Boot] [PATCH v4] socfpga: Adding Freeze Controller driver
by Chin Liang See 02 Dec '13

02 Dec '13

Adding Freeze Controller driver. All HPS IOs need to be in freeze state during pin mux or IO buffer configuration. It is to avoid any glitch which might happen during the configuration from propagating to external devices. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)altera.com> --- Changes for v4 - Removed additional lines - Single function call to freeze and thaw all channels Changes for v3 - Removed unused macro in freeze_controller.h Changes for v2 - Removed FREEZE_CONTROLLER_FSM_HW - Removed the get_timer_count_masked and convert to use delay in us - Used shorter local variables --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/freeze_controller.c | 216 ++++++++++++++++++++ arch/arm/cpu/armv7/socfpga/spl.c | 9 + .../include/asm/arch-socfpga/freeze_controller.h | 50 +++++ 4 files changed, 276 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/freeze_controller.c create mode 100644 arch/arm/include/asm/arch-socfpga/freeze_controller.h diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 0859e44..10d20f2 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -14,7 +14,7 @@ LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o COBJS-y := misc.o timer.o reset_manager.o system_manager.o -COBJS-$(CONFIG_SPL_BUILD) += spl.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c new file mode 100644 index 0000000..330b4aa --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/timer.h> +#include <asm/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Default state from cold reset is FREEZE_ALL; the global + * flag is set to TRUE to indicate the IO banks are frozen + */ +static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM] + = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN, + FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN}; + +/* Freeze HPS IOs */ +void sys_mgr_frzctrl_freeze_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_value; + u32 reg_cfg_mask; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Freeze channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset = (u32)( + &freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low enrnsl, plniotri + * and niotri signals + */ + reg_cfg_mask = + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * Assert active low bhniotri signal and de-assert + * active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; + } + + /* Freeze channel 3 */ + /* + * Assert active low enrnsl, plniotri and + * niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * assert active low bhniotri & nfrzdrv signals, + * de-assert active high csrdone and assert + * active high frzreg and nfrzdrv signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK; + reg_value + = (reg_value & ~reg_cfg_mask) + | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK + | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * assert active high reinit signal and de-assert + * active high pllbiasen signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value + = (reg_value & + ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK) + | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; +} + +/* Unfreeze/Thaw HPS IOs */ +void sys_mgr_frzctrl_thaw_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_cfg_mask; + u32 reg_value; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Thaw channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset + = (u32)(&freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low bhniotri signal and + * de-assert active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low plniotri and niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(ioctrl_reg_offset, + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; + } + + /* Thaw channel 3 */ + /* de-assert active high reinit signal */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Note: Delay for 40ns at min + * assert active high pllbiasen signals + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); + + /* + * Delay 1000 intosc. intosc is based on eosc1 + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 1000 = 20us + */ + udelay(20); + + /* + * de-assert active low bhniotri signals, + * assert active high csrdone and nfrzdrv signal + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value = (reg_value + | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK) + & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * Delay 33 intosc + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 33 = 660ns ~= 1us + */ + udelay(1); + + /* de-assert active low plniotri and niotri signals */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + + setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * Note: Delay for 40ns at min + * de-assert active high frzreg signal + */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK); + + /* + * Note: Delay for 40ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; +} + diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 74bceab..36a00c3 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/reset_manager.h> #include <spl.h> #include <asm/arch/system_manager.h> +#include <asm/arch/freeze_controller.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,6 +28,10 @@ u32 spl_boot_device(void) void spl_board_init(void) { #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + debug("Freezing all I/O banks\n"); + /* freeze all IO banks */ + sys_mgr_frzctrl_freeze_req(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ @@ -34,6 +39,10 @@ void spl_board_init(void) /* de-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); + debug("Unfreezing/Thaw all I/O banks\n"); + /* unfreeze / thaw all IO banks */ + sys_mgr_frzctrl_thaw_req(); + /* enable console uart printing */ preloader_console_init(); } diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h new file mode 100644 index 0000000..120f20e --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FREEZE_CONTROLLER_H_ +#define _FREEZE_CONTROLLER_H_ + +struct socfpga_freeze_controller { + u32 vioctrl; + u32 padding[3]; + u32 hioctrl; + u32 src; + u32 hwctrl; +}; + +#define FREEZE_CHANNEL_NUM (4) + +typedef enum { + FREEZE_CTRL_FROZEN = 0, + FREEZE_CTRL_THAWED = 1 +} FREEZE_CTRL_CHAN_STATE; + +#define SYSMGR_FRZCTRL_ADDRESS 0x40 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080 +#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040 +#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100 +#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2 + +void sys_mgr_frzctrl_freeze_req(void); +void sys_mgr_frzctrl_thaw_req(void); + +#endif /* _FREEZE_CONTROLLER_H_ */ -- 1.7.9.5

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[U-Boot] [GIT PULL] u-boot-mips/master
by Daniel Schwierzeck 02 Dec '13

02 Dec '13

Hi Tom, please pull some additional fixes for MIPS malta board, thanks. The following changes since commit d19ad726bcd5d9106f7ba9c750462fcc369f1020: Prepare v2014.01-rc1 (2013-11-25 16:49:32 -0500) are available in the git repository at: git://git.denx.de/u-boot-mips.git master for you to fetch changes up to 67d4752d1dae768c7ff381272880d4aceeb62085: malta: set CONFIG_SYS_BOOTM_LEN to 64MB (2013-11-26 21:49:42 +0100) ---------------------------------------------------------------- Paul Burton (4): mips: don't hardcode Malta env baudrate malta: correct UART baudrate malta: enable PIIX4 SERIRQ malta: set CONFIG_SYS_BOOTM_LEN to 64MB arch/mips/include/asm/malta.h | 7 +++++++ arch/mips/lib/bootm.c | 6 ++++-- board/imgtec/malta/malta.c | 12 ++++++++++++ include/configs/malta.h | 3 ++- 4 files changed, 25 insertions(+), 3 deletions(-)

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[U-Boot] [PATCH] Blackfin: remove executable permission of AWK script
by Masahiro Yamada 02 Dec '13

02 Dec '13

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/blackfin/cpu/bootrom-asm-offsets.awk | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 arch/blackfin/cpu/bootrom-asm-offsets.awk diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk old mode 100755 new mode 100644 -- 1.8.3.2

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[U-Boot] Zynq serial - pull request
by Michal Simek 02 Dec '13

02 Dec '13

Hi Tom, this is one pending patch which is around for a while and hasn't been merged yet. Please add it to your tree. Thanks, Michal The following changes since commit d19ad726bcd5d9106f7ba9c750462fcc369f1020: Prepare v2014.01-rc1 (2013-11-25 16:49:32 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git serial for you to fetch changes up to 2785a4ae76330dab5e792d52fc9c449ac3d1072e: serial: zynq: Remove unused #defines (2013-12-02 11:36:36 +0100) ---------------------------------------------------------------- Soren Brinkmann (1): serial: zynq: Remove unused #defines drivers/serial/serial_zynq.c | 4 ---- 1 file changed, 4 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [PULL] u-boot-atmel/master -> u-boot-arm/master
by Andreas Bießmann 02 Dec '13

02 Dec '13

Dear Albert Aribaud, please pull u-boot-atmel/master into u-boot-arm/master. This PR supersedes http://patchwork.ozlabs.org/patch/291044/ The following changes since commit 56eb3da43fab5990a4b7bc118b76c7cae2ceb140: arm, am335x: update for the siemens boards (2013-11-12 09:53:59 -0500) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to d07e2b598a690d6eb75019b379fc4933affe3d2c: arm: atmel: eb_cpux9k2: config clean up (2013-12-01 22:38:53 +0100) ---------------------------------------------------------------- Andreas Bießmann (6): video: remove AT91 legacy API from bus_vcxk i2c: switch from AT91 legacy to ATMEL legacy at91sam9m10g45ek: remove unused CONFIG_AT91_LEGACY snapper9260: remove unused AT91_LEGACY net: remove unused CONFIG_AT91_LEGACY at91: remove all occourances of CONFIG_AT91_LEGACY Bo Shen (8): arm: atmel: sama5d3: correct the ID for DBGU and PIT arm: at91: pm9261: remove undefined bit in mckr arm: atmel: sama5d3: correct the error define of DIV arm: atmel: sama5d3: the offset of MULA is 18 arm: atmel: sama5d3: early enable PIO peripherals arm: atmel: add ddr2 initialization function arm: atmel: sama5d3: spl boot from fat fs SD card arm: atmel: sam9m10g45ek: let CONFIG_SYS_NO_FLASH at proper position Heiko Schocher (1): arm926ejs, at91: add common phy_reset function Jens Scharsig (BuS Elektronik) (1): arm: atmel: eb_cpux9k2: config clean up Wu, Josh (1): ARM: at91: sama5d3: add support for sama5d36 chip arch/arm/cpu/Makefile | 1 + arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/at91/sama5d3_devices.c | 6 +- arch/arm/cpu/armv7/at91/timer.c | 2 +- arch/arm/cpu/at91-common/Makefile | 12 +++ arch/arm/cpu/at91-common/mpddrc.c | 124 +++++++++++++++++++++++ arch/arm/cpu/at91-common/phy.c | 57 +++++++++++ arch/arm/cpu/at91-common/spl.c | 90 ++++++++++++++++ arch/arm/cpu/at91-common/u-boot-spl.lds | 50 +++++++++ arch/arm/include/asm/arch-at91/at91_common.h | 5 + arch/arm/include/asm/arch-at91/at91_pio.h | 33 ------ arch/arm/include/asm/arch-at91/at91_pit.h | 16 --- arch/arm/include/asm/arch-at91/at91_pmc.h | 59 ++--------- arch/arm/include/asm/arch-at91/at91_spi.h | 2 +- arch/arm/include/asm/arch-at91/at91_wdt.h | 21 ---- arch/arm/include/asm/arch-at91/at91cap9.h | 69 ------------- arch/arm/include/asm/arch-at91/at91sam9_smc.h | 60 ----------- arch/arm/include/asm/arch-at91/atmel_mpddrc.h | 115 +++++++++++++++++++++ arch/arm/include/asm/arch-at91/sama5d3.h | 3 + arch/arm/include/asm/arch-at91/spl.h | 20 ++++ board/BuS/vl_ma2sc/vl_ma2sc.c | 18 +--- board/afeb9260/afeb9260.c | 18 +--- board/atmel/at91sam9260ek/at91sam9260ek.c | 19 +--- board/atmel/at91sam9263ek/at91sam9263ek.c | 19 +--- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 19 +--- board/atmel/sama5d3xek/sama5d3xek.c | 91 +++++++++++++++++ board/bluewater/snapper9260/snapper9260.c | 16 +-- board/calao/sbc35_a9g20/sbc35_a9g20.c | 19 +--- board/eukrea/cpu9260/cpu9260.c | 18 +--- board/taskit/stamp9g20/stamp9g20.c | 31 +----- doc/README.at91-soc | 7 ++ drivers/i2c/soft_i2c.c | 2 +- drivers/net/at91_emac.c | 9 -- drivers/video/bus_vcxk.c | 15 --- include/configs/afeb9260.h | 2 +- include/configs/at91sam9260ek.h | 1 + include/configs/at91sam9263ek.h | 1 + include/configs/at91sam9m10g45ek.h | 9 +- include/configs/cpu9260.h | 1 + include/configs/eb_cpux9k2.h | 4 - include/configs/pm9261.h | 6 +- include/configs/sama5d3xek.h | 34 +++++++ include/configs/sbc35_a9g20.h | 1 + include/configs/snapper9260.h | 2 +- include/configs/stamp9g20.h | 1 + include/configs/vl_ma2sc.h | 1 + include/i2c.h | 2 +- 47 files changed, 655 insertions(+), 458 deletions(-) create mode 100644 arch/arm/cpu/at91-common/Makefile create mode 100644 arch/arm/cpu/at91-common/mpddrc.c create mode 100644 arch/arm/cpu/at91-common/phy.c create mode 100644 arch/arm/cpu/at91-common/spl.c create mode 100644 arch/arm/cpu/at91-common/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-at91/atmel_mpddrc.h create mode 100644 arch/arm/include/asm/arch-at91/spl.h

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[U-Boot] [STATUS] Resuming ARM activity
by Albert ARIBAUD 02 Dec '13

02 Dec '13

Hello all, Apologies for my inactivity for the last fifteen days. I am resuming fully today, with PRs being applied first, then pending patches. If anyone wants to draw my attention to some post on the list, just reply to that post adding my e-mail address as "To:" rather than "Cc:" -- this will 'red-flag' the message in my mailer). Amicalement, -- Albert.

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[U-Boot] Compiling a debug version of u-boot on panda board
by Vikram Singh Shekhawat 02 Dec '13

02 Dec '13

Hi all, I want to compile a u-boot with debug enable.But i am getting some problem in that. I am using omap4460 panda board. When i am enabling DEBUG in config file(include/configs/omap4_panda.h). I am getting error that .rodaata not fit in region .sram , sram overflowed (might be because the size of spl image is larger then expected). Is there any way to enable DEBUG to whole u-boot source code. Waiting for your views on this problem.

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[U-Boot] [PATCH v2] dwmmc: make driver usable for non-exynos platforms
by Alexey Brodkin 02 Dec '13

02 Dec '13

There's no point in having of "dwmmc.h" per architecure - we're talking about device driver (DesignWare MMC controller) which is expected to work with any CPU it is attached to. Actually this change should have been an essential part of commit: ======= 6f0b7caa671f92c2d4676c84381d17fb90f7d2cd DWMMC: SMDK5420: Disable SMU for eMMC ======= Or even better I'd prefer all non pure DW MMC functionality (those item in ifdefs) to be moved to corresponding files like "exynos_dw_mmc.c" via call-backs etc. This will keep DW MMC driver clean and simple. As it is said in http://www.denx.de/wiki/U-Boot/DesignPrinciples: ======= 8. Keep it Maintainable Avoid #ifdefs where possible ======= Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Mischa Jonker <mjonker(a)synopsys.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Andy Fleming <afleming(a)gmail.com> Cc: Alim Akhtar <alim.akhtar(a)samsung.com> Cc: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Changes compared to initial version: Instead of modification of headers only disable some parts of code with ifdefs. --- drivers/mmc/dw_mmc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 1e0f72b..fdae40b 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -11,7 +11,9 @@ #include <mmc.h> #include <dwmmc.h> #include <asm-generic/errno.h> +#ifdef CONFIG_EXYNOS5420 #include <asm/arch/dwmmc.h> +#endif #define PAGE_SIZE 4096 @@ -302,6 +304,7 @@ static int dwmci_init(struct mmc *mmc) struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 fifo_size; +#ifdef CONFIG_EXYNOS5420 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { dwmci_writel(host, EMMCP_MPSBEGIN0, 0); dwmci_writel(host, EMMCP_SEND0, 0); @@ -311,6 +314,7 @@ static int dwmci_init(struct mmc *mmc) MPSCTRL_NON_SECURE_READ_BIT | MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); } +#endif dwmci_writel(host, DWMCI_PWREN, 1); -- 1.8.4.2

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[U-Boot] [PATCH] mmc: dw_mmc: remove the exynos specific code in dw-mmc.c
by Jaehoon Chung 02 Dec '13

02 Dec '13

dw-mmc.c is the general driver file. So, remove the exynos specific code at dw-mmc.c. Instead, exynos specific cod can be move into exynos-dw_mmc.c. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/dw_mmc.c | 12 ++---------- drivers/mmc/exynos_dw_mmc.c | 14 ++++++++++++++ include/dwmmc.h | 1 + 3 files changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 1e0f72b..38f50ce 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -11,7 +11,6 @@ #include <mmc.h> #include <dwmmc.h> #include <asm-generic/errno.h> -#include <asm/arch/dwmmc.h> #define PAGE_SIZE 4096 @@ -302,15 +301,8 @@ static int dwmci_init(struct mmc *mmc) struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 fifo_size; - if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { - dwmci_writel(host, EMMCP_MPSBEGIN0, 0); - dwmci_writel(host, EMMCP_SEND0, 0); - dwmci_writel(host, EMMCP_CTRL0, - MPSCTRL_SECURE_READ_BIT | - MPSCTRL_SECURE_WRITE_BIT | - MPSCTRL_NON_SECURE_READ_BIT | - MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); - } + if (host->board_init) + host->board_init(host); dwmci_writel(host, DWMCI_PWREN, 1); diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index a0f1511..b3e5c5e 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -34,6 +34,19 @@ unsigned int exynos_dwmci_get_clk(int dev_index) return get_mmc_clk(dev_index); } +static void exynos_dwmci_board_init(struct dwmci_host *host) +{ + if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { + dwmci_writel(host, EMMCP_MPSBEGIN0, 0); + dwmci_writel(host, EMMCP_SEND0, 0); + dwmci_writel(host, EMMCP_CTRL0, + MPSCTRL_SECURE_READ_BIT | + MPSCTRL_SECURE_WRITE_BIT | + MPSCTRL_NON_SECURE_READ_BIT | + MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); + } +} + /* * This function adds the mmc channel to be registered with mmc core. * index - mmc channel number. @@ -65,6 +78,7 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) #ifdef CONFIG_EXYNOS5420 host->quirks = DWMCI_QUIRK_DISABLE_SMU; #endif + host->board_init = exynos_dwmci_board_init; if (clksel) { host->clksel_val = clksel; diff --git a/include/dwmmc.h b/include/dwmmc.h index 6c91143..a02dd67 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -141,6 +141,7 @@ struct dwmci_host { struct mmc *mmc; void (*clksel)(struct dwmci_host *host); + void (*board_init)(struct dwmci_host *host); unsigned int (*get_mmc_clk)(int dev_index); }; -- 1.7.9.5

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[U-Boot] [PATCH] trats: enable dfu and thor protocol for Tizen download
by Piotr Wilczek 02 Dec '13

02 Dec '13

Trats2 config is updated to support DFU mode. Malloc pool must be increased for DFU buffer allocation. Signed-off-by: Piotr Wilczek <p.wilczek(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> CC: Minkyu Kang <mk7.kang(a)samsung.com> --- This patch is based on http://patchwork.ozlabs.org/patch/289378/ include/configs/trats2.h | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 66b1c95..52bb5e5 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -65,10 +65,9 @@ #define CONFIG_DISPLAY_CPUINFO -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20)) +#include <asm/sizes.h> +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) /* select serial console configuration */ #define CONFIG_SERIAL2 @@ -100,6 +99,7 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_I2C #define CONFIG_CMD_MMC +#define CONFIG_CMD_DFU #define CONFIG_CMD_GPT #define CONFIG_CMD_PMIC @@ -115,12 +115,19 @@ /* USB Composite download gadget - g_dnl */ #define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M #define CONFIG_DFU_FUNCTION #define CONFIG_DFU_MMC +/* TIZEN THOR downloader support */ +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION + /* USB Samsung's IDs */ #define CONFIG_G_DNL_VENDOR_NUM 0x04E8 #define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D #define CONFIG_G_DNL_MANUFACTURER "Samsung" /* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */ @@ -165,6 +172,12 @@ "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ +#define CONFIG_DFU_ALT \ + "u-boot mmc 80 400;" \ + "uImage ext4 0 2;" \ + "exynos4412-trats2.dtb ext4 0 2;" \ + ""PARTS_ROOT" part 0 5\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \ @@ -197,6 +210,7 @@ "mmcrootpart=5\0" \ "opts=always_resume=1\0" \ "partitions=" PARTS_DEFAULT \ + "dfu_alt_info=" CONFIG_DFU_ALT \ "uartpath=ap\0" \ "usbpath=ap\0" \ "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ -- 1.7.9.5

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